JPH03217137A - Self-diagnostic circuit - Google Patents

Abstract

PURPOSE:To always obtain correct diagnostic results by sending information indicating whether data to be diagnosed is normal or not from a device where a unit to be diagnosed is housed and providing a pseudo synchronism preventing circuit and controlling the operation of a frame detecting means in accordance with the state of information by this circuit. CONSTITUTION:A pattern generating circuit 5 outputs diagnostic data at the time of input of a self-diagnosis starting command, and the device 6 processes this diagnostic data and sends it as data to be diagnosed. After detecting a designated pattern in the data to be diagnosed from the device 6 continuously N-number of times to acquire the synchronism, a frame detecting means 3 compares the diagnostic data and the data to be diagnosed with each other; and if the number of discordances per prescribed time exceeds a set value, the means 3 sends an error pulse. The pseudo synchronism preventing circuit 4 starts the operation at the time of input of the self-diagnosis starting command, and the operation of the frame detecting means 3 is turned on to perform the self-diagnosis of the unit to be diagnosed when the information from the device 6 is normal, and it is not turned off and this self-diagnosis is not performed when this information is abnormal.

Description

[Detailed Description of the Invention] [Summary] For example, when performing self-diagnosis regarding a self-diagnosis circuit used when diagnosing an abnormality or failure of a unit in a multiplexing/separating device. The purpose is to always obtain correct diagnostic results, and when a self-diagnosis start command is input, a pattern generation circuit outputs diagnostic data, and after processing the diagnostic data from the pattern generation circuit, it outputs the diagnostic data. After detecting and synchronizing the specified pattern in the diagnostic data from the device and the device that sends out data N times in a row, the diagnostic data and the diagnostic data are compared, and the A self-diagnosis circuit that self-diagnoses abnormality or failure of the device by providing a frame detection means that sends an error pulse when the number of discrepancies exceeds a set value, which detects whether the data to be diagnosed from the device is normal or not. At the same time, when the self-diagnosis start command is input, the operation is started, and when the information from the device is normal, the operation of the frame detection means is turned on to perform self-diagnosis of the unit to be diagnosed. and when the information from the device is abnormal, the operation of the frame detection means is turned off and a control signal is sent to control the operation of the frame detection means so as not to perform self-diagnosis of the unit to be diagnosed. The configuration is such that a pseudo synchronization prevention circuit is provided.

[Industrial application field]

The present invention relates to a self-diagnosis method used, for example, when diagnosing an abnormality or failure of a unit in a multiplexing/separating device.

For example, when powering on a multiplexing/demultiplexing device and checking for abnormalities or failures in the units housed in this device through self-diagnosis without using a measuring device, etc., it is necessary to ensure that correct diagnostic results are always obtained. is necessary.

[Conventional technology]

FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an explanatory diagram of self-diagnosis using the conventional example. Below, channels 1 to 4
The operations shown in FIGS. 6 and 7 will be explained assuming that multiplexing/demultiplexing is performed.

(1) Data transmission operation (see Fig. 7) Data on channels 1 to 4 (hereinafter abbreviated as CHI-CH4) is transmitted by switches SW1 to SW1 in the dotted line state.
The signals are applied to the multiplexing/demultiplexing section 22 via SW4, where they are multiplexed, a high-order group synchronization signal is added thereto, and the signals are sent out to the transmission line via the switch SWe shown in the dotted line.

On the other hand, the multiplexed data from the transmission line passes through the switch SLo indicated by the dotted line, detects a high-order group synchronization signal in the multiplexing/demultiplexing part and obtains synchronization, and then is separated into CH 1 to CH 4, and then transferred to the switch SWa. - Output through SWs.

(2) Self-diagnosis operation (see FIGS. 7 and 6) Since the self-diagnosis start command S1 is sent from the microcomputer 24 to the low-order group loop pack section 21, the high-order group loop pack section 23, and the self-diagnosis circuit 1, Switch SW+ in the low-order group loop pack part and the high-order group loop pack part ~
The connections of SWi, SWo, and SW+o change from dotted lines to solid lines, and loop pack becomes possible.

Furthermore, in response to the input self-diagnosis start command S1, the self-diagnosis circuit 1 shown in FIG. The circuit 1l is also brought into operation by the above start command.

This PN data S2 is multiplexed in the multiplexing/demultiplexing section 22 via switch SW+ in the low-order group loopback shown in FIG. 7, but this multiplexed data is multiplexed via SWs and SLo in the high-order group loop pack. , is again input to the multiplexing/demultiplexing section, and the PN data is separated. It should be noted that addition and detection of higher-order group synchronization signals are also performed when multiplexing/separating PN data.

The separated PN data is added to the multiplexing/demultiplexing section via switches SW6 and SW2, and after the same processing as above is performed, it is input to the multiplexing/demultiplexing section via switches swg, sw, and o, where it is converted into PN data. is separated, SWe+SW
3 to the multiplex/separate section again.

This is repeated, and the PN data separated via the SWs (hereinafter referred to as PN data to be diagnosed S3) is input to the frame synchronization circuit l1 in the self-diagnosis circuit shown in FIG.

Here, the frame synchronization circuit 11 includes a specified pattern detection section Ill for detecting a specified pattern in the PN data to be diagnosed.
It has a pattern generation section 112 and a coincidence/mismatch detection section 113 having the same configuration as the pattern generation circuit l3.

Therefore, when the above-mentioned PN data to be diagnosed S3 is input, the designated pattern detection part Ill detects a designated pattern in the PN data to be diagnosed S3, for example, 1101000, and the pattern generation part 112 is activated by the detection signal. If the specified pattern can be detected consecutively, for example twice, the error counter l2 is activated to establish synchronization, and the PN data to be diagnosed S3 and the PN data from the pattern generation part are detected bit by bit in the matching/mismatching part. Check for match/mismatch.

At this time, if there is a mismatch, the mismatch result is sent to an error counter, so this counter counts the number of mismatches and sends out an error when the number of mismatches exceeds a set value within a predetermined time.

[Problem to be solved by the invention]

Here, for example, if the above-mentioned high-order group synchronization signal is inserted every 1200 bits, and the specified pattern is inserted every 2' = 128 bits, and the number of protection stages is the same, the time required to detect the high-order group synchronization pattern in the multiplexing/demultiplexing part is is longer than the time it takes for the frame synchronization circuit to detect the specified pattern.

Therefore, even though the multiplexing/demultiplexing part is in a hunting state and the data to be diagnosed S3 is not normal, the frame synchronization circuit 11 detects a designated pattern from this data S3 and enters the synchronization established state, and the PN to be diagnosed which is not normal Data S
There is a problem that there are cases where an incorrect judgment is made when making a diagnosis using 3.

An object of the present invention is to always obtain correct diagnostic results when performing self-diagnosis.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 5 is a pattern generation circuit that outputs diagnostic data when a self-diagnosis start command is input, and 6 is a device that processes the diagnostic data from the pattern generation circuit and then sends it out as data to be diagnosed.

In addition, in 3, the specified pattern in the diagnosed data from the device is detected N times in succession and synchronized, and then the diagnosed data and the diagnosed data are compared to determine the number of discrepancies per predetermined time. 4 is a frame detection means that sends out an error pulse when exceeds a set value, and 4 starts operation when a self-diagnosis start command is input, and when the information from the device is normal, the frame detection means starts operating. The frame detection means is turned on to cause the unit to be diagnosed to perform self-diagnosis, and when the information from the device is abnormal, the frame detection means is turned off to prevent the self-diagnosis of the unit to be diagnosed. This is a pseudo-synchronization prevention circuit that sends out a control signal to control the operation of the means.

[Effect]

The present invention is configured to send out information indicating whether or not the data to be diagnosed is normal from a device accommodating the unit to be diagnosed, and is also provided with a pseudo synchronization prevention circuit, and this circuit responds to the state of the information. to control the operation of the frame detection means.

For example, if the device is a multiplexing/separating device and the unit to be diagnosed is a multiplexing section and a separating section, the diagnostic data is multiplexed with other signals in the multiplexing section, but at this time, the multiplexed data is combined with a high-order group synchronization signal. is added. On the other hand, the separation section detects the high-order group synchronization signal in the multiplexed data and then separates it to extract the data to be diagnosed.

At this time, information indicating whether or not a high-order group synchronization signal has been detected is sent from the device to the pseudo synchronization prevention circuit. If this information indicates that a synchronization signal has been detected, the false synchronization prevention circuit determines that the data to be diagnosed is normal, turns on the operation of the frame detection means, and diagnoses the abnormality or failure of the unit to be diagnosed.

However, if no synchronization signal is detected, it is determined that the data to be diagnosed is not normal data, and the frame detection means is not turned on.

Therefore, correct self-diagnosis results can always be obtained.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram of the pseudo synchronization prevention circuit in FIG. 2, FIG. 4 is an explanatory diagram of the operation of FIG. 3, and FIG. An explanatory diagram of the self-diagnosis used is shown.

Here, the symbols on the left side of FIG. 4 indicate the waveforms of the portions with the same l0 symbol in FIG. 3. Note that the same reference numerals indicate the same objects throughout the figures. Further, the frame synchronization circuit 31 and the error counter 32 are the constituent parts of the frame detection means 3, and the flip-flop 41. 42 NAND gate 43, A
An ND gate 44 represents a component of the pseudo synchronization prevention circuit 4.

The operation shown in FIG. 2 when performing self-diagnosis will be described below with reference to FIGS. 3 to 5.

First, a self-diagnosis start command S1 from the microcomputer 24 in FIG.
The signal is input to the higher-order group loop pack section 23, the pattern generation circuit 5 in the self-diagnosis circuit, and the pseudo-synchronization prevention circuit 4. Therefore, the low-order group loop pack part and the high-order group loopback part are connected to internal switches SW1 to SWs, SWe, SW+.
o is switched from the dotted line state to the solid line state, and the pattern generation circuit and pseudo synchronization prevention circuit are turned on.

The pattern generation circuit 5 is a circuit that generates, for example, a 7-stage PN pattern, and uses the PN pattern generated here as diagnostic data (hereinafter abbreviated as PN data S2) l 1 and generates the low-order group loop pack portion 2l. 5 to the multiplexing/demultiplexing section 22 of FIG.

Therefore, the multiplexing/demultiplexing part is CH
After multiplexing the data as I data and adding a high-order group synchronization signal to generate multiplexed data, the multiplexed data is added to the multiplexing/demultiplexing section again via the high-order group loop pack section to detect the high-order group synchronization signal. , this PN data is separated.

Then, the separated PN data is multiplexed as CH2 data. After repeating this until, for example, CH4,
Separate the PN data and store it as the second PN data to be diagnosed S3.
It is added to the frame synchronization circuit 3l shown in the figure.

Further, when a high-order group synchronization pattern is detected, a high-order group synchronization detection signal S6 is sent to the pseudo synchronization prevention circuit 4.

Here, when the self-diagnosis start command S shown in FIG.
After being taken in using the clock CK shown in FIG.

■ 2 And the output of terminal Q of D-FF 41 and D-FF 4
When NAND is performed with the output of terminal *Q of 2 using a NAND gate, an output as shown in Fig. 4-1 is obtained, and this is the result of the AN
It is added to the D gate 44 (see Fig. 4-1 and ■).

When this AND gate receives the high-order group synchronization detection signal from the multiplexing/demultiplexing section shown in Figure 4-0, it sends an operation-on control signal as shown on the right side of Figure 4-1 to the frame synchronization shown in Figure 2. It is sent to circuit 3l.

Then, the frame synchronization circuit starts operating and, in the same way as above, from the input PN data S, to be diagnosed, for example, 11
Detects 01000. As a result, a pattern generation portion (not shown) having the same configuration as the pattern generation circuit is turned on, and if 1101000 can be detected, for example, twice in a row, synchronization is established and the error counter 32 is turned on.

In addition, a match/mismatch detection part (not shown) is used to check the match/mismatch between the diagnosed PN data S3 and the output of the pattern generation part.
The check is performed bit by bit, and if there is a mismatch, the check result is sent to the error counter 32. Therefore, the error counter sends out an error pulse when the number of mismatches exceeds a predetermined number within a predetermined time.

If the high-order group synchronization signal from the multiplexing/demultiplexing section is not input, the control signal for turning off the operation shown on the left side of Fig. 4 (1) is sent from the pseudo synchronization prevention circuit to the frame synchronization circuit. Becomes operated state.

That is, since the frame synchronization circuit is operated after the multiplexing/demultiplexing section detects a high-order group synchronization pattern, correct diagnosis results can always be obtained when performing self-diagnosis.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage that correct diagnosis results can always be obtained when performing self-diagnosis.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, 1 4 Fig. 3 is a circuit diagram of the pseudo synchronization prevention circuit in Fig. 2, and Fig. 4 is a block diagram of the pseudo synchronization prevention circuit in Fig. 3. 5 is an explanatory diagram of self-diagnosis using FIG. 2, FIG. 6 is a block diagram of a conventional example, and FIG. 7 is an explanatory diagram of self-diagnosis using the conventional example. In the figure, 3 is a frame detection means, 4 is a pseudo synchronization prevention circuit, 5 is a pattern generation circuit, and 6 is a device. l 5 Principle software diagram of the present invention ■ θ■ -274-

Claims (1)

[Scope of Claims] A pattern generation circuit (5) that outputs diagnostic data when a self-diagnosis start command is input, and a device (6) that processes the diagnostic data from the pattern generation circuit and then sends it out as data to be diagnosed. ), and after successively detecting the specified pattern in the diagnostic data from the device (6) N times (N is a positive integer) and establishing synchronization, the diagnostic data and the diagnostic data are compared. and frame detection means (3) for transmitting an error pulse when the number of discrepancies per predetermined time exceeds a set value.
) in a self-diagnosis circuit that self-diagnoses abnormalities or failures in the device (6), which transmits information indicating whether the data to be diagnosed is normal or not, and starts operation when the self-diagnosis start command is input. ,
When the information from the device (6) is normal, the frame detection means is turned on to perform self-diagnosis of the unit to be diagnosed, and when the information from the device is abnormal, the frame detection means is turned on. A self-diagnosis characterized in that a pseudo synchronization prevention circuit (4) is provided which sends a control signal for controlling the operation of the frame detection means so as to turn off the operation and prevent the self-diagnosis of the unit to be diagnosed. .