JPH03217952A - Memory block control system - Google Patents

Abstract

PURPOSE:To improve the processing ability by controlling the busy/idle state of a real memory block based on a program and controlling an address converter. CONSTITUTION:An address converter 24 is set between an address bus 23 led to an 8086 CPU 21 and an address bus 25 led to a memory 26. If an address set on the bus 23 via the CPU 21 is equal to the address buses of the prescribed program memory block access areas 13 and 17, the address is converted into the address of the corresponding real memory block 19. This converted address is shown to the memory 26 via the bus 25. Thus the memory 26 performs the transfer of data to the CPU 21 via a data bus 22 and according to the address shown by the converter 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory block management method for managing memory blocks, which are common resources of the system, in a software system using an 8086 CPU.

[Conventional technology]

In the conventional 8086 CPU system, there are the following three methods for managing memory blocks that exceed segments. That is, when an individual program accesses a memory block, the first method is to switch to and access the segment of the memory block, and the second method is to handle the address used in the program system as 32 bits, which is the sum of the segment and offset. A third method is to provide a memory block used by an individual program in the data segment of that program, and when transferring data in the memory block to another program, copy the data to the memory block of the destination program.

[Problem to be solved by the invention]

The conventional memory block management methods described above each have the following problems. That is, in the first method, each program must switch segments, which complicates the processing.

In the second method, which is mainly used in high-level languages, segment switching occurs in response to memory block accesses, resulting in a reduction in processing performance.

Furthermore, in the third method, memory blocks are allocated to individual programs, so although the complexity of segment switching can be avoided, the memory utilization efficiency of the entire system deteriorates. Furthermore, when transferring data between programs, data must be copied from memory block to memory block between segments, resulting in a reduction in processing performance.

[Means to solve the problem]

The memory block management method of the present invention, in a system using a microprocessor, has a virtual memory block access area provided in a data segment of each program, a real memory block provided commonly to the system, and the virtual memory The present invention includes an address translation device that associates an address of a block access area with an address of the real memory block, and a program that controls the address translation device by managing free/occupied spaces in the virtual memory block access area and the real memory block. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a memory configuration diagram according to an embodiment of the memory block management method of the present invention.

In FIG. 1, program A is composed of a program A code section 11 and a program A data section 12, and a program A memory block access area 13 is placed in a program A data segment 14. Here, the program A data segment is a data area that program A can access, and program A cannot access memory outside this range. When program A accesses the program A memory block access area 13, the address at that time is converted to the address of the real memory block 19. Further, a program B having a separate segment from program A also exists on the memory, and its explanation is the same as that of program A.

FIG. 2 is a configuration diagram showing the housing position of an address translation device that associates the address of the memory block access area and the address of the real memory block in FIG. 1.

Address translation device 24 includes 8086 CPU 21 and memory 2
6 address buses, 8086CPU2 1
If the address on the address bus 23 from 13.17 is an address in a predefined memory block access area 13.17, it is converted to the corresponding address in the real memory block 19 and shown to the memory 26 via the address bus 25. . The memory 26 is connected to the 8086 CPU via the data bus 22 according to the address indicated by the address translation device 24.
21 and exchanges data.

3 and 4 are flowcharts showing the operation of a program that controls the address translation device.

An example in which program A uses memory blocks will be explained. When program A requests the address translation device control program to reserve a memory block, the address translation device control program reserves a free area in the program A memory block access area 13 as shown in FIG. 3 (step 31). Then, it is determined whether or not the securing has been successful (step 32), and if the securing has been successful, the process proceeds to step 33. Next, a free area in the real memory block 19 is secured (step 33).

Next, determine whether the securement was successful or not (Step 34)
, if the securing is successful, proceed to step 35. Then, the address translation device 2 associates the secured program A memory block access area 13 with the real memory block 19.
4 (step 35).

Furthermore, when program A finishes using the memory block, it requests the address translation device program to release the memory block. As shown in FIG. 4, the address translation device control program releases the program A memory block access area 13 corresponding to the requested memory block (step 41), and releases the real memory block 19 (step 42). Then, the program A memory block access area 13 for the address translation device 24
and to cancel the association between the real memory blocks 19 (step 43).

〔Effect of the invention〕

As explained above, the present invention has the following effects.

That is, individual programs can access real memory block areas prepared by the system simply by preparing a memory block access area of the size necessary for simultaneous access. In addition, since the memory access area and the system-shared real memory block are associated with each other when the memory block is acquired, programs that are memory block users access their own data segments, which increases the complexity of segment switching and segment Decrease in processing capacity due to switching can be avoided. Furthermore, the real memory block can be referenced by any program in the system, and data can be transferred between programs without copying between segments, so it is possible to avoid a reduction in processing performance due to copy processing.

[Brief explanation of drawings]

FIG. 1 is a memory configuration diagram according to an embodiment of the memory block management system of the present invention, FIG. 2 is a configuration diagram showing the housing position of the address translation device in FIG. 1, and FIGS. 3 and 4 are the address translation device 3 is a flowchart showing the operation of a management program that performs. 11...Program A code section, 12...Program A data section, 13...Program A memory block access area, 14...Program A data segment, 15...Program B code section, 16... - Program B data section, 17... Program B memory block access area, 18... Program B data segment, 19... Real memory block, 21...
8086 CPU, 22... Data path, 232 5... Address bus, 24... Address translation device, 2 6... Memory.

Claims (1)

[Claims] In a system using a microprocessor, a virtual memory block access area provided in a data segment of each program, a real memory block provided commonly to the system, an address of the virtual memory block access area, and the real memory A memory block management method comprising: an address translation device that associates addresses of blocks; and a program that controls the address translation device by managing free/occupied areas of the virtual memory block access area and the real memory block.