JPH03217956A - Data writing control system - Google Patents

Abstract

PURPOSE:To write data into a local memory in a single cycle by performing the division of the data received via a data bus into local memories and the generation of write addresses to those local memories corresponding to each data within a single cycle. CONSTITUTION:The data received via a data bus 2 are divided into the write data units by a data dividing circuit 6 within the single unit access time. These write data units are applied to the data write input of the corresponding local memories 41-4n via the corresponding write data unit input circuits 81-8n respec tively. Meanwhile the write addresses are supplied to the write address inputs of the memories 41-4n from a write address generating circuit 10 within the single unit access time. Then the write data units are written into the memories 41-4n.

Description

[Detailed Description of the Invention] [Table of Contents] [Overview] [Industrial Application Fields] [Prior Art] [Problems to be Solved by the Invention] [Means for Solving the Problems] [Examples] Parts of the Present Invention Diagram showing an embodiment (Figure 2) [Effects of the invention] [Overview] Data write control from a data bus that can directly transfer data from an external data bus, etc. to a local memory with a data access width different from the data width of the external data bus. The purpose of this method is to transfer data to a local memory, etc. at the same speed as the data bus transfer speed. In a digital data processing system that writes data from a bus, a data division circuit divides data from the data bus into each of data write inputs of a plurality of local memories within one unit access time in response to a division control signal; a write data unit input circuit that connects the output of the data division circuit to the data write input of the corresponding memory in response to an input control signal; and a write data unit input circuit that connects the output of the data division circuit to the data write input of the corresponding memory; a write address generation circuit that outputs a write address of each local memory determined by the input address to a corresponding address input within l unit access time, and a write input control circuit that outputs a division control signal and an input control signal in response to a write access. It was composed of

[Industrial application field]

The present invention relates to a data write control method that allows data to be directly transferred from an external data bus or the like to a local memory having a data access width different from the data width.

In a data processing system, data to be processed therein is transferred between required components via a data bus to perform necessary data processing. The demand for higher data processing speeds has manifested itself in demands for faster operating speeds of each component involved in data processing. Data buses are also subject to demands for higher operating speeds. The demand for faster data buses is
This is a request to expand the data width of the external data bus of the processor.

If the data width of the external data bus is expanded to match the bus width within the processor, not only will the amount of hardware increase, but the basic calculation speed of the processor will decrease. As a means of achieving this balance, a data transfer system within the system is constructed by making the data width of the external data bus and the data width of the internal data bus different.

The data bus currently in standard use is about 4 bytes.

[Conventional technology]

As mentioned above, when the data width of the external data bus and the data width of the internal data bus in the system are different, a read buffer is provided between the external data bus and the internal data bus to allow data to be transferred to each other. This is done to absorb the difference in data width. A memory or the like is connected to the external data bus, and a register, a local memory, or the like is connected to the internal data bus.

[Problem to be solved by the invention]

When a system configuration is configured in which a read buffer is provided between the external data bus and the internal data bus, it is necessary to set the external data in the read buffer and then divide the data into internal data bus widths and transfer them to internal memory, etc. No. Furthermore, in transferring data from an internal memory or the like to an external data bus, it is necessary to set data corresponding to the width of the external data bus in a read buffer and then read the data from there. Therefore, although the transfer speed of the external data bus can be improved, there is almost no improvement in the processing speed of the data transfer command itself.

The present invention was created in view of such problems, and an object of the present invention is to provide a data write control method that can transfer data to an internal memory or the like at the same speed as the data bus transfer speed.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the present invention provides data on the data bus 2. Next, the digital data processing system writes data from the data bus 2 to a plurality of local memories 4 = (i = 1.2, . . . , n) of the same write data unit whose width is smaller by a predetermined value. It is configured by providing the following components. The components are configured to divide the data bus 2 in response to a split control signal.
a data division circuit 6 that divides data from the data into each of the data write inputs of the plurality of local memories 4i within one unit access time; A write data unit input circuit 8■ is connected to the data write input, and is connected to the address input of each of the plurality of local memories 4i, and corresponds to the write address of each local memory determined according to the division in write access. These are a write address generation circuit 10 that outputs an output to the address input within the one unit access time, and a write input control circuit 12 that outputs the division control signal and the input control signal in response to the write access.

[Operation] Data transferred from the data bus 2 and input to the data division circuit 6 is divided into write data units within one unit access time by the data division circuit 6.

Dummy pits may be included in some or all of the divided write data units. Each write data unit is applied to the data write input of its corresponding local memory via a corresponding write data unit input circuit 8.

Since a write address is supplied from the write address generation circuit 10 to the write address input of each local memory within the one unit access time, the storage location of the local memory specified by the write address is stored in the local memory. The write data unit input to the data write input of is written.

Therefore, the data transferred via data bus 2 to each local memory in write data units different from the data width of data bus 2 is subject to software control one by one by the software control system in the digital data processing system. Writing can be performed within the one unit access time without any need.

[Example] FIG. 2 shows an example of the present invention. This embodiment is an embodiment in a computer system, where the number of local memories is n, and the number of lower bits of the local memory address is represented by N, fog. When configuring a computer system with the relationship n - N, the number of memories is 2, l
og. This is an example for the case where 2=N=1.

The external data bus 20 is connected to a shifter 22,
The external data bus 20 includes, for example, a memory (not shown), etc.
is connected. Shifter 22 is connected to one input of multiplexer 30 via internal data bus 24 and to one input of multiplexer 32 via internal data bus 26. The shift control signal is given to the shifter 22 from the control section 34 .

? , the other input of multiplexers 30 and 32 has an ALU
36 outputs are provided via internal data bus 28. The output of multiplexer 30 is applied to the write data input of local memory 4I, and the output of multiplexer 32 is applied to the write data input of local memory 42. Local memory 41 and local memory 4
The output of (2) is supplied to the ALU 36 via the multiplexer 46.

The upper bit address output of the local memory address set area 40 is directly supplied to the write address input of the local memory 4■, but the output of the upper bit address of the local memory 4I is supplied through the +1 addition circuit 42 or as is. It is supplied via multiplexer 44.

The LSB set area 52 of the local memory address set area 40 is supplied to the shifter 22 directly or via an inverter 54 as the shift control signal. OR circuit 5
6 and the output of the inverter 54 are output from the AND circuit 60 according to the presence or absence of the output of the write signal cent area 50. local memory 4
LSB set area 52 supplied to I and passed through OR circuit 58
The output of the data set instruction signal set area 48 is supplied to the local memory 42 via an AND circuit 62 depending on whether or not there is an output of the write signal set area 50.

In FIG. 2, the external data bus 20 corresponds to the data bus 2 in FIG.
This corresponds to the local memory 4i in the figure.

Shifter 22 corresponds to the data division circuit shown in FIG. The multiplexer 30, 32 corresponds to the write data input circuit 8i in FIG. The control section 34, local memory address sent area 40, LSB set area 52, +1 addition circuit 42, and multiplexer 44 correspond to the write address generation circuit 10 in FIG. The LSB set area 52, inverter 52, and data set instruction signal set area 48 are as follows:
This corresponds to the write input control circuit 12 in FIG.

The data transfer operation between different data buses in the above system configuration will be explained below.

First, what about operations in computer systems? Next, we will explain the operation when it becomes necessary to read data between internal memories.

The data read commands from the local memory 41 and the local memory 42 are set in the command register 38 under the control of the control section 34. A local memory address is set in the local memory address set area 40 of the instruction register 38, and P=W="0'" is set in the data set instruction signal set area 48 and write signal set area 50.W= Since the signal is "'0", both the signals from the AND circuit 60 and the AND circuit 62 are "'0".
″, local memory 41 and local memory 4■
Both are read operations. Then, when the LSB of the local memory address in this read is a value of 0, the address (entry address) excluding the LSB of the local memory address is the LSB.
B set area 52 (L of the local memory address
SB (i.e. 0) and data set instruction signal set area 48
The multiplexer 44 controlled by the output of (P or p)? On the other hand, when the LSB of the local memory address has a value of 0, the address excluding the LSB of the local memory address is directly supplied to the address input of the local memory 4i. Provided to address input. Therefore, in any case, local memo U4i or local memory 4
2, the data at the entry address (the address excluding the LSB of the local memory address) specified by the data read command is read from the local memory 41 or the local memory 4■, and is stored in the LSB set area 52. It is input to the ALU 36 via a multiplexer 46 controlled by the output.

Next, in operation in the computer system, A
The operation when it becomes necessary to write data from LU36 to the internal memory will be explained.

The data write commands from the local memory 4i and local memory 42 are set in the command register 38 under the control of the control section 34. Is the local memory address set for that instruction register 38? The area 40 contains the local memory address, and the data set instruction signal set area 48 and write signal set area 50 contain P="Q II,
W == I "1'" is set. Since W="1"', the signals from the AND circuit 60 and the AND circuit 62 both become "1", and both the local memory 4i and the local memory 42 perform a write operation.

Then, when the LSB of the local memory address in this write is a value of 0, the address excluding the LSB of the local memory address is the LSB.
Set area 52 (LSB of the local memory address
, that is, 0) and data set instruction signal set area 48 (P
, or p)
4 to the address input of the local memory 4i, whereas the LSB of the local memory address is 0.
, the address excluding the LSB of the local memory address is directly stored in the local memory 4.
Supplied to the address input of ■. Therefore, in any case, the write data given from the ALU 36 via the multiplexer 30 and the multiplexer 32 controlled by the output of the data center instruction signal set area 48 is sent to the local memory 4i or the local memory 42. Entry address specified by the data write command (LS of the local memory addresses)
Local memory 4i specified by address (excluding address B)
, or written to local memory 42.

In the operation of a computer system, in addition to writing data to or reading data from internal memory as described above, there is a need to transfer data between external memory and local memory. Explain the operation.

First, the operation of writing data from the external memory to the local memory via the external data bus 20 will be described. In this data write operation, the data write command is set in the command register 38 under the control of the control unit 34. The local memory address set for that instruction register 38? 40 has a local memory address,
Furthermore, P=W='“1゛゜ is set in the data set instruction signal set area 48 and the write signal set area 50, but the write address (local memory address) set in the local memory address set area 40 is teeth,
Address (starting address) for the first data unit (for example, 4 bytes) written in the unit of access to the local memory, of the write data to be written to the local memory 4I and local memory 4■ by the data write command. It is. Since W="1", the signals from the AND circuit 60 and the AND circuit 62 are
Both become "'1", and both the local memory 4l and the local memory 42 perform write operations. Then, L of the local memory address in this write is
When SB has a value of 0, the upper 16 bits of the 32-bit data transferred via the external data bus 20 in the shifter 22 are transferred via the internal data bus 24, and are further transferred to the data set instruction signal set area. By the output of 48? The lower 16 bits of the 32-bit data are supplied to the local memory 4i via the controlled multiplexer 30, and the lower 16 bits are supplied via the internal data bus 26 to the multiplexer controlled by the output of the data set instruction signal set area 48. Local memory 4 via 32
supplied to t. At this time, the addresses supplied to the local memory 4I and the local memory 4■ are the following addresses. That is, the address excluding the LSB of the local memory address is set in the LSB set area 52 (LSB of the local memory address=0, that is, a='"
0'') and data set instruction signal set area 48 (P='
Multiplexer 4 controlled by the output of “1゛゜)
4 to the address input of the local memory 4i, and the address excluding the LSB of the local memory address is directly supplied to the local memory 4i.
is fed to the address input of
The upper 16 bits input to the write data input of the local memory 4i are the local memory 4i? The lower 1 data is written to the data write position specified by the entry address supplied to the address input of 41, and is also input to the write data input of local memory 4.
The 6 bits are written to the data write position specified by the entry address supplied to the address input of the local memory 4.

In addition, under the condition that P=W="1" is set in the data set instruction signal set area 48 and the write signal set area 50, the LSB of the local memory address is
When the value of a is 1 (a = "l'"), the shifter 22 that responds to the signal of a = "1" applies a 16-bit circular shift to the 32-bit data from the external data bus 20. , the upper 16 bits of the 32-bit data are supplied to the local memory 42 via the internal data bus 26 and further via the multiplexer 32 controlled by the output of the data sesoto instruction signal sent area 48, and the 32-bit data Of these, the lower 16 bits are internal data bus 2? The signal is further supplied to the local memory 4i via a multiplexer 30 controlled by the output of the data set instruction signal set area 48.

At this time, the local memory 41 and the local memory 4
The address supplied to (2) is the next address. The address excluding the LSB of the local memory address (hereinafter referred to as the upper address bit) is the LSB of the local memory address = 1, that is, a = 11 1 1
As in case 1, the upper address bit +1 is supplied directly to the address input of local memory 4■, whereas the upper address bit +1 is supplied from the +1 addition circuit 42 via the multiplexer 44 to the address input of local memory 4I. . Therefore, as described above, the lower 16 bits input to the write data input of the local memory 4i are written to the data write position specified by the entry address supplied to the address input of the local memory 4i. , and the upper 16 bits input to the write data input of the local memory 42 are the address of the local memory 4? The data is written to the write location specified by the entry address supplied to the input.

As described above, the data written to the local memory 41 and local memory 4 is transferred to the external data bus 20.
Although the readout circuit system that reads data to an external memory (not shown) through the above is not shown in FIG. 2 because it is a technical matter that is not directly related to the gist of the present invention, the configuration of this readout circuit system is as follows. Various circuit configurations are possible. For example, ALU
After each of the 36 two output data is once written into two buffer registers (not shown), the data in both buffer registers is read out to the external memory via hardware processing to be transferred to the external data bus 20. I can do it.

In the above embodiment, an example in which two local memories are used has been described, but regardless of whether or not the data width of the external data bus 20 and/or the access unit to the local memory is changed, the number of local memories and The extensibility of the present invention to the case of a system configuration in which the relationship between the local memory address and the number of lower bits used for the number is a predetermined numerical relationship is not lost in the slightest. Specifically, as described above, the numerical relationship is 12ogzn=N. In that case, the shifter 22, +1 addition circuit 42,
It goes without saying that the circuit configurations of the multiplexers 44, 30, 32, and 46 must be changed so that their operations can be expanded to correspond to the expansion described above. The relationship between each memory and its entry address in this case is as shown in the following table.

Furthermore, the relationship between the division of data input via the external data bus 20 into write data units as described above and the write address of each divided write data unit determines the relationship between writing and reading of the data. The relationship does not have to be as described above as long as it is constant between the two.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
Since the division of data from the data bus into each local memory and the generation of a write address to the corresponding local memory for these data are performed within one cycle, writing of the data to the local memory is performed in one cycle. It can be achieved with. C required for this writing
The burden on PU can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. 1 and 2, 2 is a data bus (external data bus 20), 4i is a local memory, 6 is a data division circuit (shifter 22), and 8 is a write data unit input circuit (internal data bus 2).
4i26, multiplexers 30, 32), 10 is a write address generation circuit (control unit 34, local memory address set area 40, LSB set area 52, +1 addition circuit 42, multiplexer 44). 12 is a write input control circuit (LSB set area 52, inverter 52, data set instruction signal set area 48). 49 posts ≦ θ month ri 14 women's village pu'ov 7 figure 1

Claims (1)

[Claims] (1) The data bus (2) is sent to a plurality of local memories (4_i) (i=1, 2, . . . , n) in which the same write data unit is smaller by a predetermined value than the data width of the data bus (2). 2), the digital data processing system writes data from the data bus (2) to each of the data write inputs of the plurality of local memories (4_i) in response to a division control signal by one unit of access time. a write data unit input circuit (8_i) that connects the output of the data division circuit (6) to the data write input of the corresponding memory in response to an input control signal; is connected to the address input of each of the local memories (4_i), and the write address of each local memory determined according to the division in write access is connected to the corresponding address input of the 1
a write address generation circuit (10) that outputs within a unit access time; and a write input control circuit (12) that outputs the division control signal and input control signal in response to the write access.
A data writing control method from a data bus, characterized in that it is provided with: