JPH03217985A - Data processor and image diagnostic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device and an image diagnostic device including the same, and particularly relates to a data processing device and an image diagnostic device including the same, and particularly to data processing devices that handle a large amount of data such as image processing, etc., and data that is distributed and stored in memory. The present invention relates to a data processing device that improves data access in processing and calculations, efficiently uses low-speed memory, and increases data processing speed, and an image diagnostic device that effectively utilizes this data processing device.

[Conventional technology]

A standard memory access method in a conventional data processing device will be explained. As shown in FIG.
When reading data from 2, the processor 101:
- When giving a memory address to the memory device 102 via the address bus 103, reading data via the data bus 104 from a location specified by the address information in the memory, or writing data, the respective buses 10
3, 104 to output the memory address and write data to the memory device 102, and write the data to the specified location in the memory. This access method causes almost no problems when the calculation speed of the processor 101 used in the data processing device is equal to or lower than the access speed of the memory device 102. However, in recent years, as the calculation speed of processors has improved dramatically, the access time of memory devices and the data transmission time of peripheral interface devices have become bottlenecks in speeding up data processing. For example, as shown in FIG. 11, the program execution 101a of the processor is temporarily put into a waiting state due to the access operation 102a of the low-speed memory device 102, so that even though a processor capable of high-speed processing is used, However, high-speed data processing cannot be performed. In addition, especially when handling two-dimensional or three-dimensional image data, a large-capacity dynamic memory is often used as the memory, but dynamic memory cannot significantly improve access time due to its structure.

Therefore, the following two configurations have been proposed for conventional devices to further address this problem. One configuration, as shown in FIG. 9, includes a separate cache memory 105 that operates at high speed, especially as found in general processors, and the other configuration is shown in FIG. 10. Like, Digital Signal Processor (DSP)
As seen in the configuration above, the processor is equipped with a local memory 106 built into the processor. In all of these conventional device configurations, in addition to the low-speed memory device 102, small-capacity high-speed memories (105, 106) temporarily used for calculations are arranged near the processor 101, and frequently used data is is constantly stored in this high-speed memory, and data is exchanged between the high-speed memory and the low-speed memory device 102 as necessary, thereby increasing overall access time.

[Problem to be solved by the invention]

The conventional device configuration described above, which is equipped with a separate high-speed memory, is extremely efficient when performing data processing that involves repeating a large number of local operations because there is less need to exchange data between the high-speed memory and the low-speed memory. access time can be improved. However, in the case of data processing that handles 2D and 3D images, a large amount of data used for calculations is distributed and stored over a wide range of memory, so the probability that data scheduled for use exists in high-speed memory is high. As a result, even if high-speed memory is provided, data access time becomes long and efficiency deteriorates. Next, an example of such data processing will be specifically described.

FIG. 12 shows an example in which image rotation conversion processing is performed on image data of a two-dimensional image using a cubic interpolation method. 1st
In Figure 2, (A) is the image plane 107 (2) of the display.
dimension. 1024×1024 dots), and A, B, C, D, . . . represent pixel data corresponding to each image plane position, respectively. On the other hand, FIG. 12(B) shows the addresses in the memory where each of the above-mentioned pixel data is stored, and as is clear from this table, the address of each pixel data depends on the arrangement position of the image data on the two-dimensional image plane 107. Due to restrictions, addresses in memory are distributed. In image rotation conversion, when calculating the data of one point after conversion, the calculation is first performed using 4x4 data A, B, ..., 0, P, but these data are shown in Figure 12 ( As shown in B), addresses are stored in the memory in a distributed state. Furthermore, the following 1
When calculating points, calculations are performed using, for example, 4×4 pieces of data surrounded by a square formed by data F, Q, T, and W, depending on the rotation angle. If such rotation conversion processing is performed one point at a time, a miss will occur in the cache memory each time, and the data must be replaced. A problem arises in that even if memory is used, it is of little use. Even with a configuration that includes high-speed memory such as a cache memory, data addresses are dispersed in data processing of 2D and 3D images, resulting in frequent data replacement, resulting in a decrease in efficiency. This problem occurs.

An object of the present invention is to be able to maintain high processing speed even in a data processing device consisting of a combination of a high-speed processor and a low-speed memory without being affected by the access speed of the low-speed memory. It is an object of the present invention to provide a data processing device suitable for processing image data, etc., which requires processing and has a characteristic that addresses of data to be processed are distributed in memory.

Another object of the present invention is to provide an image diagnostic apparatus in which the data processing apparatus capable of high-speed data processing is applied to image processing.

[Means to solve the problem]

A data processing device according to the present invention is a data processing device that processes a large amount of data, and calculates an address in a memory of data used for calculation, and reads out corresponding data from the memory based on the calculated address. In a data processing device that performs arithmetic operations on data, calculates an address, specifies this address, and stores the result of this operation in memory, there is an address arithmetic device that performs the address arithmetic operation, and an output from this address arithmetic device. An address first-in, first-out memory that temporarily stores addresses in the order in which they occur; a memory device that sequentially reads addresses from this address first-in, first-out memory and outputs data corresponding to each address; and a data first-in, first-out memory that temporarily stores data in the order in which it is output. and a data calculation device that sequentially reads data from this data first-in first-out memory and performs calculations.

In the above configuration, the data processing device according to the present invention has the following features:
The address arithmetic device and the data arithmetic device can be implemented as functional elements in one processor, or each of the address arithmetic device and the data arithmetic device can be implemented as a single processor.
It can also be implemented with one processor.

In the above configuration, the data processing device according to the present invention has the following features:
The address arithmetic device, the memory device, and the data arithmetic device are configured to have an asynchronous operational relationship and perform pipeline processing.

The image diagnostic apparatus according to the present invention is configured to perform image processing by cubic interpolation using the data processing apparatuses having the respective configurations described above.

[Effect]

In the data processing device according to the present invention, the address arithmetic device, the memory device, and the data arithmetic device are arranged in a first-in, first-out memory (first-in, first-out memory).
(hereinafter referred to as FIFO), and therefore each can operate independently in terms of time via the FIFO.

That is, the address arithmetic unit 5I (processor) calculates the address of data and stores the address in the address FIFO.
write to.

The address calculation device performs other processing, for example, address calculation for data (processing that makes the data accessed to the memory unnecessary) without waiting for a response from the memory device. On the other hand, if an address exists in the address FIFO, the memory device side reads the address and reads data corresponding to the address. The read data is data FIF
Stored in O. Further, the data calculation device (processor) reads data from the data FIFO after a sufficient time compared to the memory access time, and performs calculations on the data. In this way, the high speed processor prevents time loss due to slow memory access times and maintains high speed processing overall.

If the address arithmetic device and the data arithmetic device are separated and configured so that their processing is performed asynchronously using separate processors, for example, parallel processing can further increase the speed.

Further, in the image diagnostic apparatus according to the present invention, by using the data processing apparatus according to the present invention, when applying cubic interpolation to image processing such as image rotation conversion processing, it is possible to perform this at high speed.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block configuration diagram showing a first embodiment, which is the basic configuration of the present invention. In FIG. 1, 1 is a processor having calculation and signal processing functions, and 2 is a memory. The processor 1 has the function of processing data at high speed, and in this embodiment has at least the function of an address calculation device and the function of a data calculation device. The memory 2 includes a conventionally known address buffer 3 and data buffer 4, and each operation of the memory 2, address buffer 3, and data buffer 4 is controlled by a memory control circuit 5. A memory system consisting of a memory 2 and the like and the processor 1 are connected via an address bus 6 and a data bus 7, and for conventional memory access, an address is input to the memory 2 via the address bus 6 and address buffer 3. At the same time, data corresponding to the address is read out via the data buffer 4 and the data bus 7 in the same bus cycle. The route of such memory access is the same as the route in the conventional device configuration.

In addition to the above-mentioned memory access routes, other memory access routes are provided which are also a feature of the present invention. That is, there is an address FIF between the memory 2 and the data bus 7.
O (first-in first-out memory or first-in first-out memory, the same applies hereinafter) 8 and data F I FO
9 is connected to form another memory access route. The processor 1 can access the above-mentioned PIFOs 8 and 9 in the same manner as when accessing data. The output line of the address PIFO8 is connected to the address line of the memory 2, and the input line of the data FIFO9 is connected to the data output line of the memory 2. Further, each operation of the address FIFO8 and data FIFO9 is controlled by the memory control circuit 5 described above.

In the configuration shown in FIG. 1, when performing data processing using a large amount of data such as image processing, the processor 1 calculates the address of the data to be used using the address calculation unit function, and calculates the address of the data to be used. The address is sent as data to the address PI FO8 via the data bus 7, and is temporarily stored there. In address calculation, multiple addresses are calculated at once, and address P
Stored in IFO8. With the address P I FO8 full, the memory control device 5 next
The stored addresses are sequentially read out while checking the state of the IFO 8, and data corresponding to each address is read out from the memory 2 and sequentially stored in the data FIFO 9. When the data F I FO 9 becomes full, the processor 1 sequentially reads out the data stored in the data F I FO 9 via the data bus 7 using its data arithmetic unit function, and then performs the necessary calculations to execute data processing. do.

The data obtained by the calculation is stored in the memory 2 according to a predetermined procedure as necessary. The conventional address buffer 3 and data buffer 4 can be used as a means for writing data obtained by calculation into the memory 2, or the data can be written using an address PIF08, etc. You can also do that. Further, as described above, the address buffer 3 and the data buffer 4 are used for conventionally well-known data processing other than those for ordinary large amounts of data.

In addition, address FIFO8 and data FIFO9
The details of the control will be described later.

As mentioned above, the processor 1 has the functions of an address arithmetic device and a data arithmetic device, and has high-speed arithmetic and signal processing capabilities that allow one processor to perform two device functions. It is configured as having. On the other hand, if the processing capacity of the processor is relatively slow, for example, it may be better to configure the address calculation device and the data calculation device as separate processors. A configuration in which the address arithmetic device and the data arithmetic device are fabricated using separate processors is a second embodiment shown in FIG. 2.

In FIG. 2, IA is an address arithmetic unit, and IB is a data arithmetic unit, each of which is realized by one processor, and has an independent address bus and data path set (6A, 7A) for the memory device. and (6B, 7B
). Then, the input line of the address P I FO8 is connected to the data path 7A of the address arithmetic unit IA.
The two input lines of the address buffer 3 are connected to the address bus 6A of the address calculation device IA and the address bus 6B of the data calculation device IB, respectively, and the two bus-side lines of the data buffer 4 are connected to the data bus 7A of the address calculation device 1A, respectively. and the data path 7B of the data processing unit IB, and the output line of the data F I FO9 is connected to the data processing unit IB.
are respectively connected to the data path 7B. The rest of the structure is the same as that shown in FIG.

According to the configuration shown in FIG. 1, one processor performs address calculation and data calculation, and as shown in FIG.
The operation of reading from O9 is normally performed synchronously. However, even with the configuration shown in FIG. 1, it is also possible to configure it so that it is executed in an asynchronous state. On the other hand, in the configuration shown in FIG. 2, the address calculation device IA and the data calculation device IB are configured to operate independently as shown in FIG. Operation of writing to FO8 and data calculation unit I
The operation of B reading data from the data FIFO 9 can be operated independently and asynchronously. Therefore, in the data processing device according to the present invention having the configuration shown in FIG. 2 (or FIG. 1),
In the case of the embodiment, the address arithmetic unit function of processor 1)
A process in which the address is calculated and written to the address P I FO8; ■ A process in which the address is read from the address P I FO8, accessed to the memory 2, and data is stored in the data FIFO9; In the case of the example, the process in which the data calculation device of the processor 1 reads data from the data F I FO 9 and performs data calculation can be performed in a pipelined manner as independent processes, and therefore the processing in the data processing device The speed is determined depending only on the process that takes the most time among the processes (1), (2), and (2), and the other processes can be almost ignored, thereby making it possible to significantly improve the processing speed.

Next, an example of FIFO control of the data processing apparatus having the above configuration will be described in detail. FIG. 3 is a configuration diagram shown to explain the operation of the FIFO of the data processing device having the configuration shown in FIG. 2.

Note that the data processing device shown in FIG. 1 can be considered in the same way if the address calculation device and the data calculation device are replaced with one processor, and the data paths 7A and 7B are combined into one data bus 7. can.

The address arithmetic unit IA receives a signal 11 related to its internal state from the address PIFO8, and this signal 11 indicates that the address PIFO8 is not full (NOT FULL).
．． ...represented by the symbol NF in the figure),
Write the calculated address to address FIF08. When the signal 11 indicates that the address P I FO 8 is full, the address calculation device IA enters a waiting state and performs data processing other than address calculation as necessary.

The memory control circuit 5 receives signals 12 .
13, the signal 12 indicates that the address P I FO8 is in a non-empty state (NOT EMPTY, ...represented by the symbol NE in the figure), and the signal 13 indicates that the data FI
When the FO 9 indicates that it is not full, the address information stored from the address PI FO 8 is read out, the memory 2 is operated, and the data output from the memory 2 is controlled to be written into the data FIFO 9.

Further, the data calculation device IB receives a signal 14 related to the internal state from the data F I FO9, and the signal 14
When I FO 9 indicates a non-empty state, data is read from data FI FO 9 and a data operation is performed on the data.

As mentioned above, address FI FO8 and data FI
Because pipelines are executed via FO9, there may be some temporal fluctuations in each of ■Address operation, ■Memory access, and ■Data operation (for example, execution of memory refresh during memory access, address calculation) Calculating the address of the first data during conversion takes time, but
Even if the address calculation for other data takes only a short time, etc.), other processing is not made to wait, and extremely efficient pipeline processing becomes possible.

In the configuration of the embodiment based on FIG. 3, while the signal 11 is NF, the address calculation device IA performs address calculation unless other signal processing is performed, and the address P I
Continue writing the address to FO8. Furthermore, even if an NF state occurs in signal 11, when the address calculation device IA is performing other processing, the other processing is given priority, and after the completion of that processing, address calculation and address writing operations are started. controlled to do so. Furthermore, the control method can be configured such that the address calculation and address write operations of the address calculation device IA for the address PIFO 8 are periodically performed together under predetermined conditions. The above control method is based on the relationship between the memory control circuit 5 and the signals 12 and 13, and the relationship between the data processing device IB and the signal 14.
It can be similarly applied in relation to.

Next, the data processing device according to the present invention explained above is MR.
An example of application to an image processing apparatus of I (magnetic resonance imaging apparatus) will be explained based on FIGS. 6 and 7.

MRI can be broadly divided into image reconstruction processing, which performs processing such as Fourier transform on measured data to create tomographic image data, and image processing, which processes and displays the reconstructed data in a form that is easy for humans to see. There are two types of data processing: Here, the display of arbitrary cross-section cutting (oblique slice), which requires a particularly large amount of data processing, will be explained.

Oblique slices cut out and display arbitrary two-dimensional sections from three-dimensional image data.

In Fig. 6, 21 is a space where three-dimensional data exists, 22 is the shape of a human head, 23 is an oblique slice plane set at an appropriate inclination angle, and the shaded part 23a is the head on the oblique slice plane. 22 is shown in cross section. In this process, first, to which position of the data grid point coordinate system of the original three-dimensional data space 21 corresponds a grid point on the oblique slice plane 23 as shown in FIG. 7, that is, a pixel position on the display. Coordinate transformation is performed to determine whether the object exists. Generally, these corresponding points are located away from the grid points of the three-dimensional data. Therefore, the data value (density value) of each grid point on the oblique slice surface 23
. . . in the case of MRI, the value proportional to the hydrogen nucleus) must be obtained by interpolation from data at grid points around the data corresponding point in the original three-dimensional data space 21. As this interpolation method, a cubic interpolation method is usually adopted in order to perform coordinate transformation without deteriorating image quality.

In the cubic interpolation method described above, the following calculations are performed. If the coordinates of the corresponding points in the three-dimensional data space are (x, y, z), then use the values of the nearest 64 points (43 points...4 points per direction) to obtain the oblique slice surface. The concentration value f (ξ, η) of the upper grid point is C (il-x)・C (jm-y)・C (kn-z
) However, l (0 two Gauss symbols) Therefore, in order to obtain an oblique slice image, (1)
Calculate the necessary 64 addresses in the 3D data corresponding to one point of the oblique slice image (reading 2164 data (3)) Perform the above calculation using the 64 data points to calculate the address of one point of the oblique slice image. (1) to (1) to calculate the concentration value
In the process of 3), it becomes necessary to calculate the number of points required to create an oblique slice image, for example, 256×256=64K (points).

Furthermore, the address calculation in (1) can be obtained by the following equation when the slice plane is a plane.

x=aξ+bη+C y=dξ+θη+f z=gξ10hη+p i2=[x:l,L=[yL k2=[z]11”
12-1.13=t2+l,l4=f2+2L"
J2-1, Jq: J2 +1.
L = L+2k+ ”k2-1,ks・k2+
I, k4 =k2+2 However, in addition to the above calculation formula, boundary conditions must also be considered.

As described above, the calculation for obtaining an oblique slice image has the following characteristics: firstly, the address calculation is complicated, secondly, there are many data reads, and thirdly, the number of times of product-sum calculation of density values is large. However, for example, according to the configuration according to the present invention shown in FIG. 2, address calculation is performed by the address calculation device IA, data reading is performed by the memory control circuit 5, and concentration value calculation is performed by the data calculation device IB. , each can be assigned a responsibility, and the processing speed can be improved until any one of (1) to (3) becomes a bottleneck.

In addition, in address calculation, out of 64 data address calculations per point, it takes time to calculate the address for the first point, but the address calculation for the other 63 points can be calculated in a relatively short time. Because of this, addresses do not occur at equal intervals. However, by using FIFO, this effect does not appear after memory access. Therefore, the process (3) is not affected by the previous process and can read data at the required speed solely based on the process.

In addition, in the data processing device having the configuration according to the second embodiment, the performance of the address calculation device IA, the memory 2, and the data calculation device IB can be improved independently from each other, and the data processing device can be upgraded in stages. It becomes easy to aim for.

The data processing device according to the present invention can be used in image diagnostic devices such as MRI and X-ray CT as described above, or in general three-dimensional image processing devices.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a data processing device including a high-speed processor and a low-speed memory device, each operation of the processor and the memory device is loosely connected using a FIFO. Other processing can be performed during the waiting time during access, and the overall data processing speed can be improved. By separating the processor functions into address calculation and data calculation, or by implementing each as an address calculation device or a data calculation device with a single processor, each can be processed in parallel in a pipeline manner. Furthermore, data processing speed can be improved.

Furthermore, image diagnostic equipment that uses a data processing device capable of such high-speed processing operations uses a particularly large amount of data in image processing, and even though the addresses of that data are dispersed within the memory, the high-speed processing can perform data processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a data processing device according to the present invention, and FIG. 2 is a block diagram showing a second embodiment of the data processing device according to the present invention.
FIG. 3 is a block diagram for explaining the FIFO control in detail, FIG. 4 is a timing chart showing the operation in the case of a single processor, and FIG. 5 is a block diagram showing the operation in the case of two processors. A timing chart showing the operation, FIG. 6 is a diagram for explaining the creation of an oblique slice image in MRI, FIG. 7 is a diagram for explaining coordinate transformation, and FIGS.
FIG. 10 is a block diagram of a conventional data processing device, FIG. 11 is a timing chart of the conventional data processing device, and FIG. 12 is a diagram for explaining the state of data distribution in image processing. [Explanation of symbols] 1...φ...Processor IA...Address arithmetic unit 1B...Data arithmetic unit 2...●Memory 3 @●61″●Address buffer 4 @ 11 4 11 @ @ data buffer 5...
・・・・Memory control circuit 6.6A, 6B ・●●Address bus 7.7A, 7B ・・・Data path 8・●・・・Address FIFO 9・・・・・・Data FIFO 21...・Three-dimensional data space 23...Oblique slice plane b 9 Fig. 4 Fig. 5 Fig. Data calculation No. 6 Fig. 3-dimensional data grid points 8 Fig. 9 Fig.] O Fig. 11 Fig. (A) (B )

Claims (5)

[Claims] (1) A data processing device that processes a large amount of data, and calculates the address in memory of the data used for calculation,
A data processing device that reads corresponding data from the memory based on the calculated address, performs a calculation on the read data, and stores the result of the calculation in the memory by calculating an address and specifying this address. an address calculation device that performs the address calculation;
an address first-in, first-out memory that temporarily stores the addresses outputted from the address arithmetic device in the order in which they occur; a memory device that sequentially reads addresses from the address first-in, first-out memory and outputs data corresponding to each address; A data processing device comprising: a data first-in, first-out memory that temporarily stores data in the order of output; and a data calculation device that sequentially reads data from the data first-in, first-out memory and performs calculations. (2) The data processing device according to claim 1, wherein the address calculation device and the data calculation device are each made of one processor. (3) The data processing device according to claim 1, wherein the address calculation device and the data calculation device are manufactured by one processor. (4) The data processing device according to any one of claims 1 to 3, wherein the operational relationship between the address calculation device, the memory device, and the data calculation device is asynchronous,
A data processing device configured to perform pipeline processing. (5) An image diagnostic apparatus that performs image processing by cubic interpolation using the data processing apparatus according to any one of claims 1 to 4.