JPH03218010A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the correlation between a size managing pattern and gate electrode size, and realize accurate monitoring, by arranging dummy patterns in the vicinity of the size managing pattern, and making the environment of the size managing pattern approximate to that of the gate electrode. CONSTITUTION:Dummy patterns 11, 12 are arranged in the vicinity of a size managing pattern 3a. Owing to the dummy patterns 11, 12, the environment of the pattern 3a is approximated to that of a gate electrode 3, and the correlation between the pattern width L1 of the pattern 8a and the pattern width L2 of the electrode 3 is increased. Hence the size L2 of the gate electrode 3 inside a memory cell can be accurately monitored by measuring the size L1 of the pattern 3a.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides dimension control for controlling the dimensions of a pattern after pattern formation when performing etching in the gate manufacturing process of a memory cell using an etch nog gas containing carbon-based gas. The present invention also relates to a method of manufacturing a semiconductor device using an improved dimension management pattern aimed at improving the correlation between variations in dimensions of gate electrodes within a memory cell within a wafer surface.

[Conventional technology]

FIGS. 2(a) and 2(b) show an example of a conventional dimension management pattern of this type. FIGS. 2(a) and 2(b) are a plan view and a cross-sectional view showing the dimension management pattern and the inside of the memory cell during gate pattern formation. In these figures, 1 is the 81 substrate, 2 is the underlying oxide film, 3 is the gate electrode i of the memory transistor and selection transistor formed by etching the polysilicon film, and 3a is the dimension control board also formed by etching the polysilicon film. It's a pattern.

A and B indicate the dimension management pattern portion and the inside of the memory cell, respectively. The reason why the dimension control baton 3a is L-shaped is to check that the line convergence between the line in the X direction and the line in the y direction differs after exposure and development due to Ste-Soba aberration.

Next, FIG. 3(a) shows a method of forming a dimensional control pattern and its function in the conventional manufacturing of semiconductor devices.
This will be explained with reference to (b).

As shown in FIG. 3(a), a mask pattern 4 is formed using a resist or the like on the polygonal silicon film 3', and using this as a mask, a method such as plasma etching is applied to the mask pattern 4 as shown in FIG. As shown in FIG. 3(b), the gate film 3' is etched and processed.

The above-mentioned Figures 2(a) and (b) are similar to Figures 3(a) and (b).
) after removing the mask pattern 4. The correlation between the dimension L3 of the dimension management pattern 3a shown in FIG. Its function is to estimate the dimension L4 of the gates 1 to 3 inside the memory cell shown in FIG. 2(b) by measuring the dimension L3.

[Problem to be solved by the invention]

In the conventional dimension control pattern 3a, the dimension iL3 of the dimension control pattern 3a is determined by the etching characteristics during pattern formation.
There is a significant difference between the variation within the wafer plane and the variation within the wafer plane of the dimension L4 of any gate electrode 3 inside the memory cell, and a correlation between the two cannot be established. It was difficult to estimate L4.

When the cause of this was investigated, it was found that carbon contained in the gas,
This is believed to be because carbon generated by sputtering of the resist during etching is largely involved in the formation of the sidewall protective film of the pattern of the film to be etched. Therefore, in areas with dense patterns such as memory cell areas, the amount of carbon that contributes per unit area of the sidewalls of the pattern is smaller than in areas with special patterns, resulting in variations.

This invention was made to solve the above-mentioned problems, and qualitatively reduces the variation in the dimension of the dimension management pattern within nine wafer planes and the variation in the dimension of any gate electrode inside the memory cell. The object of the present invention is to obtain a method for manufacturing a semiconductor device that makes it possible to estimate the dimensions of an arbitrary gate electrode inside a memory cell (L) by measuring the dimensions of a dimension control butterfly.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, a dummy pattern is disposed near a dimension control pattern, and the dimension of a gate electrode of a semiconductor device is monitored by the dimension control pattern including the dummy pattern.

[Effect]

In this invention, since the dummy vacuum is disposed near the dimension control pattern, variations in the dimensions of the dimension control pattern within the wafer surface can be reduced to the wafer dimension of any gate electrode inside the memory cell. This is qualitatively similar to the in-plane variation, and it becomes possible to accurately monitor the dimensions of any gate electrode inside the memory cell after Pakushi formation.

〔Example〕

FIGS. 1(a) and 1(b) are a front view and a sectional view showing the structure of an embodiment of the present invention. In these figures, the same symbols as in Figures 2 and 3 indicate the same things. 11,12
is a dummy pattern disposed near the dimension management pattern 3a, L1 is the pattern width of the dimension management pattern 3a, and L2 is the pattern width of the gate pattern inside the memory cell.

Here, when the dimension management pattern 3a in which the dummy pattern 11 is arranged is used, the environment of the dimension management pattern 3a and the environment of the gate electrode are similar, and the dimension L2 of the gate electrode 3 inside the memory cell after pattern formation. Since the correlation with the variation within the wafer plane is significantly improved, by measuring the dimension L1 of this dimension management pattern 3a, it is possible to accurately monitor the dimension L2 of the gate electrode 3 inside the memory cell. Become.

In the above embodiment, two dummy patterns 11 and 12 are provided on each side of the dimension control bag 3a, but the shapes and sizes of the dummy patterns 11 and 12 may be arbitrary. However, there is an optimum value for the smooth width LS between the dummy batten 11.12 and the dimension control butter 3a,
When arranging the dummy patterns 11 and 12, it is desirable to have a rough idea of the values and find their optimum values through experiments.

For example, when the gas ratio of SF6F113 is 1:13, there is no significant difference in variation if the space width is up to 1.5 μm, but if it is 20 μm, a significant difference occurs in terms of threshold value.

Further, in the above embodiment, the material of the gate I-electrode 3 and the dimension management pattern 3a is polysilicon, but any other material may be used.

Furthermore, the dimension management pattern 3a in which the dummy patterns 11 and 12 are arranged may be placed anywhere within the chip, including the die ring line.

Further, the present invention can be applied not only to memory cells but also to peripheral circuits.

〔Effect of the invention〕

As explained above, this invention places an appropriate distance in advance near the dimension management pattern on the L tickle,
By arranging a dummy pattern, the dimensions of this dimension control pattern can be measured after each manufacturing process of the semiconductor device, and the dimensions of the wafer with the dimensions of any one of the electrodes inside the memory cell can be measured. It is possible to qualitatively and accurately monitor in-plane variations, which has the effect of providing a method for manufacturing semiconductor devices with high yield.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a plan view and a sectional view showing an embodiment of the present invention, FIGS. 2(a) and (b) are views similar to FIG. 1 showing a conventional example, and FIG. Figure (.) (b) is a cross-sectional view for explaining a conventional method of forming a dimension management pattern and a pattern inside a memory cell. In the figure, 1 is a 31 substrate, 2 is an underlying oxide film, 3 is a gate electrode, 3a is a dimension control pattern, and 11 and 12 are dummy patterns. Note that the same reference numerals in each figure represent the same or equivalent parts. 1st Figures 11, 12 2nd Figure 1. Intention to amend cityization (voluntary initiative) February 21, 1991 3. Relationship with the case of the person making the amendment Patent applicant Address 2-2-3 Marunouchi, Chiyotsu-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4. Proxy address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (contact number: 03 (3213) 3421 Patent Department) 5. Detailed description of the invention in the specification subject to amendment 6. The correction is made as "20μ1" μm on page 7, line 9 of the detailed description of the amendment. , [2.0 and above]

Claims (1)

[Claims] When performing etching in the gate manufacturing process of a memory cell using an etching gas containing a carbon-based gas, a dimension control pattern is provided at required locations within the chip in order to control the dimensions of the gate electrode in the memory cell, In the method of monitoring the dimensions of the gate electrode of the memory cell by taking a correlation between the dimensions of the dimension management pattern and the dimensions of the gate electrode of the memory cell in advance and measuring the dimensions of the dimension management pattern. , a dummy pattern is arranged near the dimension management pattern,
A method for manufacturing a semiconductor device, characterized in that a dimension of a gate electrode in the memory cell is monitored based on a dimension of a dimension management pattern including the dummy pattern.