JPH03218041A - Mounting method of semiconductor element - Google Patents

Mounting method of semiconductor element

Info

Publication number
JPH03218041A
JPH03218041A JP2013419A JP1341990A JPH03218041A JP H03218041 A JPH03218041 A JP H03218041A JP 2013419 A JP2013419 A JP 2013419A JP 1341990 A JP1341990 A JP 1341990A JP H03218041 A JPH03218041 A JP H03218041A
Authority
JP
Japan
Prior art keywords
semiconductor element
bump electrodes
electrode terminals
mounting
mounting board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013419A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Atsushi Miki
淳 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2013419A priority Critical patent/JPH03218041A/en
Priority to AU69824/91A priority patent/AU634334B2/en
Priority to CA002034702A priority patent/CA2034702A1/en
Priority to EP91100820A priority patent/EP0439136A2/en
Priority to KR1019910001106A priority patent/KR950002744B1/en
Priority to US07/644,566 priority patent/US5092033A/en
Publication of JPH03218041A publication Critical patent/JPH03218041A/en
Priority to US07/779,280 priority patent/US5302854A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303Assembling printed circuits with electric components, e.g. with resistors with surface mounted components

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize precise alignment and mounting by electrically connecting bump electrodes, and relatively moving a semiconductor element and a board while monitoring electric continuity between corresponding electrode terminals on the mounting board surface. CONSTITUTION:At least a pair of bump electrodes 2 of a semiconductor element 1 is electrically connected by using a metal wire 3. It is monitor with an ammeter 7 checking whether electric continuity between at least a pair of electrode terminals 5 on a mounting board 4 is obtained. The element 1 and the board 4 are relatively moved while the monitoring is continued. Even if deformation like cutout exists, the bump electrodes of the semiconductor element are precisely aligned for the electrode terminals of the mounting board and mounting is enabled by the electric continuity detection based on the above monitoring.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICチップ等の半導体素子の表面から突出し
たバンプ電極を実装基板上の電極端子に直接接続(フェ
ースダウンボンディング)して半導体素子を実装基板上
に実装する方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device in which bump electrodes protruding from the surface of a semiconductor device such as an IC chip are directly connected to electrode terminals on a mounting board (face-down bonding). The present invention relates to a method for mounting a product on a mounting board.

〔従来の技術〕[Conventional technology]

半導体素子上に形成されているバンプ電極を実装基板上
の電極端子に直接接続して、半導体素子を実装基板上に
実装する場合、従来は、テレビカメラや画像処理装置に
より実装基板上の電極端子の位置を確認し、この位置に
半導体素子上のバンプ電極を位置合せして実装していた
When mounting a semiconductor element on a mounting board by directly connecting bump electrodes formed on the semiconductor element to electrode terminals on the mounting board, conventionally, the electrode terminals on the mounting board were connected using a TV camera or an image processing device. The bump electrodes on the semiconductor element were aligned and mounted at this position.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、バンプ電極と電極端子は向かい合った状態で位
置合せされるので、その位置合せの状態を実際に観察す
ることはできず、半導体素子の裏側からその外形を観察
し、この外形からバンプ電極の位置を推測するなどして
いた。このため、半導体素子の外形に欠け等の変形があ
ると、正確な位置合せか困難であった。
However, since the bump electrodes and electrode terminals are aligned while facing each other, it is not possible to actually observe the alignment. Instead, the outer shape of the semiconductor element is observed from the back side of the semiconductor element, and from this outer shape the bump electrodes are aligned. They were trying to guess the location. For this reason, if there is a deformation such as a chip in the outer shape of the semiconductor element, accurate alignment is difficult.

そこで、上述の事情に鑑み、本発明は半導体素子に欠け
等の変形があっても、半導体素子上のバンプ電極を実装
基板上の電極端子に対して高精度に位置合せして実装す
ることが可能な半導体素子の実装方法を提倶することを
日的としている。
Therefore, in view of the above-mentioned circumstances, the present invention makes it possible to precisely align the bump electrodes on the semiconductor element with the electrode terminals on the mounting board and mount it even if the semiconductor element is deformed such as chipping. Our mission is to propose possible mounting methods for semiconductor devices.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的を達成するため、本発明による半導体素子の
実装方法においては、半導体素子上の少なくとも一対の
バンプ電極を互いに電気的に接続しておき、これらのバ
ンプ電極に対応して実装基板表面に形成された少なくと
も1対の電極端子が相互に導通されるか否かを監視しつ
つ、バンプ電極を実装基板表面に当接させて半導体素子
を実装基板に対して相対的に移動させ、導通が監視され
ている電極端子が相互に導通された位置にて半導体素子
を実装基板に対して位置決めし、半導体素子を実装基板
に対して実装することとしている。
In order to achieve the above object, in the semiconductor device mounting method according to the present invention, at least one pair of bump electrodes on the semiconductor device are electrically connected to each other, and corresponding bump electrodes are formed on the surface of the mounting substrate. While monitoring whether or not the formed at least one pair of electrode terminals are electrically connected to each other, the bump electrodes are brought into contact with the surface of the mounting board and the semiconductor element is moved relative to the mounting board to ensure electrical continuity. The semiconductor element is positioned on the mounting board at a position where the electrode terminals being monitored are electrically connected to each other, and the semiconductor element is mounted on the mounting board.

〔作用〕[Effect]

このようにすることにより、半導体素子が実装基板に対
して位置合せされ、半導体素子上のバンプ電極がこれに
対応して形成された電極端子に接触すると、この接触が
電極端子相互間の電気的導通として検出される。
By doing this, when the semiconductor element is aligned with the mounting board and the bump electrodes on the semiconductor element come into contact with the correspondingly formed electrode terminals, this contact causes an electrical connection between the electrode terminals. Detected as continuity.

〔実施例〕〔Example〕

以下、本発明の実施例について第1図及び第2図を参照
しつつ、説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.

第1図は本発明により半導体素子上のバンプ電極が実装
基板上の電極端子に対して相対的に位置合わせされる状
態を概略的に示している。図示したように、半導体素子
1の表面には突出したバンプ電極2が複数形成されてい
る。そして、少なくとも一対のバンプ電極2が半導体素
子1の表面に形成された金属配線3により相互に電気的
に接続されている。他方、この半導体素子1が実装され
る実装基板4の表面には、半導体素子1上のバンプ電極
2に対応して電極端子5が形成されている。
FIG. 1 schematically shows how bump electrodes on a semiconductor element are aligned relative to electrode terminals on a mounting board according to the present invention. As shown in the figure, a plurality of protruding bump electrodes 2 are formed on the surface of the semiconductor element 1. At least one pair of bump electrodes 2 are electrically connected to each other by metal wiring 3 formed on the surface of semiconductor element 1. On the other hand, electrode terminals 5 are formed on the surface of the mounting substrate 4 on which the semiconductor element 1 is mounted, corresponding to the bump electrodes 2 on the semiconductor element 1.

そして、上述したように、相互に電気的に接続されたバ
ンプ電極2に対応して形成された一対の電極端子5には
、これら電極端子5とバンプ電極2が接触することによ
り、電極端子5の相互間が電気的に導通しているか否か
を検出する検出手段が接続されている。この検出手段と
して、図示した実施例では、直流電源6と電流計7とが
電極端子5の相互間に直列に接続されている。
As described above, the pair of electrode terminals 5 formed corresponding to the bump electrodes 2 that are electrically connected to each other are brought into contact with each other by contacting the electrode terminals 5 and the bump electrodes 2. Detecting means for detecting whether or not there is electrical continuity between the two is connected. As this detection means, in the illustrated embodiment, a DC power source 6 and an ammeter 7 are connected in series between the electrode terminals 5.

次に、バンプ電極2を電極端子5に直接接続して半導体
素子1を実装基板4上に実装する場合について説明する
。本発明による実装方法では、まず、半導体素子1のバ
ンプ電極2が実装基板4の電極端子5が形成されている
表面に当接させられる。そして、上述した検出手段によ
り電極端子5の相互間か導通されたか否かが監視されつ
つ、半導体素子1が実装基板4に対して相対的に摺動さ
せられる。相互に電気的に接続された一対のバンプ電極
2が検出手段の接続されている一対の電極端子5に接触
すると、電極端子5の相互間かバンプ電極2及び金属配
線3を介して導通される。これらバンプ電極2と電極端
子5とは互いに対応して形成されているので、電極端子
5の相互間が導通した場合には、半導体素子1上の全て
のバンプ電極2がこれらに対応して形成されている実装
基板4上の電極端子5に対して位置合せされていること
になる。したがって、第2図に示したように、半導体素
子1が実装基板4に対して位置合せされ、電極端子5相
互間の導通が検出手段により検出されたところで、半導
体素子1の実装基板4に対する摺動が停止され、その位
置にて半導体素子1が実装基板4に対して位置決めされ
る。この後、実装基板4が加熱され、その電極端子5上
に施された予備ハンダがリフローされて半導体素子1上
のバンプ電極2が実装基板4上の電極端子5に直接接続
され、半導体素子1が実装基板4に対して実装される。
Next, a case will be described in which the bump electrodes 2 are directly connected to the electrode terminals 5 and the semiconductor element 1 is mounted on the mounting board 4. In the mounting method according to the present invention, first, the bump electrodes 2 of the semiconductor element 1 are brought into contact with the surface of the mounting board 4 on which the electrode terminals 5 are formed. Then, the semiconductor element 1 is slid relative to the mounting board 4 while monitoring whether or not the electrode terminals 5 are electrically connected to each other by the above-mentioned detection means. When a pair of bump electrodes 2 electrically connected to each other come into contact with a pair of electrode terminals 5 to which a detection means is connected, conduction is established between the electrode terminals 5 or through the bump electrodes 2 and the metal wiring 3. . These bump electrodes 2 and electrode terminals 5 are formed in correspondence with each other, so when the electrode terminals 5 are electrically connected to each other, all the bump electrodes 2 on the semiconductor element 1 are formed in correspondence with each other. This means that the electrode terminals 5 on the mounting board 4 are aligned with each other. Therefore, as shown in FIG. 2, when the semiconductor element 1 is aligned with the mounting board 4 and the conduction between the electrode terminals 5 is detected by the detection means, the sliding of the semiconductor element 1 with respect to the mounting board 4 is detected. The movement is stopped, and the semiconductor element 1 is positioned with respect to the mounting board 4 at that position. Thereafter, the mounting board 4 is heated, and the preliminary solder applied on the electrode terminals 5 is reflowed, so that the bump electrodes 2 on the semiconductor element 1 are directly connected to the electrode terminals 5 on the mounting board 4, and the semiconductor element 1 is mounted on the mounting board 4.

なお、相互に接続されるバンプ電極2及びこれに対応し
て形成される電極端子5のサイズを小さくすればするほ
ど、位置合せ精度は向上する。また、相互に電気的に接
続されるバンプ電極2の対を複数対設けこれら対同士を
互いに離間させておけば、これらに対応して形成されて
いる電極端子5の相互間の導通を上述したようにして検
出することにより、さらに位置合せ精度が向上する。
Note that the smaller the sizes of the bump electrodes 2 and the electrode terminals 5 formed corresponding to the bump electrodes 2 that are connected to each other, the more the alignment accuracy improves. Furthermore, by providing a plurality of pairs of bump electrodes 2 that are electrically connected to each other and separating these pairs from each other, conduction between the electrode terminals 5 formed corresponding to these pairs can be established as described above. By detecting in this manner, alignment accuracy is further improved.

相互に接続されるバンプ電極2のサイズを直径10μm
、基板上に対応して形成される電極端子5の直径を10
μmとし、本発明を適用した場合の位置合せ精度と、従
来の位置合せ装置による位置合せ精度とを比較して下表
に示す。
The size of the bump electrodes 2 that are connected to each other is 10 μm in diameter.
, the diameter of the electrode terminal 5 correspondingly formed on the substrate is 10
μm, and the alignment accuracy when the present invention is applied is compared with the alignment accuracy using a conventional alignment device, as shown in the table below.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、実装基板上に形
成された電極端子相互間の導通を検出することにより、
半導体素子上のバンプ電極と実装基板上の電極端子との
位置合せの状態を確認することができ、半導体素子に欠
け等の変形があっても半導体素子上のバンプ電極を実装
基板上の電極端子に対して高精度に位置合せして実装す
ることかできる。
As explained above, according to the present invention, by detecting conduction between electrode terminals formed on a mounting board,
It is possible to check the alignment status between the bump electrodes on the semiconductor element and the electrode terminals on the mounting board, and even if the semiconductor element is deformed such as chipping, the bump electrodes on the semiconductor element can be aligned with the electrode terminals on the mounting board. It can be mounted with high precision alignment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明により相対的に位置合せされる半導体素
子と実装基板を示した図、第2図は位置合せ終了後の半
導体素子と実装基板を示した図である。 1・・・半導体素子、2・・・バンプ電極、3・・・金
属配線、4・・・実装基板、5・・・電極端子、6・・
・直流電源、7・・・電流計。
FIG. 1 is a diagram showing a semiconductor element and a mounting board that are relatively aligned according to the present invention, and FIG. 2 is a diagram showing the semiconductor element and a mounting board after the alignment is completed. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Bump electrode, 3... Metal wiring, 4... Mounting board, 5... Electrode terminal, 6...
・DC power supply, 7... ammeter.

Claims (1)

【特許請求の範囲】 半導体素子の表面から突出したバンプ電極を実装基板上
の電極端子に直接接続して前記半導体素子を前記実装基
板上に実装する方法であって、前記半導体素子上の少な
くとも一対のバンプ電極を互いに電気的に接続しておき
、 互いに電気的に接続されたバンプ電極に対応して前記実
装基板表面に形成された少なくとも1対の電極端子が相
互に導通されるか否かを監視しつつ、前記バンプ電極を
前記実装基板表面に当接させて前記半導体素子を前記実
装基板に対して相対的に移動させ、 導通が監視されている電極端子が相互に導通された位置
にて前記半導体素子を前記実装基板に対して位置決めし
、 前記半導体素子を前記実装基板に対して実装することを
特徴とする半導体素子の実装方法。
[Scope of Claims] A method for mounting the semiconductor element on the mounting substrate by directly connecting bump electrodes protruding from the surface of the semiconductor element to electrode terminals on the mounting substrate, the method comprising: at least one pair of bump electrodes on the semiconductor element; electrically connecting the bump electrodes to each other, and determining whether at least one pair of electrode terminals formed on the surface of the mounting board corresponding to the bump electrodes electrically connected to each other are electrically connected to each other. While monitoring, the semiconductor element is moved relative to the mounting board by bringing the bump electrode into contact with the surface of the mounting board, and at a position where the electrode terminals whose continuity is being monitored are mutually electrically connected. A method for mounting a semiconductor element, comprising: positioning the semiconductor element with respect to the mounting substrate; and mounting the semiconductor element on the mounting substrate.
JP2013419A 1990-01-23 1990-01-23 Mounting method of semiconductor element Pending JPH03218041A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2013419A JPH03218041A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element
AU69824/91A AU634334B2 (en) 1990-01-23 1991-01-22 Packaging structure and method for packaging a semiconductor device
CA002034702A CA2034702A1 (en) 1990-01-23 1991-01-22 Method for packaging semiconductor device
EP91100820A EP0439136A2 (en) 1990-01-23 1991-01-23 Method for electrically connecting and packaging a semiconductor device
KR1019910001106A KR950002744B1 (en) 1990-01-23 1991-01-23 Method of mounting semiconductor device
US07/644,566 US5092033A (en) 1990-01-23 1991-01-23 Method for packaging semiconductor device
US07/779,280 US5302854A (en) 1990-01-23 1991-10-18 Packaging structure of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013419A JPH03218041A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element

Publications (1)

Publication Number Publication Date
JPH03218041A true JPH03218041A (en) 1991-09-25

Family

ID=11832613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013419A Pending JPH03218041A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element

Country Status (1)

Country Link
JP (1) JPH03218041A (en)

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