JPH03218052A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device manufactured by a mask slicing method, and particularly to a technique effective when applied to the layout of power supply wiring.

[Conventional technology]

The mask slicing method is used to manufacture custom LSIs in a short lead time, and consists of regularly arranging a large number of basic cells on a semiconductor substrate and arranging them according to the user's wishes. By connecting the basic cells with signal wiring, an LSI having a desired logic circuit is formed.

In a semiconductor integrated circuit device having a multilayer wiring structure, such as the semiconductor integrated circuit device manufactured by the above mask slicing method, power supplied from the outside is sent inside the semiconductor integrated circuit device through a pair of power supply wirings. . Of the above pair of power supply wirings, one is connected to an external power supply terminal to which a high level voltage (hereinafter also simply referred to as the electric voltage VCC) is supplied, and the other is connected to a low level voltage (hereinafter simply referred to as the ground voltage VCC). 5 (also referred to as 5) is connected to an external power supply terminal supplied with the power.

On the outer periphery of the semiconductor integrated circuit device, T bonding pads for electrical connection with the outside, and T/○ cells, which are selectively used as output buffer circuits, output bath sofa circuits, and large buffer circuits, are continuously arranged. will be placed in Above I/
The above-mentioned I
A pair of power supply wirings for supplying power to the /O cell is formed.

The pair of power supply wirings are arranged on the outer periphery of the semiconductor integrated circuit device along the arrangement of the I/O cells. In the present application, the power supply wiring formed in the outer peripheral portion is also simply referred to as a power supply line hereinafter.

A plurality of basic cells are regularly formed in an internal region (cell region) surrounded by the above-mentioned I/O cells, and a first wiring layer above the above-mentioned basic cells has a plurality of basic cells. Power supply wiring for supplying power to each basic cell is formed along the arrangement. In the present application, the power supply wiring for supplying power to each of the basic cells is hereinafter also simply referred to as cell power supply wiring.

A power supply wiring for electrically connecting the cell power supply wiring and the power supply line is formed in the same wiring layer as the power supply wiring (power supply line) in the outer peripheral portion. In this application,
The power supply wiring that connects the cell power supply wiring and the power supply line is hereinafter also simply referred to as an auxiliary power main line. The auxiliary power main line is formed by arranging a pair of 74 source wirings in parallel on the same wiring layer, and is formed in a ladder shape or a lattice shape within the cell region.

An example of a document describing a mask slicing semiconductor integrated circuit device is Japanese Patent Laid-Open No. 61-2345.
JP-A No. 6-3-4-4-7-4-2, Japanese Patent Application No. 174796-1980, etc.

[Problem to be solved by the invention]

Aβ has been mainly used as a wiring material for integrated circuits formed on semiconductor substrates due to its low electrical resistance, good adhesion to silicon oxide films, and ease of processing. BACKGROUND ART As wiring becomes finer due to higher circuit densities, disconnection of aluminum wiring due to electromigration (EM) has become a serious problem. The above-mentioned electromigration shimin is a phenomenon in which the wiring material begins to move by exchanging momentum with carriers, and it becomes more pronounced as the current density in the wiring becomes higher. Therefore, improving the electromigration resistance of wiring in semiconductor integrated circuit devices is an important issue from the standpoint of improving reliability. In the present application, the disconnection due to electromigration is hereinafter also simply referred to as EMD.

In the semiconductor integrated circuit device using the mask slicing method, power supplied from the outside is supplied to the cell area through the power line formed on the outer periphery of the semiconductor substrate. Since the current density becomes particularly high, EMD countermeasures for the power supply line become an essential issue. A possible alternative method for improving the EMD resistance of the power supply line is to increase the width of the power supply line to reduce the current density. However, if the width of the power supply lines formed in parallel on the same wiring layer is increased, the area occupied by the power supply lines increases.

Therefore, from the viewpoint of improving the degree of integration of the semiconductor integrated circuit device, the width of the power supply line cannot be increased beyond a certain level, and there is a problem that it is difficult to improve the EMD resistance.

On the other hand, the I/O cells of the semiconductor integrated circuit device using the mask slicing method are, for example, complementary MI
Formed with SFET (CMOS) circuit, the above I/O
Power is supplied to the cell from the power supply line. By the way, the above I/O cell performs a switching operation, and the power supply voltage V is applied to the elements in the cell area. When trying to supply a high-level signal corresponding to C, the current that should drive the capacitive load formed in the elements and signal wiring is the power supply voltage V. . The power is supplied to the I/○ cells from the supply power line. When a large number of the above ■/○ cells perform the above switching operation at the same time, a very large current tries to flow through the above power supply line, but the potential of the above power supply line is unstable in relation to its current supply capacity. Desired temporary drop. Further, when the ■/○ cell performs a switching operation and supplies a low level signal corresponding to the ground voltage V 5 to the elements in the cell area, the charge accumulated in the capacitive load is transferred to the I Flows through the /○ cell to the power supply line for ground voltage VSS. When a large number of I/○ cells perform this current drawing operation at the same time, a large current tries to flow through the power supply line, but there is a limit to its current drawing ability. The potential of the power supply line increases temporarily and undesirably. Furthermore, during the switching operation, the n-channel MISFET and the p-channel MISFET constituting the complementary MISFET circuit
There is a moment when both are turned on at the same time. At this time, the power supply voltage is V. A through current flows from the power supply line to which 0 is supplied to the power supply line to which ground voltage VSS is supplied. When a large number of the above I/O cells perform switching operations simultaneously, a large through current flows instantaneously.
In this case as well, the power supply voltage is V. C or the ground voltage VSS change undesirably.

Such temporary potential changes in the power supply line, ie, power supply noise, may cause malfunctions in transistors forming the logic circuit. For example, if the potential of the power supply line to which the ground voltage V 5 5 is applied increases undesirably, the source potential of the n-channel MISFET increases, and as a result, the gap between the gate electrode and the source electrode of the n-channel MISFET increases. Because the potential difference between the n-channel MISFET and the N-channel MISFET is relatively reduced, the n-channel MISFET may temporarily turn off when it should be on, or its mutual conductance may become small. obtain.

Such malfunctions also occur when the power supply voltage V. This also occurs in a p-channel MISFET when 0 is applied.

Further, the auxiliary power supply main lines of semiconductor integrated circuit equipment using the above-mentioned mask slicing method are formed in parallel on the same wiring layer, but when the above-mentioned auxiliary power supply main lines are formed in a lattice shape, the intersections of the lattice In order to prevent short circuits, the auxiliary power main line must be formed three-dimensionally using two wiring layers. Similarly, the part connecting the power line formed on the outer periphery and the auxiliary power main line needs to be formed three-dimensionally to avoid short circuits, which poses the problem of complicating the design. was discovered by the present inventor.

An object of the present invention is to provide a semiconductor integrated circuit device having power supply wiring with improved EMD resistance.

Another object of the present invention is to provide a semiconductor integrated circuit device that is free from malfunction due to power supply noise and can be expected to operate stably.

Still another object of the present invention is to provide a semiconductor integrated circuit device whose auxiliary power main line is easy to design.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit device having a multilayer wiring structure, a first power supply wiring to which a first power supply voltage is supplied;
The second power supply wiring to which the second power supply voltage is supplied is arranged in a separate layer.

Further, the first power supply wiring and the second power supply wiring are arranged in parallel so as to overlap with each other in vertically adjacent different layers.

Furthermore, the first power supply wiring and the second power supply wiring are arranged in the same wiring layer as the first power supply wiring and the second power supply wiring, which are arranged in parallel so as to overlap with different layers adjacent to each other vertically. The third power supply wiring and the fourth power supply wiring are arranged parallel to each other, and the third power supply wiring and the fourth power supply wiring are also arranged in parallel so as to overlap vertically, and The same first power supply voltage is supplied to the power supply wiring and the fourth power supply wiring, and the same second power supply voltage is supplied to the second power supply wiring and the third power supply wiring.

[For production]

According to the above-mentioned means, by arranging the first power supply wiring and the second power supply wiring in different layers, part or all of the pair of power supply wirings are overlapped with each other with a predetermined insulation distance, and as a result, Since the width of each power supply wiring can be made wider than before, the current density in the power supply wiring is reduced and EMD resistance is improved. In addition, by arranging the first power supply wiring and the second power supply wiring in separate layers while maintaining a predetermined insulation distance vertically, the power supply wiring can be intersected three-dimensionally at the intersection of the power supply wiring as in the conventional method. Since this is no longer necessary, the design of the power supply wiring described above becomes easier.

In addition, by distributing the first power supply wiring and the second power supply wiring so that they overlap in vertically adjacent separate layers, a much larger coupling capacitance is formed between the pair of power supply wirings than in the past. be done. Since such a large coupling capacitance acts to alleviate and absorb fluctuations in the potential of the N source wiring due to power supply noise, malfunctions due to power supply noise are prevented.

Furthermore, according to the above-mentioned means, since the same power supply wiring layer includes mutually different power supply wirings to which the first voltage #i voltage and the second power supply voltage are individually supplied, the power supply wiring This makes it easier to supply power to elements formed directly below or above the power supply, and the power supply voltages of the power supply wiring located at the side ends of the power supply wiring layers stacked one above the other are also different from each other. Power can also be easily supplied to circuit elements formed on the sides of the wiring.

Hereinafter, the present invention will be explained in detail with reference to Examples. In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment 1] FIG. 1 shows a configuration diagram of a semiconductor integrated circuit device which is an embodiment of the present invention. Note that in this figure, the interlayer insulating film is omitted to simplify the explanation.

The semiconductor integrated circuit device shown in this figure has, for example, a three-layer wiring structure, and although it is not particularly limited, a p-channel type M
This is a CMOS gate array in which gates formed by complementary MISFETs (CMOS) each having two ISFETs and two n-channel MISFETs are regularly arranged. The gate is the basis of a logic circuit, and is also called a basic cell 11. The basic cells 11 are arranged in a column direction to form a cell column 12, and the cell column 12 is arranged in a row direction to form a cell area. 20 are configured.

The CMOS gate array of Example 1 has the cell area 2
This is a so-called "sea of gates" method in which the basic cells 11 are arranged without gaps within the cell rows, and unlike the so-called fixed channel method, there is no wiring channel region between cell rows. And the above basic cell 1
A desired logic circuit is formed by connecting the internal cells 1 and between the basic cells 1l with signal wiring (not shown). The signal wiring is formed of, for example, a first layer wiring made of an aluminum alloy. The line width of the above signal wiring is, for example, 2
It is about 4 μm. In addition, in the first wiring layer,
A pair of cell power supply lines 17 and 18 made of aluminum alloy for supplying power to the basic cells 11 are formed along each cell row 12.

The line width of the cell power supply wiring 17 and 18 is, for example, 6 to 10
It is about μm.

An input buffer is selectively provided around the cell area 20.
An I/O cell 13 serving as an output buffer or a human output buffer is continuously formed, and a substrate 10 outside the I/O cell 13 is formed continuously.
A bonding pad 14 for electrical connection with the outside is arranged on the outer periphery. The I/O cell 13 is composed of a complementary MISFET, and is configured as an input buffer, an output buffer, or a human output buffer by connecting it with, for example, the wiring of the first wiring layer. Also, the above I/O
The cells 13 constitute an electrostatic damage prevention circuit and a clamp circuit. Among the many bonding pads 14 mentioned above,
Some of them are external power supply terminals for receiving power supply from the outside, and the power supply voltage Vcc (for example, 5V) or the ground voltage V, (for example, OV) is supplied to the external power supply terminal.

In the upper layer of the I/O cell 13, for example, a second wiring layer, there is a power supply line 15 made of aluminum alloy for transmitting the power supplied to the external power supply terminal into the cell region 20. 16 are formed in parallel. One power supply line 15 is formed on the side facing the cell region 20, and is supplied with a ground voltage V 5 5 from the external power #i terminal. The other power supply line 16 is formed outside the power supply line 15 and receives the power supply voltage V from the external power supply terminal. . is supplied. Since the power supply lines 15 and 16 are formed in parallel on the same wiring layer, electrical connection with the ■/○ cells 13 can be easily made as in the conventional case.

In the upper layer of the power supply line 15.16, for example, the third wiring layer, the power supply line 5 made of aluminum alloy,
6 are formed in parallel. The width of the power supply line 5.6 is approximately the same as the width of the power supply line 15.16 in the lower layer.

One power supply line 5 is formed in parallel so as to overlap with the upper layer of the power supply line 16, and the other power supply line 6
are formed in parallel so as to overlap the upper layer of the power supply line 15. In addition, several parts of the power supply line 5 are formed so as to extend directly above the power supply line 15 formed diagonally below, and are connected to the lower layer through contact holes 47 opened directly below the above-mentioned extension of an insulating film (not shown). It is electrically connected to the power supply line 15 of. That is, the power supply line 5 is supplied with the ground voltage VSS. At the upper projecting portion, the adjacent power lines 6 are formed to be curved so as to avoid the projecting portion of the power line 5. In addition, several parts of the power line 16 are formed so as to extend directly below the power line 6 formed diagonally above, and are connected to the power line 6 in the upper layer through contact holes 48 opened in an insulating film (not shown). electrically connected. That is, the power supply line 6 is supplied with the power supply voltage VCC. Note that in this figure, one representative portion of each of the above-mentioned overhang portions is shown. Furthermore, the power supply lines 5.6 and 15.16 are formed continuously along the outer periphery of the substrate 10, but some of them have been removed to make it easier to understand how they are formed so as to overlap vertically. It is illustrated as follows. Furthermore, the above power lines 5, 6, 15.16
is formed by arranging a plurality of wirings each having a width of, for example, 45 μm in parallel in order to prevent the occurrence of package cracks during the sealing process.
It is expressed as the wiring of a book. The plurality of wires constituting the power supply line 15 are supplied with power from one I/O cell 13 to which the ground voltage VSS is supplied, and the power supply line 16
The plurality of wirings constituting the circuit are supplied with power from one I/O cell 13 to which the power supply voltage VCC is supplied.

In the upper layer of the cell region 20 surrounded by the power supply lines 5, 6, 15.16, the cell power supply wiring 17.
Auxiliary power main line 45.4 made of aluminum alloy for electrical connection between 18 and the above power line 15.16
6 is formed.

The auxiliary power main line 45 is formed in the same second wiring layer as the power line 15, and its end portion is integrally connected to the power line 15. That is, the auxiliary power main line 45 is supplied with the ground voltage VSS. The line width of the auxiliary power main line 45 is, for example, about 15 to 25 μm. The other auxiliary power main line 46 is formed in the same third wiring layer as the power line 6, and its end is integrally connected to the power line 6. That is, the auxiliary power main line 46 is supplied with the power supply voltage V. 0 is supplied. The line width of the auxiliary power main line 46 is, for example, about 30 to 50 μm. A plurality of the auxiliary power main lines 45 and 46 are formed in a grid pattern. Further, the auxiliary power main lines 45 and 46 are formed parallel to each other, but are not formed so as to overlap one above the other, but are formed at different levels at a predetermined interval.

FIG. 2 shows a more detailed arrangement of the auxiliary power mains 45, 46. The number of auxiliary power main lines 45 and 46 to be placed and the wiring size (line width, film thickness) are automatically set based on fixed pattern information incorporated in the base data of the automatic placement and wiring system, which will be detailed later. , the layout is common to all types of gate arrays. That is, the spacing M and the number of the auxiliary power main lines 45, 46 in the row direction, and the spacing N and the number of lines in the column direction are based on the number of basic cells 11, with the frequency and wiring size used as the main requirements. stipulated. FIG. 3 shows an example of the relationship between the frequency used and the number of basic cells. In this figure, the horizontal axis is the frequency used (M
HZ), and the vertical axis represents the number of basic cells 11 (the product of the number of basic cells 11 arranged in the row direction [m] and the number of basic cells 11 arranged in the column direction [n]). It shows. Each of the curves ASB and C in the figure indicates the total cross-sectional area [μm''] of the auxiliary power main line 45.46, which is the sum of the cross-sectional area of the auxiliary power main line 45 and the cross-sectional area of the auxiliary power main line 46. Curve A is, for example, when the total cross-sectional area of the auxiliary power supply main lines 45.46 is 22 to 23 μm'.Curve B is, for example, when the total cross-sectional area of the auxiliary power supply main lines 45.46 is 35 to 36 μm.
μm''.Curve C is, for example, the case of the auxiliary power main line 4
This is the case when the total cross-sectional area of 5.46 is 61 to 62 μm'.

As a result, the optimum current density for one basic cell 11 can be measured, so depending on the frequency used, the number of basic cells 11 and the auxiliary power supply required for this number of basic cells 11 can be determined from FIG. The total cross-sectional area of the main lines 45 and 46 can be calculated.

For example, the frequency used is 30M7, auxiliary power main line 45
．． When the total cross-sectional area of 46 cells is 22 to 23 μm'' (curve A), the number of basic cells 11 for optimum current density is approximately 1000. Since it is the product of the number of basic cells 11 arranged [m] and the number of basic cells 11 arranged in the column direction [n], for example, for every 10 basic cells 1l arranged in the row direction, One auxiliary power main line 45 and one auxiliary power main line 46 are prepared, and one auxiliary power main line 4 is provided for every 100 basic cells 11 arranged in the column direction.
All you need to do is prepare one each of 5.46. In this embodiment, for example, one auxiliary power main line 45,46 is prepared for each of about 10 to 20 basic cells 11 arranged in the row direction, and one auxiliary power supply main line 45,46 is prepared for each of about 10 to 20 basic cells 11 arranged in the column direction. One auxiliary power main line 45,46 is prepared for each cell 11.

As a result, the auxiliary power main lines 45, 46 extending in the row direction
The number of basic cells 11 arranged in the area partitioned by and the auxiliary power main lines 45 and 46 extending in the column direction is substantially the same as the number of basic cells 11 arranged in other partitioned areas. is equal to Further, the current density in each divided region is also substantially equal. Therefore, the auxiliary power main line 45.
Since the current density in each region divided by 46 is optimally set based on the number of basic cells 11, extreme concentration of current density does not occur no matter what logic circuit is created. Note that the usage rate of the basic cells 11 (the placement ratio of logic circuits) in the above partitioned area does not necessarily have to be 100%, and usually there is a tolerance of about 20%, so the average is about 80%. It is.

In this way, a plurality of auxiliary power main lines 45 extending in the column direction and arranged at substantially equal intervals M in the row direction are provided in the upper layer of the cell region 20 of the semiconductor integrated circuit device manufactured by the mask slicing method. .46 and a plurality of auxiliary power supply main lines 45.46 extending in the row direction and arranged at substantially equal intervals N in the column direction in a grid pattern, the auxiliary power supply main lines 45.46 are Since it is possible to equalize the current density in each region divided by Power main line 45
．． The area occupied by 46 can be reduced and the implementation rate of logic circuits can be improved.

As shown in FIG. 1, one of the pair of cell power supply lines 4117.18 (7) formed in the upper layer of the cell column 12 is connected to the basic cell 11 constituting the cell column 12. A pad electrode 42 formed on the p-channel MISFET in the second wiring layer and a contact hole 36 opened in an interlayer insulating film (not shown)
It is connected to the auxiliary power supply main line 46 via. The other cell power supply line 18 is formed on the n-channel MISFET in the basic cell 11, and is connected to the auxiliary power supply main line 45 through a contact hole 39 opened in an insulating film (not shown). Therefore, the power supply voltage V is applied to the power supply wiring 17. , and the ground voltage VSS is supplied to the power supply wiring 18, respectively. In this way, this example 1
The CMOS gate array supplies power to the cell area 20 from the power supply lines 5.6, 15.16 formed in the upper layer of the I/O cell 13, to the auxiliary power supply main lines 45, 46, and further through the cell power supply wiring 17.18. do.

The power lines 5, 6, 15, and 16 are formed thinner than conventional power lines formed in parallel on the same wiring layer, but their width is at least half the width of the conventional power lines. . Since the width of each of the power supply lines 5.6 and 15.16 is narrower than before, the area occupied by the power supply lines 5.6 and 15.16 is reduced compared to the conventional case.
The semiconductor integrated circuit device has an improved degree of integration compared to conventional semiconductor integrated circuit devices having the same chip size. In addition, the power lines 5 and 15 or 6 and 16 formed across two vertically adjacent layers are supplied with the same potential, and the width of each power line is at least half wider than the conventional power line. Therefore, the overall width of the power supply lines having the same potential is formed wider than in the past. As a result, in the semiconductor integrated circuit device of the first embodiment, the density of the current flowing through the power supply line is reduced compared to the conventional device, so that its EMD resistance is improved.

Furthermore, conventionally, coupling capacitance in power supply lines formed in parallel on the same wiring layer was formed only between the side surfaces of two power supply lines, but the coupling capacitance of the power supply line in this embodiment 1 is , power supply lines 5 and 6 and 15 and 16 formed in parallel on the same wiring layer, and power supply lines 5 and 16 and 6 and 15 formed between the side surfaces and overlapping vertically. It is also formed between surfaces. That is, the above power lines 5.6, 15.1
The coupling capacitance formed between the sides of the power lines 5, 6, 15, .
Since the coupling capacitance formed between the surfaces of the power supply lines 5.6 and 15.16 is added, the coupling capacitance formed in the power supply lines 5.6 and 15.16 becomes much larger than that in the conventional case.

By the way, when a plurality of I/O cells 13 connected to the power supply lines 5, 6, 15.16 perform switching operations at the same time, power supply noise is generated on the power supply lines 5, 6, 15.16. When the power supply noise occurs, the increased coupling capacitance acts to alleviate the noise. That is, when the power supply noise occurs, the potential of the power supply lines 5, 6, 15, 16 tends to rise or fall undesirably, but the ground voltage VSS of the power supply lines 5, 15 tends to rise undesirably. In this case, the excess charge is used to charge the large coupling capacitance, and if the power supply voltage VCC of the power supply lines 6 and 16 is about to drop undesirably, the large coupling capacitance is charged. The charge on the voltage compensates for that voltage drop. In this way, the power lines 5, 6, 15, 16
By alleviating undesirable changes in the potential of the semiconductor integrated circuit device of the first embodiment, the increased coupling capacitance alleviates and absorbs power supply noise, thereby preventing malfunctions of the transistors formed inside. Therefore, stable circuit operation is ensured. Further inside the above power line 6.15
are formed in separate upper and lower layers, and each has a power supply voltage V. c1
Alternatively, since the ground voltage V S 5 is supplied, the auxiliary power main line 46.
45 can be formed on the same wiring layer as the power supply lines 6 and 15, and as a result, there is no need for three-dimensional wiring to prevent short circuits at the connection between the two as in the past. .45 design becomes easy.

FIG. 4 shows a detailed diagram of the basic cell 11, cell power supply wiring 17, 18, and auxiliary power main lines 45, 46 shown in FIG. 1 above. The basic cell 11 includes two p-channel type MIS formed on the n-type well region 40.
FET (P,, P.) and two n-channel type Mr SFETs (N
Is it possible to have l, N, )? iflM I S FET
(CMOSFET). The p-channel MISFET (P., P2) has three p-type semiconductor regions 23.24.2 formed in parallel with each other.
5, one p-channel type MISFET (PI)
is composed of a p-type semiconductor region 24 located in the center of the upper p-type semiconductor region and a p-type semiconductor region 23 located at one end of the semiconductor region, and the other p-channel type MISFET (P2) is composed of a p-type semiconductor region 24 common to the p-channel type MISFET (P1) and a p-type semiconductor region 25 located at the other end of the p-type semiconductor regions. Further, the n-channel type MISFET (N+, Nz>) is formed by three n-type semiconductor regions 26 and 27 formed in parallel.
．． 28, one n-channel type MISFET (N
1) is composed of a p-type semiconductor region 27 located in the center of the n-type semiconductor region and an n-type semiconductor region 26 located at one end of the n-type semiconductor region, and the other n-channel MISFET (N2> is the above n
It is composed of an n-type semiconductor region 27 common to the channel type MISFET (N) and an n-type semiconductor region 28 located at the other end of the n-type semiconductor regions. Above M
A common gate electrode 21 is formed in the ISFET(P,,N,), and the same gate electrode 21 is formed in the ISFET(P,,N,).
A common gate electrode 22 is formed at (P2, N2).

A cell row 12 constituted by the plurality of basic cells 11
In the upper layer, a cell power supply wiring 1? is connected to the auxiliary power main line 45, 46 along the cell row l2. tl7,18 is formed. The cell power supply wiring 17, I'8 is formed in parallel to the first wiring layer. One cell power supply wiring 17 is connected to the auxiliary power main line 46 via a pad electrode 42 and a contact hole 36 opened in an interlayer insulation film (not shown), and is connected to a contact hole 29 opened in an interlayer insulation film (not shown). It is connected to the p-type semiconductor region 23 through it. The other cell power supply wiring 18 is connected to the auxiliary power main line 45 via a contact hole 39 formed in an interlayer insulating film (not shown), and a contact hole 30 formed in the interlayer insulating film (not shown).
It is connected to the n-type semiconductor region 26 via.

For example, the basic cell construction shown in this figure includes signal wiring 31, 3
4.37 and contact holes 29, 30, 32, 3
By adding 3.38, a two-person NAND circuit is formed. The cell power supply wiring 17 is connected to the p-type semiconductor region 23.25 through a contact hole 29, and the cell power supply wiring 18 is connected to the n-type semiconductor region 26 through a contact hole 30. The above two-person NA
Contact hole 3 is used to input a signal to the ND circuit.
A signal wiring 3 connected to the gate electrode 21 via 2
1 is formed, and a signal wiring 37 connected to the gate electrode 22 through a contact hole 38 is formed. Furthermore, a signal wiring 34 is formed for transmitting the signal output from the two-way NAND circuit to other circuits, and is connected to the p-type semiconductor region 24 and the n-type semiconductor region 28 via the contact hole 33.

FIG. 5 shows an equivalent circuit of the above two-manpower NAND circuit. The above two-man power NAND circuit consists of two p-channel MISFETs (P,, P2) connected in parallel and two n-channel MISFETs (P, P2) connected in series.
N,, N,). Now, if the signal wires 31 and 37 are set to high level at the same time, the p-channel type MISFET (P, .P.) will be in the t7 state, the n-channel type MISFET (N,, N2) will be in the on state, and the signal wire 34 will be in the low level. becomes. Also signal wiring 3
1.37 When one of them is set to low level and the other is set to high level, p-channel type M I S F E
Either one of T (Pl. P2) is turned on, and the signal wiring 34 becomes high level. Furthermore, signal wiring 3
1.37, when both are set to low level, p-channel type M
Both ISFETs (P, , P2) are turned on, and the signal wiring 34 is at a high level. In this manner, the two-manpower NAND circuit performs a logical AND NOT operation.

Next, the manufacturing process of the semiconductor integrated circuit device of Example 1 will be briefly explained using FIG. 6 (process flow diagram).

First, the logic to be mounted on the semiconductor substrate 10 is designed and a logic circuit diagram is created (50). Next, based on the above logic circuit diagram,
Automatic placement and routing system using a computer (Des
+gn Automat+on; DA) automatically places and connects the logic circuit <51>. In the automatic placement and routing system described above, first, based on the logic circuit diagram, connection information (NE) that can be handled by the automatic placement and routing system is
The upper 8 connection information is input to the automatic placement and routing system as T FILE) <511>.

Next, the base data of the automatic placement and routing system 517
<512>.

The base data <5 1 7> is information in which basic cell patterns are arranged on a semiconductor substrate. The power supply wiring is an auxiliary power supply main line (45,46), and the auxiliary power supply main line is arranged based on the power supply wiring number information <5 1 6>. That is, as mentioned above, based on the frequency and wiring size mainly used, an auxiliary power main line (45,46> extending in the column direction is arranged for every m basic cells, and a Auxiliary power main line (4 5.
4 Place 6). The above automatic placement of auxiliary power main lines allows the number of wires and wiring size to be freely changed based on the frequency and wiring size so that the current density within the area divided by the grid-like auxiliary power main lines can be optimally controlled. I can do it. The above-mentioned auxiliary power main line is arranged only in the cell area (20), and is not arranged in other areas because the arrangement of power supply wiring is prohibited.

In addition, among the power supply wiring, the power supply line (5, 6, 15.16)
and cell power supply wiring (17.18), base data <
517> as a fixed pattern.

Next, the designed logic circuit is automatically placed based on the connection information manually entered into the automatic placement and wiring system.<5 1 3
>. The above automatic placement of the logic circuit is performed using a module (logic function pattern) stored in the automatic placement and routing system <518
> is automatically arranged along the basic cell pattern.

Next, based on the above wiring information, the automatically arranged logic circuits (modinals) are automatically connected with signal wiring to complete the logic circuit information <514>. Next, the above logic circuit information completed by the automatic placement and routing system is converted into mask creation data based on the design rules <5 1
5>. The steps from the step <511> of inputting the connection information to the step <5 1 5> of converting into the mask creation data are automatically processed by the automatic placement and routing system.

Next, based on the above mask creation data, electron beam (EB)
) A wiring mask (manufacturing mask having a wiring pattern) is formed using a drawing device (52), and a device process is performed on the semiconductor wafer using the wiring mask (52), whereby a predetermined logic is mounted. The semiconductor integrated circuit device is substantially completed.

In this way, in manufacturing a mask slicing semiconductor integrated circuit device formed using an automatic placement and routing system, the power supply wiring number information of the automatic placement and routing system <5 1
6>, automatically arranging auxiliary power main lines (45.46) for each predetermined number of basic cells (11) <5 1
2>, then automatically arrange the wiring patterns of the logic circuits <5 1 3>, and automatically connect the logic circuits with signal wiring <514>, thereby connecting the auxiliary power main lines (45, 46) in advance. Since the current density is optimized, the auxiliary power main line is placed as a fixed pattern in the base data of the automatic placement and routing system, and after the stage of automatically connecting logic circuits, it is placed according to the current density in a predetermined area. This eliminates the step of re-arranging the auxiliary power main line, and the number of processing steps of the automatic placement and wiring system is reduced by the amount corresponding to this step, and the development period of a semiconductor integrated circuit device using the mask slicing method can be shortened.

As described above, according to the first embodiment, the following effects can be obtained.

(1). A power supply line 16 for power supply voltage VCC and a power supply line 15 for ground voltage v, , are formed in the wiring layer in the lower layer (second layer), and a power supply line 6 for power supply voltage VCC and Since the power supply line 5 for the ground voltage V55 is arranged so as to overlap, the total power supply when all the power supply lines for the power supply voltage vCc and the power supply line for the ground voltage VSS are formed in one wiring layer as in the conventional case. Compared to the line width, the above power supply voltage V. The total line width of the C power supply lines 6 and 16 and the total line width of the ground voltage VSS power supply line 5.15 can be expanded to the maximum of the conventional power supply line width, and the above power supply line 5.6,15
．． By reducing the current density within 16 compared to the conventional one, its EMD
Can improve resistance.

(2). According to (1) above, the total line width of the power supply lines 6 and 16 for the power supply voltage Vcc and the total line width of the power supply line 5.15 for the ground voltage VSS are reduced to the conventional total line width. EMD resistance can be improved more than before without expanding. In other words, the power supply voltage V is divided into two parts. 0 power supply lines 6, 16 and ground voltage V
The width of each of the SS power lines 5.15 can be made narrower than the width of the conventional total power line. As a result, the power supply lines 5 and 6 in the semiconductor integrated circuit device
．． The area occupied by the semiconductor integrated circuit device 15 and 16 is smaller than that of the prior art, thereby improving the degree of integration of the semiconductor integrated circuit device.

(3). By arranging the power supply lines 5.6 and 15.16 so as to overlap one another, a large coupling capacitance is formed between the two pairs of power supply lines. The power supply line with the above-mentioned large canobling capacity is the I/O cell 1.
3 and connected to the I/O cells 13, it is possible to alleviate and absorb power supply noise generated by the switching operations of a large number of the I/O cells 13. This increases the noise resistance of the semiconductor integrated circuit device and ensures stable operation.

(4) By arranging the power supply lines 6.15 so as to overlap vertically, the auxiliary power supply trunk lines 46.45 formed in the same wiring layer as the power supply lines 6 and 15 are also formed in upper and lower layers. Therefore, it is no longer necessary to intersect the upper eight auxiliary power main lines 45 and 46 three-dimensionally to prevent short circuits, as in the conventional case. Due to these, the above-mentioned auxiliary power main line 45.
46 becomes easier, and the development period of the semiconductor integrated circuit device can be shortened.

(5). A power supply line 16 for power supply electrician VCC and a power supply line 1 for ground voltage VSS are installed in the lower (second layer) wiring layer.
5 are arranged in parallel, the power supply lines 15.
The power supply to the I/O cell 13 formed directly below the I/O cell 16 is as follows.
This can be done easily as before.

[Example 2] Another embodiment of the invention is shown in FIG.

The difference between the second embodiment shown in this figure and the first embodiment is the auxiliary power main line. Note that the insulating film is also omitted in this figure.

In the first embodiment, the auxiliary power supply main lines 45 and 46 were formed in separate layers, but in the second embodiment, they are formed in parallel in the same wiring layer. In this case, among the auxiliary power supply trunks formed in a grid, the auxiliary power supply trunks 45 and 46, which are formed in either the vertical or horizontal direction, are connected to the second wiring layer. Auxiliary power main lines 45' and 46', which are formed in a direction perpendicular to .46, are formed parallel to the third wiring layer. The auxiliary N source trunk line 45 is connected to the power supply line 15 at both ends, but the other auxiliary power supply trunk line 46 formed in the same wiring layer as the auxiliary power supply trunk line 45 is connected to the power supply line 15 at both ends thereof. and is connected to a power supply line 6 formed in the upper layer. The auxiliary power main line 46 and the power line 6 are connected through a contact hole 50 formed in an insulating film (not shown), and the power line 6 is formed so as to extend directly above the contact hole 50. In addition, the above auxiliary power main line 46
'' is connected to the power supply line 6 at both ends thereof, but the auxiliary power supply main line 45°, which is formed in the same wiring layer as the auxiliary power supply main line 46', is connected to the power supply line 6 at both ends thereof. The auxiliary power main line 45° and the power line 15 are connected through a contact hole 50° formed in an insulating film (not shown), and the power line 15 is connected to the power line 15 through the contact hole 50°. The auxiliary power main line 45.
46, 45', and 46' are formed in separate layers above and below, so short circuits do not occur at the intersections formed in a grid pattern.
It is not necessary to form the auxiliary power main line three-dimensionally as in the conventional case. This facilitates the design of the auxiliary power main line as in the first embodiment. Note that the above power lines 5, 6,
15 and 16 are formed continuously along the outer periphery of the substrate 10, but in this figure, a portion is removed to make it easier to understand how they are formed so as to overlap vertically. . Also, the connection part of the power line 5.15 and 6.1
The connection part 6 is omitted.

According to the second embodiment, as in the first embodiment, the EMD resistance and noise resistance of the power supply lines 5, 6, 15.16 are improved, and the auxiliary power main line 45.46.45'
, 46' can be easily designed. However, in the case of the second embodiment, it is necessary to take into consideration the disadvantage that one of the pair of auxiliary power supply main lines needs to be connected to the power supply line through a contact hole.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to Examples 1 and 2, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is.

For example, in Embodiments 1 and 2, the power supply lines are composed of four lines, and two power lines with different potentials are arranged on the same wiring layer. However, the present invention is not necessarily limited to this. It is also possible to form only books, one in each vertically adjacent separate layer, so as to overlap one above the other. In this case, some kind of contrivance is required for electrical connection with the I/O cells formed in the lower layer.

Further, the width of the power supply line in the first and second embodiments was formed to be narrower than the width of the power supply line conventionally formed on the same wiring layer, but it is not necessarily limited to this. Two pairs of power supply lines having approximately the same width as the line may be formed so as to be stacked one above the other. In this case, the EMD resistance is further improved, but the degree of integration of the semiconductor integrated circuit device remains substantially the same as the conventional one.

Further, in Examples 1 and 2, all the power supply wiring is made of aluminum alloy, but it is not necessarily limited to this, and high melting point metals such as tungsten and molybdenum, or their silicides may be used as appropriate. Ru.

Further, although the gate arrays in the first and second embodiments are of a spread type, the gate array is not necessarily limited to this, and a fixed channel type can also be adopted.

Further, in the first and second embodiments, the power supply voltage supplied to the power supply line is the ground voltage and the positive power supply relative to the ground voltage, but it is not necessarily limited to this. One may be a negative power supply, and the other Power supply voltage is not limited to ground voltage.

In the above explanation, the invention made by the present inventor was mainly applied to a gate array type semiconductor integrated circuit device, which is the background field of application, but the present invention is not limited thereto. , standard cell type LSI, and other semiconductor integrated circuit devices. That is, the present invention can be applied to at least a semiconductor integrated circuit device having a multilayer wiring structure.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.

(1). By arranging the first power supply wiring to which the first power supply voltage is supplied and the second power supply wiring to which the second power supply voltage is supplied in vertically adjacent separate layers, the width of the power supply wiring can be reduced. The current density in the power supply wiring can be reduced by forming it widely, and the EMD resistance of the power supply wiring can be improved.

(2) Furthermore, by overlapping some or all of the power supply wirings, the area occupied by the power supply wirings can be reduced and the degree of integration of the semiconductor integrated circuit device can be improved.

(3). Furthermore, short circuits can be prevented without forming the power supply wiring three-dimensionally at the intersections of the power supply wiring, and the design of the power supply wiring becomes easy.

4 (4). Furthermore, by forming the first power supply wiring and the second power supply wiring in parallel so as to overlap with each other in vertically adjacent different layers, the coupling capacitance formed between the power supply wiring can be reduced by forming the coupling capacitance between the power supply wirings in the same wiring layer. The coupling capacitance is significantly increased compared to the coupling capacitance formed in the power supply wiring formed in parallel above, and the increased coupling capacitance alleviates and absorbs power supply noise, thereby preventing malfunction of the semiconductor integrated circuit due to upper power supply noise. This has the effect of being able to prevent.

(5). In addition, in the lower wiring layer, a first power wiring and a third power wiring to which different power supply voltages are individually supplied are formed. This has the effect of facilitating power supply to circuit elements. Furthermore, since different power supply voltages are supplied to the third power supply wiring and the fourth power supply wiring, which are formed so as to overlap each other vertically, the third power supply wiring and the fourth power supply wiring, which are formed to overlap each other, are supplied with different power supply voltages. This has the effect of making power supply easier.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device that is an embodiment of the present invention, FIG. 2 is a schematic plan view of a semiconductor substrate showing the arrangement of power supply wiring of this semiconductor integrated circuit device, and FIG. , a diagram showing the relationship between the basic number of cells, the frequency used, and the current density of this semiconductor integrated circuit device, and FIG. 4 is a partial enlarged view of a semiconductor substrate showing the circuit configuration formed in the cell area of this semiconductor integrated circuit device. 5 is an equivalent circuit diagram of the basic cell portion shown in FIG. 4, FIG. 6 is a process flow diagram showing the manufacturing process of this semiconductor integrated circuit device, and FIG. 7 is a diagram of the present invention. FIG. 3 is a schematic diagram showing another example of power supply wiring according to the invention. 5, 6, 15. 16... Power supply line, 10... Semiconductor substrate, 11... Basic cell, 12... Cell row, 13
...I/O cell, 14...Bonding pad, 1
7.18...Cell power supply wiring, 20...Cell area, 2
1.22...gate electrode, 23,24.25...p
type semiconductor region, 26, 27.28...n type semiconductor region, 29, 30, 32, 33, 36. 38, 39, 47.
48... Contact hole, 31, 34.37...
Signal wiring, 40... N-type well region, 41... P-type well region, 42... Pad electrode, 45, 46.45
',46'...Auxiliary power main line, 50,50°
...Contact hole.

Claims (1)

[Claims] 1. A multilayer wiring structure is provided, and a first power supply wiring to which a first power supply voltage is supplied and a second power supply wiring to which a second power supply voltage is supplied are arranged in different layers. A semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring and the second power supply wiring are arranged in parallel so as to overlap vertically adjacent different layers. 3. The semiconductor integrated circuit device according to claim 1, wherein a plurality of each of the first power supply wiring and the second power supply wiring are arranged in parallel. 4. Claim 1, wherein the first power supply wiring and the second power supply wiring are formed continuously along the outer periphery of the semiconductor substrate.
The semiconductor integrated circuit device described above. 5. A first auxiliary power main line and a second auxiliary power main line are arranged in separate layers in an upper layer of a cell area surrounded by the first power supply wiring and the second power supply wiring, and 5. The semiconductor integrated circuit according to claim 4, wherein an end of one auxiliary power supply main line is connected to the first power supply wiring, and an end of the second auxiliary power supply main line is connected to the second power supply wiring. Device. 6. The semiconductor integrated circuit device according to claim 5, wherein the first auxiliary power main line and the second auxiliary power main line are arranged in a grid pattern. 7. The first auxiliary power main line and the second auxiliary power main line are arranged in parallel, and the first auxiliary power main line and the second auxiliary power main line are arranged at different levels with a predetermined interval. 7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is formed as follows. 8. In the same wiring layer as the first power supply wiring, the second
A third power supply wiring to which a power supply voltage of is supplied is arranged in parallel with the first power supply wiring, and the first power supply voltage is supplied to the same wiring layer as the second power supply wiring. 3. A fourth power supply wiring is arranged in parallel with said second power supply wiring, and said third power supply wiring and said fourth power supply wiring are arranged in parallel so as to vertically overlap. semiconductor integrated circuit devices.