JPH03218065A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing semiconductor devices, particularly memory devices.

2. Description of the Related Art In recent years, there has been a strong demand for higher integration in semiconductor devices, especially memory devices.
(abbreviated as ), multi-gate structures are increasingly being used. An example of a conventional method for manufacturing a ROM having a multi-gate structure will be described below with reference to FIG.

As shown in FIG. 2(a), an impurity diffusion mask 7 made of a photoresist or the like corresponding to the ROM code to be stored is formed on the silicon substrate 1 via the gate insulating film 2,
By ion implanting impurities such as arsenic into the silicon substrate,
An impurity diffusion layer 8 for threshold voltage control is formed. Next, as shown in FIG. 2(b), a plurality of gate electrodes 3 are formed at equal intervals. Next, as shown in FIG. 2(C), a glabellar insulating film 5 is formed.

Problems to be Solved by the Invention In the conventional manufacturing method described above, the gate electrode is formed after forming the impurity diffusion layer corresponding to the ROM code, so it takes a long time from receiving an order for the ROM code to shipping it as a product. (hereinafter abbreviated as TAT) had a problem of being long. In order to shorten the TAT, a possible method is to form an interlayer insulating film in advance without forming an impurity diffusion layer, then form an impurity diffusion mask on the glabellar insulation, and write by ion implantation with a high acceleration voltage. However, in the multi-gate method described above, due to differences in the shape and thickness of the gate electrode and the glabellar insulating film in the gap between the electrodes, the diffusion depth varies greatly, making it difficult to control the impurity diffusion region. . In addition, when forming an impurity diffusion mask on the glabellar insulating film for the gate electrode, the alignment marks that serve as the reference for alignment go through many different diffusion processes, so they are easily deformed and misalignment increases, resulting in offset There is a high possibility that defects will occur.

The present invention solves these conventional problems,
Do not reduce the degree of integration. An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily shorten TAT.

Means for Solving the Problem In order to solve this problem, the present invention implants ions in advance into the gap between the gate electrodes to prevent offset after forming the gate electrodes, expands the mask alignment margin, and After forming the glabellar insulating film, the first interlayer insulating film is buried in the gate electrode by etching to the height of the gate electrode by anisotropic dry etching, and the gate electrode and the first glabellar insulating film are formed into a flat shape. Then, a second glabellar insulating film is formed thereon, an impurity diffusion mask is formed, and writing is performed by ion implantation with a high acceleration voltage.

By doing this, the mask alignment margin between the gate electrode and the impurity diffusion mask is expanded, and the impurity diffusion region of the channel portion of the MOS transistor can be easily controlled from above the glabella insulating film.

Example Hereinafter, R O of a multi-gate structure according to an example of the present invention will be explained.
An example of a method for manufacturing M will be explained with reference to FIG.

As shown in FIG. 1(a), a plurality of gate electrodes 3 are formed at equal intervals on a silicon substrate 1 with a gate insulating film 2 interposed therebetween. Next, as shown in FIG. 2(b), an impurity diffusion layer 4 for preventing offset is formed in the silicon substrate by ion implantation of an impurity such as arsenic into the gap between the gate electrodes, and a first glabella insulating film 5 is formed. form. Next, as shown in FIG. 2(c), the first glabellar insulating film is etched to the height of the gate electrode by anisotropic dry etching, and then a second glabellar insulating film is etched on the gate electrode and the first interlayer insulating film. A glabellar insulating film 6 is formed. Next, as shown in FIG. 2(d), an impurity diffusion mask 7 made of photoresist or the like corresponding to the ROM code to be stored is formed on the second glabellar insulating film, and ions of impurities such as arsenic are implanted. Thus, an impurity diffusion layer 8 for threshold voltage control is formed on the silicon substrate.

Effects of the Invention In the present invention, after forming the gate electrode, ion implantation is performed in advance into the gap between the gate electrodes to prevent offset, thereby expanding the mask alignment margin between the gate electrode and the impurity diffusion mask, and further improving the gap between the gate electrodes. A first glabellar insulating film was embedded in the electrode, the gate electrode and the interlayer insulating film were formed into a flat shape, and a second glabellar insulating film was formed thereon, and then an impurity diffusion mask was formed to provide a high acceleration voltage. Writing by ion implantation facilitates control of the impurity diffusion region in the channel portion of the MOS transistor from above the interlayer insulating film.

Therefore, TAT can be easily shortened, making it extremely useful for shortening the delivery time of ultra-large capacity memories.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to (d) are step-by-step cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2(a) is
-(C) are sectional views in the order of steps of the conventional example. ■... Silicon substrate, 2... Gate insulating film, 3... Gate electrode, 4... Impurity diffusion layer for offset prevention, 5... ...First interlayer insulating film, 6...Second interlayer insulating film, 7...
. . . Mask for impurity diffusion, 8 . . . Impurity diffusion layer for threshold voltage control.

Claims (1)

[Claims] One source diffusion layer and one source diffusion layer formed under the surface of the semiconductor substrate.
A plurality of gate electrodes are arranged in series on a semiconductor substrate located between two drain diffusion layers with a gate insulating film interposed therebetween.
M with an impermanent diffusion layer that controls the threshold voltage of
In the manufacturing process of an OS type transistor, a step of forming gate electrodes on a semiconductor substrate at equal intervals via a gate insulating film, a step of implanting ions into the gap between the gate electrodes,
a step of forming a first interlayer insulating film that also serves as planarization; a step of anisotropic dry etching the first interlayer insulating film;
A method for manufacturing a semiconductor device, comprising the steps of forming a second interlayer insulating film, forming an impurity diffusion mask on the second interlayer insulating film, and implanting ions.