JPH03218113A - Clock signal switching circuit - Google Patents

Abstract

PURPOSE:To prevent the production of a notch in a selected clock signal by using a clock signal output obtained by a 2nd switching circuit, synchronizing a selective signal with the clock signal and using the synchronized selective signal to select the clock signal by a 1st switching circuit. CONSTITUTION:This switching circuit is provided with the 2nd switching circuit 20 selecting two systems of clock signals 0, 1 by the selective signal S and having an uncertain time at a change in an opposite direction to that of a switching circuit 10 and with a synchronous circuit 30 sampling the selective signal S for synchronization with a signal outputted from the 2nd switching circuit 2. Thus, the clock signal output obtained by the 2nd switching circuit 20 is utilized to synchronize the selection signal S with the clock signal and the synchronized selective signal is used to select the clock signals 0, 1 by the switching circuit 10. Thus, the production of the notch in the selected clock signal is prevented and the clock signal is made stable, thereby improving the system reliability.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a clock signal switching circuit configured into two systems, and in particular, in the process of selecting one clock signal depending on the operating status of the system, the clock signal is distorted. Regarding circuits that switch without switching.

[Conventional technology]

Conventionally, as shown in FIG. 3, this type of clock signal switching circuit switches between clock signal 0 and clock signal 1.
A switching circuit 10 has been proposed that performs switching using a selection signal S that is completely asynchronous with a clock signal. This switching circuit 10
As shown in the equivalent circuit in FIG. 4, one NOT gate 11, four AND gates 12 to 15, and one O
The selection signal S is input to the gate 12.13, and the clock signal 0, 1 is input to the gate 14.15.
and the selected clock signal OUT from the gate 16.
It is configured to output .

[Problem to be solved by the invention]

However, in the conventional switching circuit described above, if the clock signal is at a high level at the moment when the selection signal S rises from a low level (LOW) to a high level (HIGH),
There is a problem in that a dent in the clock as shown in the time chart of FIG. 5 occurs.

The logic of this process will be explained using FIGS. 4 and 5.

First, when the selection signal S is at a low level, the gate l2 is at a high level and the gate 13 is at a low level.
5 is a low level, and the gate 14 outputs the clock signal O as it is, so the clock signal 0 is output from the gate 16 which is output by the OR logic of the gates 14 and 15.

Next, when the selection signal S rises from a low level to a high level, the gate 12 goes to a low level, and as a result, the gate 14
becomes a low level, but the gate 13 still remains at a low level due to the delay time of the gate 11. At this time, gate l4 and gate 15 both become low level, and gate l6 outputs a low level. In other words, if the clock signal to be outputted is at a high level, a low level will be outputted against the intention. After this delay time difference of the gate 1l, the gate 13 becomes high level, so the clock signal 1 is output from the gate 16 as expected, but the output clock signal does not match the time chart shown in Fig. 2. As you can see, a dent is formed.

Such a phenomenon occurs in the switching circuit 10 only when the selection signal logically changes from a low level to a high level.

This recess is used in digital signal processing systems.
Since it is regarded as one clock signal, it causes equipment malfunctions in all situations, significantly impairing the reliability of the entire system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock signal switching circuit that prevents the generation of dents in the output clock signal and enables stable output of the clock signal.

[Means to solve the problem]

The clock signal switching circuit of the present invention is capable of selecting two systems of clock signals using a selection signal, and includes a first switching circuit in which an uncertain time exists when the selection signal changes in a certain direction; , and a second switching circuit in which an uncertain time exists when the change occurs in the opposite direction to that in the first switching circuit; and a synchronization circuit that samples and synchronizes the selection signal with the signal output from the second switching circuit. The clock signal in the first switching circuit is selected using the output signal of this synchronous circuit.

[Operation] According to the present invention, the selection signal is synchronized with the clock signal using the clock signal output obtained by the second switching circuit,
By selecting a clock signal by the first switching circuit using this synchronized selection signal, generation of a dent in the selected clock signal is prevented.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a clock signal switching circuit according to an embodiment of the present invention. In the figure, 1o is a switching circuit (first switching circuit I) similar to the conventional one shown in FIGS. 3 and 4, and 20 is a newly added second switching circuit. This second switching circuit 2
o consists of two AND gates 21.22 and one (7)N
It is composed of an OT gate 23 and one NOR gate 24. Furthermore, a synchronization circuit 30 composed of a D flip-flop is connected to the output side of the second switching circuit 20.

The selected clock signal 0.1 is input to the switching circuit 10 and the second switching circuit 2o, respectively, and the selection signal S is input to the second switching circuit 20. Here, the clock signal 0.1 and the selection signal S are each AND gate 2
1.22, the outputs of the AND gates 21 and 22 are input to the NOR gate 24, and the output of the NOR gate 24 is used as the output of the second switching circuit 20. Further, in this case, contrary to the switching circuit 10 shown in FIG. 4, the selection signal S is inputted via the NOT gate 23 to the AND gate 2I which manually inputs the clock signal 0.

The output of the second switching circuit 20 is input to the selection terminal of the switching circuit 10 via the synchronization circuit 30, and the switching circuit 10 is configured to output an output clock signal OUT.

The operation of the clock signal switching circuit having the above configuration will be explained.

First, the operation of the second switching circuit 20 will be explained. Clock signal O. When a selection signal S asynchronous with l is input, AN
The outputs of the D gates 21 and 22 are as shown in FIG. 2, and as a result, the output of the NOR gate 24 is also as shown in FIG. At this time, in the second switching circuit 20, the NOT gate 2
3 is connected to the clock signal O side, the selection signal S
When the level changes from a low level to a high level, the output of the NOR gate 24 is not damaged, but contrary to the switching circuit 10, when the level changes from a high level to a low level, the output signal is damaged at point P.

However, since the selection signal S is sampled by the synchronization circuit 30 at the output of the NOR gate 24, it becomes a signal synchronized with the clock signal 0.1 after that and is used as the selection signal of the switching circuit 10.

When this synchronized selection signal changes from a low level to a high level, it always changes when the clock signal is at a low level, so that as a result, a distortion-free clock signal is obtained as an output signal.

〔Effect of the invention〕

As explained above, the present invention provides a second switching circuit that can select two systems of clock signals using a selection signal, and in which an uncertain time exists when the clock signal changes in the opposite direction to that in the conventional switching circuit; Since a synchronization circuit is provided that samples and synchronizes the selection signal with the signal output from the circuit, the selection signal is synchronized with the clock signal using the clock signal output obtained from the second switching circuit, By selecting a clock signal by a switching circuit using this synchronized selection signal, it is possible to prevent the occurrence of a dent in the selected clock signal, and to stabilize the clock signal that is the reference signal in the system. This has the effect of improving the credibility of the system.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a clock signal switching circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing signal waveforms at various parts, Fig. 3 is a circuit diagram of a conventional clock signal switching circuit, and Fig. 4 is a diagram showing signal waveforms of various parts. FIG. 3 is an equivalent circuit diagram, and FIG. 5 is a diagram showing signal waveforms at various parts in FIG. 4. l...clock signal, lO... switching circuit, 1...
NOT gate, 12-15...AND gate, 6...
- OR gate, 20... second switching circuit, 1. 22・
...AND gate, 23...NOT gate, 4...
NOR gate, 30... synchronous circuit. Figure 4 Figure 14 Figure 5! Between yIjA

Claims (1)

[Claims] 1 or 2 systems of clock signals can be selected by the selection signal,
a first switching circuit in which an uncertain time exists when the selection signal changes in a certain direction; and a first switching circuit in which the clock signal can be selected by the selection signal, and an uncertain time exists when the selection signal changes in a direction opposite to that in the first switching circuit; a second switching circuit;
It is characterized by comprising a synchronization circuit that samples and synchronizes the selection signal with the signal output from the switching circuit, and configured so that the output signal of the synchronization circuit selects the clock signal of the first switching circuit. Clock signal switching circuit.