JPH03218147A - Communication control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control device, and particularly to a communication control device that can isolate a line fault when it occurs.

[Prior Art] Conventionally, a communication control device is generally known in which layer 1 and layer 2 are implemented using separate processors. , it is not possible to correctly notify the host device of the root cause.

As this type of prior art, for example, Japanese Patent Application Laid-Open No. 62-2457
Although a technique described in Japanese Patent No. 50 and the like is known, this conventional technique only describes a method of periodically collecting line failure information.

[Issue Mi to be Solved by the Invention] Since the above-mentioned conventional technology collects failure information as statistical information, the failure information collection cycle is long, and when a layer 2 protocol retryout occurs, the failure information is collected. There is a problem in that it is not possible to determine whether the latest failure information is the failure information immediately before the retryout occurred, and it is not possible to use this failure information to isolate the problem. There is.

Further, in the prior art, if the failure information collection cycle is shortened, the amount of data to be collected becomes enormous, resulting in a problem that a large amount of memory is required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above, to shorten the failure information collection cycle using a small amount of memory, and to collect the line status immediately before a layer 2 protocol retryout occurs. The purpose of the present invention is to provide a communication control device that achieves the following.

[Means for Solving the Problems] According to the present invention, the object is to provide two small capacity memories A1.
, A2 are prepared, and while resetting these memories alternately at short intervals, each time data reception occurs, line error information is set in the newly reset memory.

In addition, the above purpose is to provide a timer generation line in order to reliably collect line errors in a short cycle, and to set the interrupt level for line error collection using this timer to be higher than the normal data transmission completion interrupt and data reception interrupt. This is achieved by increasing the value to prevent the timer interrupt from sinking.

[Operation] By alternately resetting the two memories and alternately writing the collected line error information to the reset memory, the line error information is stored in the unreset memory even immediately after the memory reset. Therefore, it is possible to collect line error information for a minimum of one cycle of memory reset timing and a maximum of two cycles of memory reset timing.

Therefore, when a layer 2 protocol retryout occurs, if the line error information in the memory is read out, this line error information is the line error information immediately before the layer 2 protocol retryout occurred, and based on this error information, , it is possible to identify and isolate whether this fault is caused by the line or a link-level fault.

[Embodiment] Hereinafter, an embodiment of a communication control device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a line adapter, FIG. 3 is a diagram explaining the contents of a line error, and FIG. 4 is a block diagram showing the configuration of a line adapter. FIG. 5 is a sequence diagram illustrating the operation of one embodiment, and a time chart illustrating the period during which line error information is retained. 1 and 2, 10 is a host computer, l00 is a line adapter, 110, 340 are local buses, 120, 130 are line control lines, 121, 122
is a data driver/receiver; 123 is a line error collection line; 124 is a data transmission/reception control line; 140 is a memory A; 150 is a bus interface line; 160 is a processor A; 161 is a timer generation line; 170 is a shared bus; 300 is a communication control line. 310 is a communication control adapter control line, 320 is a shared memory, 330 is a host interface line, 350 is a processor B, and 360 is a memory B.

As shown in FIG. 1, the communication control device according to the present invention includes:
One communication control adapter 300 and multiple line adapters 1
00, the line adapter 100 implements layer 1, and the communication control adapter 300 implements layer 2.

The line adapter 100 can accommodate the lines 200a to 200d, and the communication control adapter 300 can connect up to eight line adapters 100 via the shared bus 170, and up to 16 can connect to the host. It can be connected to the computer IO.

The communication control adapter 300 includes a host interface line 330 that controls the interface with the host computer 10, arbitrates access to the shared memory 320,
A communication control adapter control line 310 that performs bus arbitration for the shared bus 170, and a processor B35 that is a main processor that controls the overall operation of the communication control adapter 300.
0, a memory 8360 in which a program running in the processor B350 is stored, and a processor B350,
A local bus B340 that connects the memory B360 to the communication control adapter control line 310, and a shared memory 3 accessible from the processor A160 and the processor B350.
20.

The line adapter 100 includes a line control line A120 that controls lines 200a and 200b, and lines 200c and 200d.
The interface between the line control line B130, which controls the line control line B130, the processor A160, which is a processor that controls the entire line adapter, the memory Al40, which stores programs running on the processor Al60 and line error information, and the communication control adapter 300. Bus interface line 150 and local bus 110 connecting these
It is composed of:

In one embodiment of the communication control device of the present invention configured as described above, data transferred from the host computer 10 is stored in the shared memory 320 via the host interface line 330 and the communication control adapter control line 310. Ru. Host interface line 330 allows processor B 35 to store data in shared memory 320.
Generates an interrupt for 0.

Upon receiving this interrupt, the processor B 350 creates a layer 2 frame, for example, an HDLC I frame, and after creating the frame, sets a data transmission request command in the shared memory 320, and sends the processor A 160 in the line adapter 100 Generates an interrupt for.

The processor A160 that has received this interrupt analyzes the command set in the shared memory 320 and issues a transmission instruction to the line control line Al20 or the line control line B130. The line control line A120 or the line control line B130 that receives this transmission instruction transmits data to any of the lines 200a to 200d.

Next, other configurations of the line adapter 100 other than those described above will be explained with reference to FIG. 2 showing the detailed configuration of the line adapter 100.

In FIG. 2, a timer generation line 161 is a line that generates periodic timer interrupts, and a line error collection line 123 is a line used by a data driver/receiver 121 that sends data to and receives data from the line. ,
This is a line for reading line errors detected at 122.

The processor A 160 uses the interrupt signal from the timer generation line 161 as a trigger to send the line error collection line 123 to the line error collection line 123.
The line error information read in is read out, and the line error information is set in, for example, the memory A1 in the memory Al40, and then the next trigger timing is set in the timer generation line 161. When the next trigger is issued from the timer generation line 161, the processor 160 performs the same processing as described above, but at this time, the line error information is stored in the memory A2 in the memory A.

As mentioned above, the embodiment of the present invention stores line error information as
The data will be stored alternately in memory A1 and memory A2. The interrupt signal generation cycle of the timer generation line 161 is determined by changing the value of the system setting table set in the memory Al40. For example, by changing the
It can be arbitrarily set up to 255 seconds.

As shown in Figure 3, the line error information is expressed as 8-bit data, and is divided into spare, long frame, buffer busy, overrun, short frame, abort detection, synchronization loss, and FCS error corresponding to each bit position. is configured to indicate the presence or absence of each error.

Next, the operations of the communication control adapter 300 and the line adapter lOO when a layer 2 protocol retryout occurs in the above-described embodiment of the present invention will be described with reference to the sequence shown in FIG. 4.

When transmitting data, the communication control adapter 300
A data transmission request command is issued to the line adapter 100 by interrupt. This data transmission request command is written by the communication control adapter 300 on the shared memory 320, and triggered by the interrupt, the line adapter 10
0 is passed to the line adapter 100 by reading this.

When the line adapter 100 receives this data transmission request command, it uses the data driver/receiver to transmit data I(0,0) to the other communication device.

At this time, the destination address and data length of the transmission data are those added to the data transmission request command.

When the data transmission is completed, the data driver/receiver generates an interrupt to processor A160. In response to this interrupt, the line adapter 100 sets a transmission completion interrupt response in the shared memory 320 and interrupts the communication control adapter 300.

When the communication control adapter 300 receives this response, it issues an instruction to start the monitoring timer to the timer 370, and when the timer 370 times out, it interrupts the processor B, and uses this interrupt as a trigger to start the monitoring timer again.
A data transmission request command is issued to line adapter lOO.

On the other hand, in the line adapter 100, the data driver/
The receivers 121 and 122 perform an operation of checking for line errors each time they receive data and internally retaining the check results. Furthermore, the processor A 160 receives timer interrupts from the timer generation line 161 at predetermined intervals and issues an error collection instruction to the line error collection line 123.

The line error collection line 123 reads line error information detected and held by the data driver/receiver each time data is received, and temporarily stores it in a register within its own line error collection line. The line error information stored in this register is stored in the memory A140 by the processor A160.
The data is stored in memory A1 within the memory A1. At this time, the memory A1 has been reset by a timer interrupt from the timer generation line 161.

After storing the line error information in the memory AI in the memory A140, the processor A160 issues an error factor reset instruction to the line error collection line 123, clears the register in the line error collection line 123 to "0°," The error in the data driver/receiver is reset.Furthermore, the processor A160 gives an interrupt generation instruction to the timer generation line 181 in order to obtain a trigger for reading the next line error information.

In the line adapter 100, each time a timer interrupt occurs on the timer generation line 161, the memories A1 and A2 in the memory 140 are alternately reset and line error information is collected, and the collected line error information is stored in the memory A14.
The operation of alternately storing data into the memories A1 and A2 within 0 is continued.

During such an operation, when the communication control adapter 300 detects a layer 2 protocol retryout, the communication control adapter 300 issues a line error information read command to the line adapter 100.

When the line adapter 100 receives this command, the processor A160 in the line adapter 100 stores the memory A1.
, A2, performs the logical OR of the contents of both read information, writes this result to the shared memory 320,
A line error information notification response is issued to the communication control adapter 300.

Processor B350 in communication control adapter 300, which received this line error information notification response, analyzes the contents of the line error information. In the case of embodiments of the invention,
The line error information is configured as explained in FIG. 3, so if the line error information is AH “0”,
If there is no line error and AH is not “O”, “1”
It can be determined that a line error has occurred corresponding to the bit position marked with ".

As a result of this determination, the communication control adapter 300 notifies the host computer 10, which is a host device, of a link error in the case of an error other than a line error, and notifies the line error in the case of a line error.

Next, the line error information collection period will be explained with reference to the timing chart shown in FIG.

In FIG. 5, interrupt timings T1 from the timer interrupt generation line 161 occur at equal intervals (although they appear to be different in the figure), and memories A1 and A2 are cleared alternately. On the other hand, line error information is stored in a memory that is cleared every time data reception occurs.

Therefore, after the memory reset 1 occurs, the contents of the memory Al are held until the memory reset 3 occurs, and after the memory reset 2 occurs, the contents of the memory A2 are held until the memory reset 4 occurs. will be retained. In the example shown in the figure, between the occurrence of memory reset 2 and the occurrence of memory reset 3, line error information 2,
3 occurs, and these error information are stored in memory reset 4.
It will be held in memory A2 until it occurs.

Therefore, if an error information read request is subsequently generated between memory resets 3 and 4, the error information held at this time becomes line error information 2 and 3.

In the embodiment of the present invention, even if the above-mentioned memory reset period, that is, the line error collection period is shortened, the memories AI, A
Since this does not cause an increase in the capacity of 2, it is possible to collect short-period line error information with a small memory capacity.

In the embodiment of the present invention described above, the line error information is
It may also be stored in a register instead of memory.

Further, the line error information can be changed depending on the physical characteristics of the line. Furthermore, since the data transmission/reception control line can read the signal of the layer I physical interface, failures can be effectively isolated by using this interface signal and line error information together.

[Effects of the Invention] As explained above, according to the present invention, it is possible to easily determine whether the cause of a layer 2 protocol error is due to line failure or due to the other party's communication device using a small amount of information. By alternately storing line error information in two memories and performing a logical sum of the contents of both memories in response to a read instruction, it is possible to accurately grasp the line status immediately before the read instruction.

In addition, for each communication control adapter and line adapter,
By including a processor, the present invention can be applied even when the communication control device has a multiprocessor configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a line adapter, FIG. 3 is a diagram explaining the contents of a line error, and FIG. 4 is a block diagram showing the configuration of a line adapter. FIG. 5 is a sequence diagram illustrating the operation of one embodiment, and a time chart illustrating the period during which line error information is retained. 10...Host computer, lOO...
...Line adapter, 110, 340...Local bus, 120, 130...Line control line, 1
21, 122... Data driver/receiver, 123... Line error collection line, 124...
...Data transmission/reception control line, 140...Memory A, 150...Bus interface line,
160... Processor A, 16l...
Timer generation line, 170...Shared bus, 300
...Communication control adapter, 310...Communication control adapter control line, 320...Shared memory, 33O...Host interface line, 3
50...Processor B, 360...Memory B.

Claims (1)

[Claims] 1. In a communication control device that realizes layer 1 and layer 2 using separate processors, it is equipped with two small-capacity memories, and resets these memories alternately in short cycles, each time data reception occurs. A communication control device characterized in that line error information is set in a newly reset memory, and when a layer 2 protocol retryout occurs, the line error information set in the memory is notified to a higher-level device.