JPH03218177A - Clamping device for video signal - Google Patents

Abstract

PURPOSE:To effectively reduce a jagged low frequency non-linear distortion generated in a vertical synchronizing(VS) signal part at the time of adding a ghost by inhibiting the use of a pulse included in the VS signal part of a video signal out of a horizontal synchronizing(HS) pulse or a composite synchronizing signal. CONSTITUTION:The clamping device is provided with a VS pulse reproducing means 30 for separating and reproducing a VS pulse from a video signal 10 and a pulse synthesizing means 32 for synthesizing the reproduced VS pulse and a HS pulse and forming a clamp pulse excluding the HS pulse included in the VS pulse period. Thereby, clamping is not executed in the VS signal period, the video signal is biased almost at a constant potential and the video signal level is maintained at the level clamped before the VS signal period, so that the generation of unnecessary low frequency distortion can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to video equipment. This relates to a video signal clamping device that is used in broadcast receiving equipment, and is particularly suitable for vedestal clamping of television video signals that have undergone waveform distortion such as ghosting. [Prior Art] Conventionally, a television receiver As an example of a video signal clamping device commonly used in such applications, there is one shown in FIG. 4, for example. In the figure, a television video signal is manually input to a terminal IO. This terminal lO is connected to the amplifier 12. Each is connected to the input side of the synchronous separation circuit l4. The output side of the amplifier l2 is connected to one power side of the clamp circuit l6 having a rather long discharge time constant circuit, and the output side of the synchronous separation circuit 14 is connected to the input side of the horizontal synchronous pulse regeneration circuit 18. . The output side of this horizontal synchronizing pulse reproducing circuit l8 is connected to the other human power side of the clamp circuit 16, and the clamped video signal is output from this clamp circuit l6.

Among the above-mentioned units, the amplifier 10 may be configured to have a simple buffer function, or may have a band-limiting low-pass filter (LPF) as a function. The synchronization separation circuit l4 is a well-known circuit, and is used to separate the composite synchronization signal.

In addition, in the horizontal synchronization pulse regeneration circuit 18, the simplest method is to capture the timing of the leading edge of the human cabulus by differentiation, and to capture the periodicity of the human cabulus and remove the equalized pulse portion to generate the horizontal synchronization pulse. is now played. Note that there may be a configuration in which a PLL circuit is used to reproduce the horizontal synchronization pulse. In this example, since the reproduction horizontal synchronization pulse is used for clamping, it is often extracted as a medium-sized pulse train of equalization pulses, which is slightly narrower than the pulse width of the original horizontal synchronization signal.

Next, the clamp circuit l6 includes NPN transistors Q1, . . . Q5, a resistor R1, and
, . . R5, a capacitor C1, and a clamp reference voltage source v8. In addition, the terminal 20 is connected to a DC voltage ■ for driving. C is applied and terminals 22.24
is an amplifier 12. The output sides of the horizontal synchronization pulse regeneration circuit 18 are connected to each other.

Among the above components, the transistor Q and the resistor R1 constitute a low impedance output buffer. Also, high impedance input is provided by transistor Q5 and resistor R5. A low impedance output buffer is configured. Transistor Q. ．． The bases of Q4 are commonly connected to form an analog switch. This analog switch is driven by transistor Q2. Resistor R2, R. ．． R. This is done by a clamp pulse output from a drive circuit configured by.

Next, regarding the operation of the conventional example configured as above,
This will be explained with reference to the time chart shown in FIG. Note that FIG. 6 shows a waveform near the vertical synchronization signal, which is the portion of the video signal that is of interest in the present invention.

A television video signal shown in FIG.
(see figure). This television video signal is
It is also added to the synchronization separation circuit 14, where the composite synchronization signal is separated. The separated composite synchronizing signal is inputted to the horizontal synchronizing pulse reproducing circuit 18, where the horizontal synchronizing pulse (see FIG. 2B) is regenerated. This horizontal synchronizing pulse is used as a clamp pulse by the clamp circuit l6.
is supplied to terminal 24 of.

Next, in the clamp circuit 16, the television video signal supplied to the terminal 22 (almost the same as fAl in the figure) is transferred to the transistor Q. The DC component is further cut off by the capacitor C1, and then the transistor Q. ．． Q4
It is output to the analog switch side configured as follows. The clamp pulse input to the terminal 24 is input to this analog switch as a negative polarity clamp pulse via the transistor Q2. By this, transistor Q
3. Then, Q4 becomes "ON" and the television video signal is clamped to the reference voltage vll. The points to be clamped are the horizontal synchronization signal, the vertical synchronization signal, and the leading edge of the equalization pulse. The clamped video signal is output to the outside via transistor Q5.

[Problem to be solved by the invention] As described above, the television video signal is
In the case of a normal signal as shown in FIG. 1, the desired clamping operation can be performed without any trouble even in the prior art. However, a problem occurs when a ghost generated by multipath in the transmission system, such as reflection from a building, is included in the video signal as shown in the figure fcl.

That is, in this case, a step difference ΔV occurs between the voltage at the tip of the equalization pulse and the potential at the tip of the vertical synchronization signal. Although not shown in the figure, the potential at the tip of the horizontal synchronization signal is the same as that of the equalization pulse. When such a video signal is subjected to signal processing by the clamp circuit shown in FIG. 5, the video signal after clamping becomes as shown in FIG. occurs. The shape of this waveform distortion is related to the discharge path and discharge time constant of the electric charge charged in the capacitor C, but the waveform is generally like this. This distortion is so-called nonlinear distortion, and once the waveform has become like this, it is almost impossible to return it to the original shape shown in Figure 4 (Cl). If the video signal is supplied to a monitor TV, etc., vertical synchronization may become difficult to achieve, resulting in problems such as synchronization being lost.Furthermore, if ghost removal is performed on such video signals using a ghost removal device, etc. , vertical synchronization becomes even more difficult.

As a clamping pulse, instead of the horizontal synchronizing pulse (or a pulse with a slightly narrower width) shown in FIG. However, even in this case, the above problem is not solved and the same phenomenon occurs.

As described above, according to the prior art, when a video signal includes waveform distortion such as a ghost, the amplitude of the ghost etc.
phase. Although it depends on the delay time, there is generally a disadvantage that zag-like low frequency nonlinear distortion occurs in the vertical synchronization signal portion.

The present invention has been made in view of the above points, and is capable of satisfactorily reducing the zag-like low-frequency nonlinear distortion that occurs in the vertical synchronization signal portion when the input video signal contains ghosts. Its purpose is to provide a signal clamping device.

[Means for Solving the Problems] One aspect of the present invention is to clamp a video signal to obtain a timing for clamping the video signal to a predetermined level by using a horizontal synchronizing pulse separated and reproduced from the video signal to be clamped. In the apparatus, a vertical synchronizing pulse reproducing means separates and reproduces a vertical synchronizing pulse from the video signal, and combines the vertical synchronizing pulse reproduced thereby with the horizontal synchronizing pulse. The present invention is characterized by comprising a pulse synthesizing means for generating a clamp pulse excluding a horizontal synchronizing pulse included in a vertical synchronizing pulse period.

According to another invention, a composite synchronization signal is used instead of the horizontal synchronization pulse.

[Operation] According to the present invention, the clamp pulses supplied to the clamp circuit are synthesized excluding the horizontal synchronization pulse or composite synchronization signal included in the vertical synchronization pulse period. As a result, clamping is not performed during the vertical synchronizing signal period, and the voltage appears to be biased at a substantially constant potential. The video signal level is maintained at the level clamped before the vertical synchronization signal period, and unnecessary low-frequency distortion is reduced.

[Embodiments] Hereinafter, embodiments of a video signal clamping device according to the present invention will be described with reference to the accompanying drawings. Note that the same reference numerals are used for the same components as in the conventional example described above.

<First Embodiment> First, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. In FIG. 1, the output side of the above-mentioned synchronization separation circuit l4 is connected to the input side of a vertical synchronization pulse regeneration circuit 30 as well as the horizontal synchronization pulse regeneration circuit l8. These synchronous pulse regeneration circuits 18.30
Each output side is connected to the input side of the combining circuit 32, respectively. The output side of this synthesis circuit 32 is connected to the clamp pulse input side of the clamp circuit 16.

Among the above-mentioned parts, the vertical synchronization pulse regeneration cycle 30 applies a low-pass filter that can sufficiently suppress the horizontal synchronization signal and equalization pulse to the composite synchronization signal supplied from the synchronization separation circuit 14, and the remaining 3H (horizontal scanning period) width vertical synchronizing signal pulses are separated and reproduced using a comparator or the like. Next, the synthesis circuit 32 performs the following calculation based on the vertical synchronizing pulse vS supplied from the vertical synchronizing pulse reproducing circuit 30 and the horizontal synchronizing pulse HS supplied from the horizontal synchronizing pulse reproducing circuit 18. This is to reproduce the clamp pulse CP.

ff = VS-W Ding ・・・・・・・・・・・・
(11 According to this formula (1+), when the horizontal synchronizing pulse HS is the logical value rL4, the vertical synchronizing pulse vS is the logical value r
When the logic value is “L” as the clamp pulse CP,
” pulse will be obtained.

The synthesis circuit 32 that performs such operations is a gate circuit composed of an inverter and an AND gate.

Next, the operation of the first embodiment as described above will be explained with reference to FIG. First, as described above, the reproducing synchronizing pulse of the horizontal synchronizing pulse reproducing circuit l8 is
It becomes as shown in l. In addition, the vertical synchronization pulse regeneration circuit 3
The vertical synchronization pulse reproduced by 0 becomes as shown in FIG. In the combining circuit 32, the calculation of equation (1) is performed on these input pulses, and a combined signal shown as fcl in the figure is output as a clamp pulse. The clamp circuit 16 clamps the video signal including the ghost shown in FIG. 2(D) based on the clamp pulse.

Here, when comparing the clamp pulse used in the conventional example shown in the same figure (Al) and the clamp pulse used in the same figure (Cl) in this embodiment, it is found that the clamp pulse that was conventionally present in the part where the vertical synchronization signal exists is It can be seen that this is not the case in this embodiment.

When such a clamp pulse is input to the clamp circuit l6, there is a period in which there is no clamp pulse. In particular, clamping is not performed during the period when the vertical synchronization signal is present, and the previously clamped potential is output as a video signal. For this reason, as shown in the same figure (D), when a ghost is included in the input video signal, there is a potential difference △V between the tips of the equalization pulse (or horizontal synchronization signal) and the vertical synchronization signal. Even in cases where the video signal is clamped, it is possible to obtain a clamped output of the video signal without changing its shape.

<Second example> Next, a second embodiment of the present invention will be described.

This embodiment corresponds to the case where a composite synchronization signal is used as a clamp pulse in the conventional example described above. The configuration is as shown in FIG. 3, in which the horizontal synchronization pulse regeneration circuit 18 is omitted compared to the first embodiment described above, and the output side of the synchronization separation circuit l4 is directly connected to the other input of the synthesis circuit 32. It has a horizontal structure connected to the side.

According to this embodiment, the composite synchronization signal CS shown in FIG. 2 (iE) is used instead of the horizontal synchronization pulse shown in FIG.
This is combined with the vertical synchronizing pulse vS shown in FB) in the same figure to form the clamp pulse CP. Expressing this in a formula, similar to the above fil formula, τr=vs-τd...
...(2).

The clamp pulse in this second embodiment is shown in FIG.
As shown in the first embodiment, there is no clamp pulse in the portion where the vertical synchronization signal is present. Therefore, the period without clamp pulse. In particular, clamping is not performed during the period when the vertical synchronization signal is present, and the previously clamped potential is output as a video signal.

As a result, the occurrence of low-frequency distortion such as zag can be largely avoided.

Note that the present invention is not limited to the Doi embodiment; for example, the circuit configuration can be modified in various ways so as to achieve the same effect.

[Effects of the Invention] As explained above, according to the present invention, the pulse included in the vertical synchronization signal portion of the video signal out of the horizontal synchronization pulse or composite synchronization signal is not used for clamping. This has the effect that it is possible to satisfactorily reduce the zag-like low-frequency nonlinear distortion that occurs in the vertical synchronization signal portion when the signal is added.

[Brief explanation of drawings]

FIG. 1 shows a first example of a video signal clamping device according to the present invention.
FIG. 2 is a time chart showing the operation of the embodiment of the present invention, FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIGS. 4 and 5 are diagrams showing the conventional example. The configuration diagram shown in FIG. 6 is a time chart showing the operation of the conventional example. l2...Amplifier, 14-...Synchronization separation circuit, l6...
- Clamp circuit, l8... horizontal synchronization pulse regeneration circuit,
30... Vertical synchronization pulse regeneration circuit, 32... Synthesis circuit.

Claims (2)

[Claims] (1) In a video signal clamping device that obtains the timing to clamp the video signal to a predetermined level by using the horizontal synchronization pulse separated and reproduced from the video signal to be clamped, the vertical synchronization pulse is separated and reproduced from the video signal. a vertical synchronizing pulse reproducing means for regenerating the vertical synchronizing pulse, and synthesizing the vertical synchronizing pulse regenerated by the vertical synchronizing pulse and the horizontal synchronizing pulse,
1. A video signal clamping device comprising: pulse synthesis means for generating a clamp pulse excluding a horizontal synchronization pulse included in a vertical synchronization pulse period. (2) In a video signal clamping device that obtains timing for clamping the video signal to a predetermined level by using a composite synchronization signal separated and reproduced from the video signal to be clamped, the vertical synchronization pulse is separated and reproduced from the video signal. a vertical synchronizing pulse reproducing means for regenerating the vertical synchronizing pulse, and a pulse synthesizing means for synthesizing the vertical synchronizing pulse regenerated by the vertical synchronizing pulse and the composite synchronizing signal to generate a clamp pulse excluding the composite synchronizing signal included in the vertical synchronizing pulse period. A video signal clamping device comprising: