JPH03218224A - Failure detector - Google Patents

Abstract

PURPOSE:To facilitate investigation of the cause of an accident by equipping the failure detector of the gate driving circuit or base driving circuit of a switching element with a storage to store up gate signals or base signals every specified time. CONSTITUTION:A gate circuit 2 controls a GTO 1 through pulse amplifiers 15a and 15b with the signals of light/electricity conversion circuits 11a and 11b. The signals of the light/electricity conversion circuits 11a and 11b are entered to shift registers 34a and 34b through input signal changeover circuits 33a and 33b and the waveform of the specified bit is stored. Normally, the contents of the shift registers 34a and 34b are updated. If an inverter breaks down, a forced off-gate signal is supplied from a control circuit to the light/ electricity conversion circuit 11b and the output signals of the shift registers 34a and 34b are again inputted thereto. That is, the shift registers 34a and 34b store up the waveform just before a failure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a failure detection device for a base drive circuit or a gate drive circuit of a semiconductor switching element.

(Prior Art) As an example of a semiconductor switching element, a gate turn-off thyristor (hereinafter simply referred to as GTO) which is turned on and off by a gate current will be described below.

FIG. 5 is a block diagram showing an example of a conventional GTO gate drive circuit. In the same figure, 1 is a gate drive circuit that supplies predetermined on-gate current and off-gate current to the gate of GT0, 2 is a gate drive circuit that supplies predetermined on-gate current and off-gate current to the gate of GTO1, and 11a and llb are gate drive circuits. An optical/electrical conversion circuit 12a converts an on-gate signal (optical signal) and a control off-gate signal (optical signal) transmitted from a control device (not shown) into electrical signals; 12a is an optical/electrical conversion circuit 11;
A normal off-gate signal generation circuit generates an off-gate signal of a predetermined width at the falling edge of the output signal of the optical/electrical conversion circuit 1lb, and 12b is a control circuit that generates an off-gate signal of a predetermined width at the rising edge of the output signal of the optical/electrical conversion circuit 1lb. 15 is an off-gate signal generation circuit; 13 is an OR circuit; 15a is an on-gate pulse amplifier that amplifies the on-gate signal output from the optical/electric conversion circuit 11a to generate a predetermined on-gate current;
b is an off-gate pulse amplifier that amplifies the off-gate signal output from the OR circuit 13 and generates a predetermined off-gate current.

FIG. 6 is a diagram for explaining the operation of the gate drive circuit 2, in which (6a) is an on-gate signal output from the optical/electric conversion circuit 11a, and (6b) is an off-gate signal generation circuit 12a.
The off-gate signal of the output of (6c) is the gate drive circuit 2
The output current IG, (6d) shows an example of the waveform of the output voltage VG of the gate drive circuit 2.

Next, the operation of the conventional gate drive circuit 2 will be explained using FIGS. 5 and 6. In FIG. 5, when an on-gate signal (optical signal) is transmitted from a control device (not shown) to the optical/electrical conversion circuit 11a at a predetermined period, the signal is transmitted to the optical/electrical conversion circuit 11a (6a). It is converted into an electric signal shown in (6c) and further amplified into an on-gate current shown in period I (6c) by the on-gate pulse amplifier 15a. Further, at the falling edge of the rear end of the on-gate signal (6a), the off-gate signal generating circuit 12a generates the off-gate signal shown in (6b).

The off-gate signal is amplified by the off-gate pulse amplifier 15b to an off-gate current shown in period (3) of (6C).

If a failure occurs in the device including the GTO 1 and the gate drive circuit 2, a forced off-gate signal (optical signal) is transmitted from a control device (not shown) to the optical/electrical conversion circuit 11b. The signal is converted into an electrical signal by the optical/electrical conversion circuit 1'lb, and is further converted into an electrical signal by the forced off gate signal generation circuit 1.
2b generates an off-gate signal with a predetermined width, and the off-gate signal is amplified into the above-mentioned off-gate current by the off-gate pulse amplifier 15b. In addition, forced off-game-1
The signal is given to all gate drive circuits that make up the device at once in order to stop the device as quickly as possible in the event of a device failure, and as a result, the current flowing through GTO 1 is cut off all at once.

(Problems to be Solved by the Invention) A device using a plurality of conventional gate drive circuits 2 has the following problems.

For example, in a GTO inverter, if the GTOs of the upper and lower arms are turned on at the same time, a DC short circuit will occur and the function will often stop. The reasons why the GTOs of the upper and lower arms are turned on at the same time are the operation of the gate drive circuit 2 and the gate drive circuit 2.
There may be a malfunction of the control device that sends the gate signal 5. Therefore, in the past, in order to investigate the cause after a problem occurs, a method has often been adopted in which the output voltage or output current of the gate drive circuit 2 is monitored using a commercially available waveform recorder. However, the conventional method requires an insulated amplifier and current detection in order to input the output voltage or output current of the gate drive circuit 2 to a commercially available waveform recording device. Depending on the configuration of the device, it may be extremely difficult to attach these isolation amplifiers and current detectors to the device after a failure occurs. In addition, in a large-sized device using a large number of GTO1s, a large number of insulated amplifiers, current detectors, commercially available waveform recorders, etc. are also required, and the actual situation is that finding the cause of the problem costs a lot of money.

The present invention has been made in order to solve such problems, and an object of the present invention is to provide a failure detection device that allows easy investigation of the cause of failure.

[Configuration Code of the Invention (Means for Solving the Problems) In order to achieve the above object, the present invention stores a game signal or a base signal at predetermined time intervals, and stores the stored signal [7]. A storage means that sequentially outputs the output at predetermined time intervals after a desired time, and a signal that is output to the storage means in response to a signal for stopping the on/off control of the semiconductor switching element when an abnormality occurs in the gate drive circuit or the base drive circuit, etc. The present invention is characterized by comprising input signal switching means for switching the input from the gate signal or base signal to the output signal of the storage means.

(Function) By providing the above means, an abnormality occurs in the gate drive circuit or the base drive circuit, or an abnormality occurs in the output of the gate drive circuit or the base drive circuit due to external noise, etc., and the semiconductor switching element When a signal is generated to stop the on/off control of the vehicle, the gate signal or base signal immediately before the accident is stored in the storage means, so that it is easy to determine the cause of the accident from the timing of the accident and analysis of the signal.

(Example) An example of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, the names and operational functions of the parts designated by the same reference numerals as in FIG. 5 are the same, and their explanations will be omitted.

In FIG. 1, 30 is an evening lock pulse generation circuit that generates an evening lock pulse, and 33a is an optical/electrical conversion circuit 11a.
33b outputs the output signal of the off-gate signal generation circuit 12a and the output signal of the shift 1 register 34b according to the output signal of the optical/electrical conversion circuit 1lb. This is input signal switching means for switching. 34 a, 34b are n
A bit (n is an integer) shift register with n
It has serial registers (storage locations).

In FIG. 2, (2a) is the output signal (on-gate signal) waveform of the optical/electrical conversion circuit 11a, (2b) is the output waveform of the clock pulse generation circuit 30, (2c), (2d),
(2e) (2f), (2g) (2h) are the read waveforms of the shift register 34a at times t1, t2, t3, t4, t5, and t6, respectively. (21) is the waveform stored in the shift register 34a.

Here, if the period of the clock pulse is T, then n bits
・The storage time that can be stored on the shift register stand is (TX
n).

In FIG. 2, for example, the means signals read at the timing of the first to third clock pulses are each at logic level "1" and have a pulse width T, and are read at the timing of the fourth to sixth clock pulses. The input signals read at the timing of are stored in the shift register 34a for (TXn) seconds as signals having a logic level of "0" and a pulse width T.

Therefore, for example, an input signal read as a logic level "1" at the timing of the first clock pulse is (
TXn) seconds later, Schiff 1.
Appears at the output of register 34a. Similarly, the input signal read at logic level "1" (or "0") at the timing of the n-th clock pulse becomes a signal at logic level 9 "1" (or "0") after (Txn) seconds. Appears at the output of shift 1 register 34a.

During normal operation of the device including the gate drive circuit 2, the input signal switching circuit 33a outputs the output signal (
Since the on-game 1 signal) is switched so that it becomes the input signal of the shift register 34a, when a new manual signal is read, the shift 1 register 34a changes the old signal that was stored (TXn) seconds before that point. The signal disappears. On the other hand, when the inverter fails and stops, the control device (not shown) sends the light/electric conversion circuit of the gate drive circuit 2]. 1
A forced off-gate signal is applied to the optical/electrical conversion circuit 1.b. The output signal of 1b is the input signal switching circuit 33
a, the input signal switching circuit 33a performs a switching operation so that the output signal of the shift register 34a becomes the input signal of the shift register 34a instead of the output signal of the optical/electric conversion circuit 11a. Therefore, since the output signal is fed back to the input of the shift register 34a, the on-gate signal for (TXn) seconds before the forced off-gate signal is applied to the gate drive circuit 2 is stored.

The storage operation of the shift register 34b is performed by the shift register 34b.
This is the same as the storage operation of point a, and the output signal of the off-gate signal generation circuit 12a is normally stored.

In order to reproduce the signals stored in the shift registers 34a, 34b immediately before the failure occurs, the shift registers 34a,
An electromagnetic oscilloscope, synchroscope, etc. may be connected to the memory waveform output terminal 5]a151b of 34b. Note that the forced off-game 1 signal, which is the input switching signal of the shift registers 34a and 34b, is similarly stored in another shift register (not shown), and the output signal of the shift register is reproduced with an electromagnetic oscilloscope, synchronoscope, etc. The cause of the failure can be determined from the failure timing and waveform analysis.

FIG. 3 is a block diagram showing another embodiment of the present invention.
The difference from the figure is that the voltage monitoring point is the voltage between the gate and cathode of a semiconductor switching element, for example, GTO1. In FIG. 3, the names and operating functions of the parts 11 denoted by the same reference numerals as in FIG. 1 are the same, and their explanations will be omitted.

In FIG. 3, a differential amplifier 32a132b is a level conversion circuit that converts an input signal higher than a threshold value to logic "1" and a lower input signal to logic "0".

FIG. 4 is a diagram for explaining the operation of the gate drive circuit 2 in FIG. 3, where (4a) shows the output voltage of the differential amplifier 31,
(4b) is the output voltage of the level conversion circuit 32a, (4c)
shows the waveform of the output voltage of the level conversion circuit 32b.

In (4a), LVI and LV2 indicated by broken lines indicate the threshold values of the level conversion circuits 32a and 32b, respectively.

Although the present invention has been described above using the GTO gate drive circuit as an example, the present invention is not limited to the GTO gate drive circuit, but can also be applied to a normal thyristor gate drive circuit, Furthermore, the signal stored in the storage means may be the gate signal or the base signal 1 2 . In addition, in GTO etc., the voltage between the gate and cathode can be monitored in the same way.

[Effects of the Invention] According to the present invention, even if an abnormality occurs in a control device for a semiconductor switching element, the cause of the problem can be easily investigated. In addition, in the conventional method, a commercially available waveform recording device was installed after a problem occurred, which made it difficult to find the cause if the problem did not reproduce.In contrast, with the present invention, the waveform is constantly monitored, making it possible to reproduce the problem. For innocent accidents,
Especially effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, a waveform diagram for explaining the operation, Fig. 5 is a block diagram of a conventional device, and Fig. 6 is a diagram for explaining the operation of Fig. 5. be. 1... Semiconductor switching element, for example GT0, 213... Gate drive circuit, 11a, 1. 1 b... Optical/electric conversion circuit, 1.2a, 12b... Off-gate signal generation circuit, 1 3-OR circuit, 15a, 1. 5
b - Pulse amplifier, 33a, 33b, input signal switching means, 34a, 34b, storage means such as shift 1 register, 31, differential amplifier, 32a, 32b
...Level conversion circuit.

Claims (2)

[Claims] (1) In a failure detection device that detects a failure in a gate drive circuit or base drive circuit for controlling on/off of a semiconductor switching element, a gate signal or a base signal is stored at predetermined time intervals, and the stored signal is used at a desired time. A storage means that subsequently outputs the output at predetermined time intervals, and an input to the storage means in response to a signal for stopping the on/off control of the semiconductor switching element when an abnormality occurs in the gate drive circuit or the base drive circuit, etc. A failure detection device comprising input signal switching means for switching the output signal from the gate signal or the base signal to the output signal of the storage means. (2) In a failure detection device that detects a failure in a gate drive circuit for controlling on/off of a semiconductor switching element, a voltage signal between the gate and cathode of the semiconductor switching element is stored at predetermined intervals, and the stored voltage signal is outputted sequentially at predetermined time intervals after a desired time, and in response to a signal for stopping the on/off control of the semiconductor switching element when an abnormality occurs in the gate drive circuit or the like, the input to the storage means is output. A failure detection device comprising input signal switching means for switching from a voltage signal between the gate and cathode of the semiconductor switching element to an output signal of the storage means.