JPH11144468A - Address transition detection circuit - Google Patents

Abstract

(57) [Object] To provide an address transition detection circuit capable of preventing a malfunction of a memory even when a pulse having a short pulse width is input as an address signal. A first detection circuit provided in one-to-one correspondence with each address signal detects a transition of each address signal and outputs a pulse having a predetermined pulse width. , Calculate the logical sum of the pulses output from all the first detection circuits, detect the transition of the output signal of the logical sum circuit by the second detection circuit, and calculate the logical sum of the pulses output from the first detection circuit. The above problem is solved by outputting a pulse having a pulse width equal to or larger than the pulse width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address transition detection circuit for detecting a transition of an address signal input to a memory.

[0002]

2. Description of the Related Art An address transition detection circuit (hereinafter, referred to as an ATD circuit) detects a transition of an address signal input to a memory and generates a pulse having a predetermined pulse width. The ATD circuit controls the power supply to the memory for a predetermined period of time in accordance with the pulse width of the pulse generated by the ATD circuit after a transition of the address signal is detected, for example. It is used for applications such as reducing power consumption.

Hereinafter, a conventional ATD circuit and its problems will be described. FIG. 3 is a circuit diagram illustrating an example of a conventional ATD circuit. As shown in FIG. 1, a conventional ATD circuit 20 is provided in one-to-one correspondence with each address signal, and detects a transition of each address signal.
2, and an OR gate 14 for calculating the logical sum of the output signals of all the detection circuits 12, that is, detecting a transition as the entire address signal.

In the illustrated ATD circuit 20, the detection circuit 12 has a delay circuit 16 and an EXOR gate 18. Address signal A is supplied to delay circuit 16 and EXOR
The output signal B of the delay circuit 16 is input to one input terminal of the gate 18 and the other input terminal of the EXOR gate 18. All the output signals of the detection circuit 12 are input to the OR gate 14, and the output signal of the OR gate 14 is output as the output signal C of the ATD circuit 20.

FIG. 4 is a timing chart showing an example of the operation of the ATD circuit. FIG. 7A shows a normal operation, for example, when the address signal A transitions from a low level to a high level, and FIG. 7B shows an abnormal operation, for example, a delay time of the delay circuit 16 as an address signal A, such as a glitch. 7 shows waveforms of the address signal A, the output signal B of the delay circuit 16 and the output signal C of the ATD circuit 20 when a high-level pulse having the following pulse width is input.

First, as shown in FIG. 4A, in the normal operation of the ATD circuit 20, the address signal A is delayed by a predetermined fixed time by the delay circuit 16, and is delayed by the EXOR gate 18 with the address signal A. A mismatch with the output signal B of the circuit 16 is detected. The EXOR gate 18 outputs a high-level pulse having a pulse width corresponding to the delay time of the delay circuit 16, and this output signal is
Through the gate 14, the output signal C of the ATD circuit 20 is output.
Is output as

On the other hand, in the case of abnormal operation, that is, when a pulse having a pulse width equal to or less than the delay time of the delay circuit 16 is input as the address signal A, FIG.
As shown in (b), the address signal A and the delay circuit 1
The output signals B of No. 6 do not overlap in high level, and have a pulse width equal to the pulse width of the input pulse at a time interval corresponding to the delay time of the delay circuit 16 from the OR gate 14. Two consecutive high-level pulses are output.

As described above, in the conventional ATD circuit 20, as an address signal, for example, as a glitch,
When a short pulse having a pulse width shorter than the delay time of the delay circuit 16 is input, an incomplete pulse having a short pulse width is output. For this reason, in the memory using the conventional ATD circuit 20, power is not supplied to the memory before the access to the memory is completed, and the memory may malfunction.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problem of the prior art, and to prevent a malfunction of a memory even when a pulse having a short pulse width is input as an address signal. An object of the present invention is to provide an address transition detection circuit that can prevent the occurrence of an address transition.

[0010]

In order to achieve the above object, the present invention is provided in one-to-one correspondence with each address signal, and detects a transition of each address signal to generate a predetermined pulse. A first detection circuit that outputs a pulse having a width, an OR circuit that calculates a logical sum of the pulses output from all the first detection circuits, and a transition of an output signal of the OR circuit. A second detection circuit that outputs a pulse having a pulse width equal to or greater than the pulse width of the pulse output from the first detection circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an address transition detecting circuit according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings. FIG. 1 is a configuration circuit diagram of an embodiment of an address transition detection circuit of the present invention. An address transition detection circuit (hereinafter, referred to as an ATD circuit) 10 in the illustrated example detects a transition of an address signal and outputs a pulse having a predetermined pulse width. Basically, a detection circuit 12a and an OR gate 1
4 and a detection circuit 12b.

In the ATD circuit 10, the detection circuit 12a
Is for detecting a transition of each address signal and outputting a pulse having a predetermined pulse width, and is provided in one-to-one correspondence with each address signal. Each detection circuit 1
2a has a delay circuit 16 and an EXOR gate 18. Each address signal A is supplied to delay circuit 16 and EX
The signal is input to one input terminal of the OR gate 18 and EXOR
The output signal B of the delay circuit 16 is input to the other input terminal of the gate 18.

The delay circuit 16 delays the address signal by a predetermined time, and the EXOR gate 18 outputs the address signal A
And the output signal B of the delay circuit 16 are not matched. That is, in the detection circuit 12a, when the transition of the address signal A is not detected, the output signal of the EXOR gate 18 is held at a low level. On the other hand, when the transition of the address signal A is detected, Outputs a high-level pulse corresponding to the delay time of the delay circuit 16.

All the output signals of the detection circuit 12a are input to the OR gate 14, and the output signal C of the OR gate 14 is input to the detection circuit 12b. The OR gate 14 calculates the logical sum of the output signals of all the detection circuits 12a. That is, when at least one transition of the address signal is detected by the detection circuit 12a, the OR gate 14 outputs a high-level pulse having a pulse width corresponding to the delay time of the delay circuit 16.

The detection circuit 12b detects a transition of the output signal C of the OR gate 14, and outputs a pulse having a pulse width equal to or greater than the pulse width of the pulse output from the detection circuit 12a. When a high-level pulse is output from the OR gate 14, a high-level pulse having a pulse width equal to or longer than the delay time of the delay circuit 16 of the detection circuit 12a is output from the detection circuit 12b. The output signal of the detection circuit 12b is output as the output signal C 'of the ATD circuit 10.

Although a specific circuit configuration of the detection circuit 12b is not shown in FIG.
2b may have the same configuration as the detection circuit 12a. In this case, the delay times of the delay circuits 16 of the detection circuits 12a and 12b are set to be the same, and when the transition of the address signal is detected by the detection circuit 12a, the detection circuit 12b
Outputs a high-level pulse having a pulse width equivalent to twice the delay time of the delay circuit 16.

Further, as shown in FIG.
Is to detect a high-level pulse output from the OR gate 14, an OR gate is used as the detection circuit 12 b, for example, instead of the EXOR gate 18.
The logical sum of the output signal C of the OR gate 14 and the output signal of the delay circuit of the detection circuit 12b may be calculated.
In this case, the delay times of the delay circuits 16 of the detection circuits 12a and 12b may be the same or different.

In the ATD circuit 10, each detection circuit 12a detects a transition for each address signal, and the OR gate 14 calculates a logical sum of transition detection signals of each address signal. A transition as the entire address signal is detected. Thereafter, the detection circuit 12
b, the transition of the OR gate 14, that is, the transition of the detection signal of the transition as the entire address signal is detected,
This detection signal is output as the output signal C 'of the ATD circuit 10.

It should be noted that the ATD circuit 10 of the present invention is not limited to the circuit configuration shown in FIG.
It is needless to say that the circuit can be appropriately changed such as inverting the polarity of the output signal of the EXOR gate 18 and the OR gate 14 and changing the circuit accordingly. OR gate 14
Is inverted so that a low-level pulse is output, the EXO is used as the detection circuit 12b.
An AND gate may be used instead of the R gate 18.

In the present invention, for example, the detection circuit 1
When a signal having the same configuration as the detection circuit 12a is used as 2b, a pulse having a pulse width twice as large as the output signal C of the conventional ATD circuit 20 shown in FIG. As described above, in the ATD circuit 10 of the present invention, the detection circuit 12a,
By changing the delay time of the 12b delay circuit 16, the pulse width of the output signal C 'of the ATD circuit 10 can be appropriately adjusted.

The address transition detection circuit 10 of the present invention is basically as described above. Next, the difference between the operation of the address transition detection circuit 10 of the present invention and the operation of the conventional address transition detection circuit 20 shown in FIG. 3 will be described with reference to a timing chart shown in FIG. FIG. 2 (a),
(B), (c) and (d) are timing charts of one embodiment showing the operation of the present invention and the conventional address transition detection circuit.

FIGS. 2A and 2B show a case where a relatively short high-level pulse such as a glitch is input as an address signal, and FIG.
When a high-level pulse having a relatively long pulse width shorter than the delay time of the delay circuit 16 is input, FIG.
Shows the address signal A when the address signal transitions from low level to high level, the output signal C of the conventional ATD circuit 20 shown in FIG. 3, and the output signal C 'of the ATD circuit 10 of the present invention. is there.

First, as shown in FIG. 2A, when a relatively short pulse is inputted as the address signal A, the output signal C 'of the ATD circuit 10 of the present invention and the conventional A
Each of the output signals C of the TD circuit 20 holds a low level state. This is because, in the case of the ATD circuit 10 of the present invention, the input pulse is removed in an analogous manner in the course of propagating through the detection circuit 12a, the OR gate 14, and the detection circuit 12b. Therefore, in any case, the memory operates normally.

Subsequently, as shown in FIG. 2B, when a high-level pulse having a pulse width slightly longer than the pulse width shown in FIG. 2A is input as the address signal A, In the conventional ATD circuit 20, the input pulse is not removed in an analogous manner in the process of propagating through the detection circuit 12 and the OR gate 14, and an incomplete pulse having a short pulse width is output as the output signal C. However, there is a risk that the memory malfunctions.

On the other hand, in the ATD circuit 10 of the present invention, the OR signal corresponding to the output signal of the conventional ATD circuit 20 is used.
The incomplete high-level pulse with a short pulse width described above is generated in the output signal C of the gate 14, but this pulse is removed in an analog manner in the process of propagating through the detection circuit 12b. As shown in b), the output signal C ′ of the ATD circuit 10 is held at a low level. Therefore, malfunction of the memory can be prevented.

Subsequently, as shown in FIG. 2C, when a relatively long high-level pulse having a pulse width smaller than the delay time of the delay circuit 16 is input, the conventional ATD circuit 2
0, two consecutive high-level pulses having a pulse width equal to the pulse width of the pulse input as the address signal A are separated from the OR gate 14 by a time interval corresponding to the delay time of the delay circuit 16. Is output. For this reason, the memory may malfunction.

On the other hand, in the ATD circuit 10 of the present invention, the OR signal corresponding to the output signal of the conventional ATD circuit 20 is used.
As described above, in the output signal C of the gate 14, two short pulses that are shorter than the delay time of the delay circuit 16 are generated, and the pulse width of these pulses is extended by the detection circuit 12b, and the ATD A pulse having a pulse width longer than the delay time of the delay circuit 16 is output as the output signal C ′ of the circuit 10. Therefore, malfunction of the memory can be prevented.

As shown in FIG. 2D, when the address signal A transitions from the low level to the high level, that is, a pulse having a pulse width longer than the delay time of the delay circuit 16 as the address signal A. Is entered,
As the output signal C ′ of the ATD circuit 10 of the present invention and the output signal C of the conventional ATD circuit 20, a high-level pulse having a pulse width corresponding to the delay time of the delay circuit 16 is output. Therefore, in any case, the memory operates normally.

As described above, in the ATD circuit 10 of the present invention, since the transition of the output signal C of the OR gate 14 is further detected by the detection circuit 12b, the pulse having a pulse width smaller than the delay time of the delay circuit 16 is used. Is input, a relatively short pulse such as a glitch is removed in an analog manner by the detection circuit 12b, whereas a relatively long pulse which cannot be removed in an analog manner has a pulse width delayed. The pulse width is extended to be equal to or longer than the delay time of the circuit 16.

Therefore, according to the ATD circuit 10 of the present invention, the power supply to the memory is not stopped before the access to the memory is completed, and the malfunction of the memory can be prevented. As described above, the address transition detection circuit of the present invention has been described in detail. However, the present invention is not limited to the above-described embodiment, and various improvements and changes may be made without departing from the gist of the present invention. It is.

[0031]

As described in detail above, the address transition detecting circuit of the present invention detects the transition of each address signal by the first detecting circuit provided in one-to-one correspondence with each address signal. A pulse having a predetermined pulse width is detected and output, and a logical sum circuit calculates the logical sum of the pulses output from all the first detection circuits, and the second detection circuit outputs the output of the logical sum circuit. A signal having a pulse width equal to or greater than the pulse width of the pulse output from the first detection circuit upon detecting a signal transition is output.
Thus, in the address transition detection circuit of the present invention, even when a pulse having a relatively short pulse width is input as an address signal, a relatively short pulse such as a glitch is removed in an analog manner. , Relatively long pulses that cannot be removed analogously
Since the pulse width is extended, power is not supplied to the memory before the access to the memory is completed, so that malfunction of the memory can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of an address transition detection circuit of the present invention.

FIGS. 2 (a), (b), (c) and (d) are timing charts of an embodiment showing the operation of the present invention and the conventional address transition detection circuit.

FIG. 3 is a configuration circuit diagram of an example of a conventional address transition detection circuit.

FIGS. 4A and 4B are timing charts each showing an example of the operation of a conventional address transition detection circuit.

[Explanation of symbols]

 10, 20 address transition detection circuit 12, 12a, 12b detection circuit 14 OR gate 16 delay circuit 18 EXOR gate

Claims (1)

[Claims] A first detection circuit provided in one-to-one correspondence with each address signal to detect a transition of each address signal and output a pulse having a predetermined pulse width;
An OR circuit for calculating the logical sum of the pulses output from all the first detection circuits, and a pulse of the pulse output from the first detection circuit by detecting a transition of the output signal of the OR circuit And a second detection circuit that outputs a pulse having a pulse width equal to or greater than the width.