JPH03218517A - Arithmetic control unit - Google Patents

Abstract

PURPOSE:To shorten an arithmetic operation time by providing a counter which counts the number of arithmetic digits and which can be preset, setting the number of arithmetic digits in the counter so as to execute counting for respective digits, stopping the arithmetic operation in a prescribed digit corresponding to the number of the arithmetic digits, and shifting a system to a subsequent instruction. CONSTITUTION:The number of digits is set in the counter in an arithmetic digit number control circuit 25 by an arithmetic signal supplied to main ROM 15. The counter counts down or counts up for respective arithmetic operations of respective digits and an address counter 13 and an address auxiliary counter 16 are controlled after the arithmetic operation till the having set digit terminates. Then, the main ROM 15 and an instruction decoder 17 are controlled and the system shifts to the subsequent instruction. Consequently, processing is attained by one instruction even if the number of arithmetic digits increases, and the number of steps of the program in the main ROM 15 can be reduced. Thus, the arithmetic operation time can be shortened even if the number of arithmetic digits is large.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic desktop calculator, and particularly to an arithmetic control device thereof.

Conventionally, electronic desktop calculators have been constructed as shown in FIG. That is, the calculation signal input from the keyboard 11 is sent to the addition/subtraction circuit 12, address counter 13 . The signals are supplied to the main ROM 15 via the address decoders 14, respectively. The instruction decoder 17 sends each instruction signal and each A gate control signal is output. Address register (X) 1
8, Address register (Y) 19 is controlled and RAM2
The storage location of 0 is determined, and the arithmetic signal is stored at a predetermined location. Furthermore, the program in the main ROM 15 processes and determines the arithmetic signal, and the arithmetic operation number is displayed on the display 22 via the display circuit 21. Next, according to the program in the main ROM 15, the operand is temporarily stored in the accumulator 23 from the RAM 20 one digit at a time via the addition/subtraction circuit 12, and the operand is transferred one digit at a time through the addition/subtraction circuit 12.
is temporarily stored in the transfer register 24 via the adder/subtracter circuit 12, and the calculated value is stored in the R for each digit.
I'll save it to AM20. When the carry signal Ca is output from the adder/subtractor circuit l2 during the operation, the count value of the address auxiliary counter l6 is counted up, and the instruction decoder l7 is controlled to switch each command signal and each gate signal to perform a carry. It is done as it is done.

In such a configuration, it is wasteful to perform calculations on all bits of the RAM 2G, so the number of digits of the calculation number is temporarily stored in the transfer register 24, and the calculation is stopped when the number of digits is stored. I have to. in this case,
In order to determine whether the calculation has been performed up to a predetermined digit, for example, after completing one instruction, the calculated value is stored in the RAM.
20, the number of digits stored in the transfer register 24 is subtracted by "1" by the adding/subtracting circuit 12, and "0" is stored.
” The calculation stops at the digit that is reached.

Therefore, since only calculations are performed up to digits corresponding to the input number of calculation digits, calculation time can be shortened. However, since the addition/subtraction circuit 12 is used to determine the number of digits calculated, no calculation can be performed while counting the number of digits, and particularly when the number of digits is large, no great effect can be obtained.

This invention was made in view of the above circumstances,
The purpose is to provide an arithmetic control device that can sufficiently shorten the computation time even when the number of digits in the computation is large.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a schematic configuration of an electronic desktop calculator to which the present invention is applied. In addition to the conventional circuit shown in FIG. The number of digits to be calculated is set in this counter, and each digit is counted each time the calculation is performed, and the calculation is stopped at a predetermined digit.

In the figure, the same parts as in FIG. 1 are given the same reference numerals, and their explanation will be omitted. That is, the number of digits is set in the counter in the calculation digit number control circuit 25 by the calculation signal supplied to the main ROM 15, and the number of digits is counted down or counted up for each calculation of each digit, and after the calculation up to the set digit is completed. , address counter l3 and address auxiliary counter l6 are controlled, and the main ROM 15. The instruction decoder 17 is controlled to move to the next instruction.

In the above configuration, the instruction to store the data in the main ROM 15 at the address Ay(, -Ay,
Store it at AY address 20. Next, the auxiliary counter IB is
1, the cell address of the RAM 20 is counted up by one digit (Y+1).

When the address auxiliary counter l6 reaches "2", the operation digit number control circuit 25 is counted up by one digit (m+1). Here, the initial value m is data of the complement of the number of digits to be calculated. When the address auxiliary counter 16 reaches "3", the address auxiliary counter 16 is reset and the above-described operation is repeated for each digit in sequence unless a carry signal from the operation digit number control circuit 25 is output. Then, when a carry signal is generated, execution of the next instruction starts.

According to such a configuration, the calculated value for each digit is stored in the RAM 20.
It is possible to count up the number of calculation digits while memorizing the
Even if the number of calculation digits increases, it can be processed with one instruction. Therefore, the number of program steps in the main ROM 15 can be reduced.

In addition, since the calculation digit number control circuit 25 is controlled by one instruction, sufficient precharging time can be taken to determine the next address of the main ROM 15.
It is also possible to reduce the number of bits of the address auxiliary counter 1B in which the instruction is configured.
Even if the processing speed of the OM 15 is relatively slow, the calculation speed can be increased.

FIG. 3 shows one embodiment of the present invention. This figure is for explaining in detail the arithmetic control device, and shows a specific example of the structure of the arithmetic digit number control circuit 25 in the circuit shown in FIG. The preset signal m output from the instruction decoder l7 is input to the inverter circuit 2B. 27,
28. 29 and an AND circuit 30, and supplies the data to the ROM data select circuit 32 via a preset timing circuit 3l that presets the data in the main ROM 15 only once before calculating the first digit. This R
The OM data selection circuit 32 consists of AND circuits 33a to 33d that output the logical product of the output of the preset timing circuit 31 and the output of the main ROM 15, and each output is connected to a counter constituting the calculation digit number control counter circuit 34. There are 35 preset signals. This calculation digit number control counter circuit 34 receives a count up signal m +
1 is supplied via a 1-bit shift register 36 and an inverter circuit 37, and when the carry signal Ca is output from the counter 35, an AND circuit 39 for clearing the address auxiliary counter IB via the inverter circuit 38. is supplied to one input terminal of the carry determination OR circuit 41 via an inverter circuit 40.
is supplied to one input end of the . The count up signal m + 1 is sent to the other input terminal of the AND circuit 89 for clearing the address auxiliary counter 1B.
, and are supplied via an inverter circuit 42. Also,
The output of the inverter circuit 42 is connected to the other input terminal of the OR circuit 4l for carry determination.
The calculation digit number control circuit 25 is configured in such a manner that the calculation digit number control circuit 25 is supplied through the .

Furthermore, an inverter circuit 44 is connected to the output of the carry judgment OR circuit 4l and the instruction decoder l7.
．． Return signal Return supplied via 45
, and the output of the AND circuit 4B which performs an AND operation with the preset signal of the address auxiliary counter 16 is supplied to the address counter 13 via an inverter circuit 47. The preset signal of the address auxiliary counter l6 is
The carry signal Ca output from the addition/subtraction circuit l2 is input to an inverter circuit 48. The carry check signal C B check of the instruction decoder 17 is supplied to one end of the AND circuit 50 via the inverter circuit 5l, and the logical product is obtained. Further, the address auxiliary counter 16 is
A preset signal for the counter 35 of the calculation digit number control circuit 25, an AND circuit 39. The count value is cleared by an OR circuit 52 which outputs the logical sum of 46 outputs, and the count value is supplied to the instruction decoder 17.

FIG. 4 shows a timing chart of signals φ1 and φ2 for controlling each inverter circuit in the circuit shown in FIG.

As explained above, according to the present invention, a presettable counter for counting the number of digits to be calculated is provided, the number of digits to be calculated is set to this counter, the count is performed for each digit, and a predetermined value corresponding to the number of digits to be calculated is provided. Since the computation is configured to stop the computation at the digit and move on to the next instruction, an arithmetic control device that can shorten the computation time can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional electronic desk calculator, FIG. 2 is a block diagram showing a schematic configuration of an electronic desk calculator to which the present invention is applied, and FIG. 3 is a block diagram showing an embodiment of the invention. This circuit diagram is used to explain such an arithmetic control device, and shows a specific configuration example of the calculation digit number control circuit in the circuit shown in FIG. 2 above, and FIG. 4 is a timing chart of control signals for the circuit shown in FIG. 3 above. It is. l3...Address counter, 15...Main ROM
, 16... Address auxiliary counter, 17... Instruction decoder, 25... Arithmetic digit number control circuit,
31...Preset timing circuit, 32...RO
M data selection circuit, 34... Calculation digit number control counter circuit, 35... Counter, 39... AND circuit (
4l...OR circuit (second logic means), m...preset signal, m+1...count up signal (counting control signal).

Claims (1)

[Claims] In a microprogram type arithmetic device having an address counter and an address auxiliary counter, a preset signal output from an instruction decoder is supplied, and before calculating the first digit, data corresponding to the number of digits of the operation number in the main ROM is preset. ROM data selection means for selecting and outputting data corresponding to the number of digits of the operation number read from the main ROM when the output of the preset timing means is at a significant level; calculation digit number control counter means having a presettable counter for counting the number of digits of the calculation number supplied from the main ROM via the ROM data selection means; , a signal for clearing the address auxiliary counter based on the count up signal and a match signal indicating that the set number of digits output from the counter of the calculation digit number control counter means matches the count value; and a second logic means that outputs a signal for coincidence determination based on the coincidence signal and an inverted signal of the counting control signal, The number of digits of the calculation number is set in the calculation digit number control counter means, the calculation is performed for each calculation of each digit, and the calculation is stopped when the number of calculation digits reaches the set value of the counter. An arithmetic and control device characterized by: