JPH03218526A - information processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device using an electronic computer.

[Conventional technology]

FIG. 5 shows a block diagram of a conventional information processing device. In FIG. 5, 101 is an instruction decoding unit that decodes instructions, 102 is a register interference detection unit that detects register interference between consecutive instructions, and 103 is composed of a plurality of registers and holds 32-bit 0 data. 0 to do
A register section with registers, 104 is an integer operation section, 1
05 is a data transfer control unit that controls data transfer to and from a data cache (not shown), and 501 is a data address generation unit that generates a data address. 1)
0 is an instruction bus for transferring instructions, 1) 1 is a 32-bit immediate data path for transferring immediate data, 1) 2 is a 32-bit first internal data path, 1) 3 is a 32-bit second internal data path , 1) 4 is a 32-bit third internal data path, 1) 5 is a 32-bit data address bus, 1) 6
is a 32-bit store data bus that transfers to the data cache, 1) 7 is a 32-bit store data bus that transfers from the data cache.
Bit load data bus, 1) 8 is instruction decoding unit 101
There are control signals sent from the

FIG. 6 is a block diagram showing the internal configuration of the data address generation section 501 of the conventional information processing apparatus shown in FIG. In FIG. 6, 601 and 203 are 32-bit multiplexers, 202 is a 32-bit adder, and 204 is a 32-bit feedback latch. 1) 1 is 3
2-bit immediate data path, 1) 2 is the 32-bit first
Internal data path 1) 3 is a 32-bit second internal data path, each corresponding to the bus of the same name in FIG. 210 is the output of the multiplexer 601 and the adder 2
A 32-bit data path input to 02, 21) is the output of the adder 202 and is an addition result output bus. 1)5 is a data address bus, which corresponds to the data address bus 1)5 in FIG. 212 is feedback latch 2
Data address bus 1 held at 04 l clocks ago
)5 data is output. 2
13 and 214 are multiplexers 601.
These are a data select signal and an address hold signal that indicate the selection conditions of 203, and both are part of the control signal 1) 8 in FIG.

The operation of the conventional information processing apparatus configured as described above will be described below.

This conventional information processing device has a four-stage pipeline configuration, performs operations only between data in two 32-bit registers, performs inter-register operations in which the results are stored in the registers again, and exchanges data with memory. is an information processing device that uses a load/store architecture that performs operations only between memory and registers.

FIG. 7 is a timing diagram showing the operation of arithmetic instructions in a conventional information processing device. In FIG. 7, CI, C2, etc. are the processing cycles of a conventional information processing device, and A. B represents an arithmetic instruction to be processed.

First, the operation of arithmetic instructions in a conventional information processing device will be explained using FIGS. 5 and 7.

CI cycle. Fetch arithmetic instruction A and send it to instruction bus 1)0.

C2 cycle: Arithmetic instruction A sent to instruction bus 1) 0 is sent to instruction decoder 1
01 deciphers it. The instruction decoder 101 sends out control information according to the decoded instruction as a control signal 1)8, which is divided into the following two types of processing depending on the type of arithmetic instruction A.

(1) In the case of operation instruction A or operation between data in two 32-bit registers, the register unit 103 transfers the data in the two 32-bit registers specified by the control signal 1)8 to the first internal data bus l12 and the 2 Internal data bus 1) Send to 3.

(2) When the operation instruction A is an instruction to set immediate value data specified by the instruction in a specific register, the instruction decoding unit 101
sends the immediate data to the immediate data bus 1)1. Further, the register unit 103 sends the 32-bit 0 register data designated by the control signal 1)8 to the first internal data bus 1)2.

It also fetches arithmetic instruction B and sends it to instruction bus 1)0.

C3 cycle: The integer calculation unit 104 decodes the instruction decoding unit 101 in the C2 cycle.
Executes the operation specified by the control signal 1)8 sent by the controller. At this time, the data used for this calculation differs in the two types of cases explained in the C2 cycle.

(1) When operation instruction A is an operation between data in two 32-bit registers, the integer operation unit 104 executes the operation in the register unit 103 in the C2 cycle.
The data sent to the first internal data bus 1) 2 and the second internal data bus 1) 3 are input, and an operation is executed. After the calculation is completed, the calculation result is sent to the 32-bit third internal data bus 1)4.

(2) If the operation instruction A is an instruction to set immediate value data specified by the instruction in a specific register, the integer operation unit 104
inputs the immediate data sent by the instruction decoder 101 to the immediate data bus 1) 1 in the C2 cycle, and inputs the immediate data sent to the register unit 10.
3 performs addition with O sent to the first internal data bus 1)2. After the calculation is completed, the calculation result is sent to the 32-bit third internal data bus 1)4.

The processing for the arithmetic instruction B is the same as that for the arithmetic instruction A in the C2 cycle, so a detailed explanation will be omitted.

C4 cycle: The register unit 103 is activated by the integer operation unit 104 in the C3 cycle.
The data sent to the third internal data bus 1) 4 is stored in the register specified by the control signal 1) 8 in the 02 cycle.

The processing for the arithmetic instruction B is the same as that for the arithmetic instruction A in the C3 cycle, so a detailed explanation will be omitted.

Next, the operation of an instruction that requires memory address calculation in a conventional information processing device will be explained. An example is a store instruction that stores register data in memory.

FIGS. 8 and 9 are timing diagrams showing the operation of a store command for storing data in the memory of a conventional information processing device. Here, FIG. 8 shows a case where the memory address for storing data is calculated by adding the data of one 32-bit register and the immediate data specified in the store instruction (hereinafter referred to as l clock store). FIG. 9 shows a case where the sum of data in two 32-bit registers is calculated to calculate a memory address for storing data (hereinafter referred to as 2-clock store).

First, the operation of a one-clock store in a conventional information processing apparatus will be explained using FIGS. 5, 6, and 8. To simplify the explanation, the data of the register used for address calculation when storing 1 crotch is (r 1), the immediate value data is (immA), and the data of the register to be stored is (r2).
).

CI cycle: Fetch store instruction A and send it to instruction bus 1)0.

C2 cycle: The store instruction A sent to the instruction bus 1)0 is decoded by the instruction decoder 101. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immA) to the immediate data bus 1) 1.

Further, the register unit 103 sends the 32-bit register data (r1) used for calculating the memory address specified by the control signal 1)8 to the second internal data bus 1)3,
32-bit register data (r
2) to the first internal data bus 1)2.

Next, the operation of data address generation section 501 will be explained. The multiplexer 601 uses the information of the data select signal 213 sent out as the control signal 1)8.
Immediate data (immA) of immediate data path 1) 1 is output to data path 210. Each adder 202 has 32
Bit data path 210 and second internal data bus 1) 3
The immediate value data (immA) and data (r1
) and outputs the result to the addition result output bus 21). The multiplexer 203 outputs the data of the addition result output bus 21) to the data address bus 1) 5 based on the information of the address hold signal 214 sent as the control signal 1) 8. In this way, the address (immA) + (r1) of the data to be stored in the data address bus 1)5
Send out.

C3 cycle: address (im
Access the data cache using mA)+(r 1). Assume here that the data cache is hit. Further, the data transfer control unit 105 latches the data (r2) sent to the first internal data bus 1)2.

C4 cycle: The data transfer control unit 105 sends the data (r2) latched in the C3 cycle to the store data bus 1) 6 and stores it in the data cache.

Next, the operation of the two-clock store in the conventional information processing apparatus will be explained using FIGS. 5, 6, and 9. To simplify the explanation, the register data used for address calculation during two-clock storage are expressed as (r l) and (r 2),
Assume that the data in the register to be stored is (r3).

CI cycle: Fetch store instruction A and send it to instruction bus 1)0.

C2 cycle: The instruction decoder 101 decodes the store instruction A sent to the instruction bus 1)0, and sends out the control information as the control signal 1)8. The register unit 103 transfers the data (r 1) and (r 2) of two 32-bit registers used for memory address calculation specified by the control signal 1) 8 to the first internal data bus 1) 2 and the second internal data bus. 1) Send to 3.

Next, the operation of the data atlas generation unit 501 will be explained. The multiplexer 601 uses the information of the data select signal 213 sent out as the control signal 1)8.
The data on the internal data bus 1) 2 is output to the data bus 210. The adder 202 outputs data (r 1) . (r2) and outputs the result to the addition result output bus 21). multiplexer 20
3 is connected to the data address bus 1) 5 by the information of the address hold signal 214 sent as the control signal 1) 8.
The data of the addition result output bus 21) is output to. In this way, the address (r 1) + (r 2) of the data to be stored is sent to the data address bus 1)5.

C3 cycle: Since the store instruction A decoded in the C2 cycle is a 2-clock store, the instruction decoder 101 sends control information indicating the second cycle operation of a 2-clock store as a control signal 1)8.

The register unit 103 sends the data (r3) of the 32-bit register to be stored in the memory designated by the control signal 1)8 to the first internal data bus 1)2.

The data address generation unit 501 uses the information of the address hold signal 214 sent out as the control signal 1)8.
The result of addition in C3 cycle is transferred to data address bus 1)
5, the multiplexer 203 is controlled so that the data (r 1) + (r 2) on the hold data bus 212 is output to the data address bus 1)5. Furthermore, since the instruction decoded in the C2 cycle was a two-clock store instruction, the instruction decoding unit 101 does not decode the next instruction (no p).

C4 cycle: Address (r) sent to data address bus 1)5
1) Access the data cache using + (r 2). Here, assume that the data cache is hit. Further, the data transfer control unit 105 latches the data (r3) sent to the first internal data bus 1)2.

C5 cycle: The data transfer control unit 105 sends the data (r3) latched in the C4 cycle to the store data bus 1) 6 and stores it in the data cache.

As explained above, since the two-clock store instruction requires data in three registers, it requires five cycles to execute. Therefore, there is a blank space in the pipeline for l cycles.

Next, in a conventional information processing device, an arithmetic instruction that sets immediate value data in a specific register and an instruction that requires memory address calculation are consecutive, and the register used for the memory address calculation of the subsequent instruction is used for the preceding operation. The operation will be explained when the immediate value data matches the register to be set by the instruction.

A store instruction is given as an example of an instruction that requires memory address calculation.

FIG. 10 and FIG. 1) show a conventional information processing device in which an arithmetic instruction A and a store instruction B that set immediate value data in a specific register are consecutive, and a register is used for calculating the memory address of the subsequent store instruction B. FIG. 12 is a timing diagram showing the operation when the preceding operation instruction A matches the register in which immediate value data should be set (register interference). FIG. 1.theta. shows the case where the store instruction B is a 1-clock store, and FIG. 1) shows the case where the store instruction B is a 2-clock store.

Using FIG. 5, FIG. 6, and FIG. 10, an operation instruction A for setting immediate value data in a specific register of a conventional information processing device and a 1-clock store instruction B are used to calculate the memory address of the store instruction B. The operation when register interference occurs between the register used for the operation and the register to which immediate value data should be set by the preceding operation instruction A will be described. For simplicity of explanation, the register where interference occurs is rl, the immediate data of operation instruction 8 is (immA), the immediate data used for address calculation of l clock store instruction B is (immB),
De of registers to be completed. Let Itoyo be (r2).

C1 cycle: (1) Processing for operation instruction A Fetch arithmetic instruction A and send it to instruction bus 1)0.

C2 cycle: (1) Processing instruction bus 1 for operation instruction A Processing instruction A sent to instruction bus 1)
01 deciphers it. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immA) to the immediate data bus 1) 1.

Further, the register unit 103 sends the 32-bit 0 register data specified by the control signal 1)8 to the first internal data bus 1)2.

(2) Processing for store instruction B Fetch store instruction B and send it to instruction bus 1)0.

C3 cycle: (1) The integer arithmetic unit 104 processes the arithmetic instruction A, and the integer arithmetic unit 104 processes the instruction decoder 101 in the C2 cycle.
The immediate data (imm
A) is input, and addition with 0 sent from the register unit 103 to the first internal data bus 1) 2 is executed. After the calculation is completed,
The calculation result is sent to the 32-bit third internal data bus 1)4.

(2) Processing for store instruction B The instruction decoder 101 decodes the store instruction B sent to the instruction bus 1)0. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immB) to the immediate data bus 1) 1.

The register unit 103 also receives a control signal! Sends the 32-bit register data (r1) used for calculating the memory address specified in 18 to the second internal data bus 1)3,
32-bit register data (r
2) to the first internal data bus 1)2. however,
The data (r1) on the second internal data bus 1)3 is invalid data because the arithmetic instruction A has not been completed. In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 1
02 detects register interference between the register r1 used for calculating the memory address of the store instruction B and the register r1 to which immediate value data should be set in the preceding operation instruction A, and notifies the instruction decoder 101 of the result.

C4 cycle: (1) The processing register unit 103 for operation instruction A is processed by the integer operation unit 104 in the C3 cycle.
The immediate data (i) sent to the third internal data bus 1) 4
mmA) is stored in the register r1 specified by control signal 1)8 in cycle 02.

(2) The processing instruction decoder 1 (1) for the store instruction B determines whether the register interference detector 102 or 0
Since interference in register rl of store instruction B was detected in cycle 3, the decoding of store instruction B is continued in the same way as in cycle C3, control information is sent as control signal 1) 8, and immediate data (immB) is transferred to the immediate data bus. 1) Send to 1. The register unit 103 sends the 32-bit register data (rl) required for memory address calculation specified by the control signal 1) 8 to the second internal data bus 1) 3, and outputs the 32-bit register data (rl) to be stored in the memory. Register data (r2)
is sent to the first internal data bus 1)2.

Next, the operation of data address generation section 501 will be explained. The multiplexer 601 operates according to the data selection signal 213 sent as the control signal 1)8.
The immediate data (immB) of the immediate data bus 1) 1 is output to the data path 210. The adders 202 each have 3
2-bit data path 210 and second internal data bus 1)
The immediate value data (immB) and data (rl) outputted to 3 and 3 are added, and the result is output to the addition result output bus 21). The multiplexer 203 uses the information of the address hold signal 214 sent as the control signal 1)8,
The data of the addition result output bus 21) is output to the data address bus 1)5. Thus, the data address bus 1)
Address of data to be stored in 5 (immB) + (r
1) is sent.

The operations of the C5 and C6 cycles are the same as the C3 and C4 cycles explained in connection with the 1-clock store, so the explanation will be omitted (see the explanation regarding FIG. 8).

As explained above, if register interference occurs between register rl used for memory address calculation of 1-clock store instruction B and register r1 to which immediate data should be set in the preceding operation instruction, there will be a blank space in the pipeline for one cycle. I can do it. Here, the l clock store instruction is given as an example of an instruction that requires memory address calculation, but the same reason may apply to other instructions that require memory address calculation, such as a load instruction or a branch instruction, if the interference described above occurs. ,
A blank space appears on the vibe line for one cycle.

Similarly, if register interference occurs between the register used to calculate the memory address of the two-clock store instruction B and the register to which immediate data should be set in the preceding arithmetic instruction A, a blank space for two cycles is created in the pipeline. Regarding this operation, since the 1-clock store only changes to the 2-clock store, a detailed explanation will be omitted, but a timing diagram thereof is shown in Fig. 1).

[Problem to be solved by the invention]

However, in the above configuration, if register interference occurs between the register used for memory address calculation of an instruction that requires memory address calculation and the register to which immediate value data should be set in a preceding operation instruction, one cycle worth of data will be lost. If there is a blank space in the vibe line, especially if there is register interference between the register used for memory address calculation in the 2-clock store instruction and the register to which immediate data should be set in the preceding arithmetic instruction, there will be a blank space in the pipeline for 2 cycles. The problem was that it could be done.

An object of the present invention is to provide an information processing device that eliminates blank spaces in the pipeline and enables speeding up.

[Means to solve the problem]

The information processing device of the present invention includes: an immediate data latch that holds immediate data designated by an instruction; two multiplexers that receive the output of the immediate data latch as input;
It is equipped with an adder that adds the outputs of two multiplexers, and a register interference detection section that detects register interference between consecutive instructions. When the register interference detection unit detects a match between the register used for memory address calculation in the subsequent instruction and the register storing immediate data in the preceding instruction, . The adder calculates a memory address using the immediate data of the preceding instruction held by the immediate data latch, which is the output from one of the multiplexers.

Further, the information processing device of the present invention includes: an immediate data latch that holds immediate data designated by a command; and two multiplexers that receive the output of the immediate data latch as input.
an adder that adds the outputs of the two multiplexers;
A register interference detection unit that detects register interference between consecutive instructions is provided, and the instruction to store immediate data in a specific register and the data in the specific register are specified by the sum of the immediate data and data in another register. When instructions to store the address in the memory are consecutive, when the register interference detection unit detects a match between the register used for memory address calculation in the subsequent instruction and the register storing immediate data in the preceding instruction, the adder The address is calculated by adding the immediate data of the preceding instruction held in the immediate data latch, which is the output from one multiplexer, and the immediate data of the subsequent instruction, which is the output from the other multiplexer.

Furthermore, the information processing device of the present invention includes an immediate data latch that holds immediate data specified in an instruction, two multiplexers that receive the output of the immediate data latch as input, and an adder that adds the outputs of the two multiplexers. a register interference detection section that detects register interference between consecutive instructions; and a register section that is made up of a plurality of registers that can output data in two registers simultaneously; , when an instruction to store data in a specific register in a memory at an address specified by the sum of data in two other registers is consecutive, the register interference detection unit uses the register interference detection unit to calculate a memory address in the subsequent instruction. When a match is detected between the register and the register storing immediate data in the preceding instruction, the register section outputs the other register that did not match and the data of the register to be stored in memory, and the adder A memory address is calculated by adding the immediate data of the preceding instruction held by the immediate data latch output from the multiplexer and the data of the other register that did not match in the subsequent instruction output from the other multiplexer. .

[Effect]

With the above configuration, when an instruction to store immediate value data in a specific register and an instruction requiring memory address calculation are consecutive, the register interference detection unit registers a register used for memory address calculation in the subsequent instruction. When a match is detected between the register and the register storing immediate data in the preceding instruction, the adder calculates the memory address using the immediate data of the preceding instruction held by the immediate data latch, which is the output from one multiplexer. do.

In addition, the present invention provides that when an instruction to store immediate value data in a specific register and an instruction to store data in a specific register in a memory at an address specified by the sum of the immediate value data and data in another register are consecutive, the register When the interference detection unit detects a match between the register used for memory address calculation in the subsequent instruction and the register storing immediate data in the preceding instruction, the adder detects that the immediate data latch, which is the output from one multiplexer, is held. The address is calculated by adding the immediate value data of the preceding instruction and the immediate value data of the subsequent instruction which is output from the other multiplexer.

Furthermore, in the present invention, when an instruction to store immediate data in a specific register and an instruction to store the data in the specific register as a sum of the data in two other registers in the memory at a specified address, When the register interference detection unit detects a match between one register used for memory address calculation in a subsequent instruction and a register storing immediate data in a preceding instruction, the register unit detects a match between the other register that did not match and the memory. Outputs the data in the register to be stored, and detects a mismatch between the immediate data of the preceding instruction held by the adder or the immediate data latch output from one multiplexer and the subsequent instruction output from the other multiplexer. The memory address is calculated by adding the data in the other register.

〔Example〕

FIG. 1 shows a block diagram of an information processing apparatus in an embodiment of the present invention. In FIG. 1, 101 is an instruction decoding unit that decodes instructions; 102 is a register interference detection unit that detects register interference between consecutive instructions;
103 consists of multiple registers, 32 bits of 0
A register section with a 0 register that holds data, 10
4 is an integer calculation unit; 105 is a data transfer control unit that controls data transfer with a data cache (not shown);
106 is a data address generation unit that generates data addresses. 1) 0 is an instruction bus that transfers instructions, 1) 1 is a 32-bit immediate data path that transfers immediate data, 1
) 2 is the 32-bit first internal data path; 1) 3 is the 32-bit first internal data path;
1) 4 is a 32-bit third internal data path; 1) 5 is a 32-bit data address bus; 1) 6 is a 32-bit store data bus that transfers to the data cache; 1) 7 is a 32-bit load data bus transferred from the data cache; 1) 8 is a constraint signal sent from the instruction decoding unit 101; 1) 9 is a register interference detection signal sent from the register interference detection unit 102. .

FIG. 2 is a block diagram showing the internal configuration of the data address generation unit 106 of the information processing apparatus in the embodiment of FIG. 1. In the figure, 201, 203, 205, are 3
2-bit multiplexer, 202 is a 32-bit adder, 204 is a 32-bit feedback latch, 20
6 is a 32-bit immediate data latch. 1) 1 is 3
2-bit immediate data path, 1) 2 is the 32-bit first
Internal data path 1) 3 is a 32-bit second internal data path, each corresponding to the bus of the same name in FIG. 210 is the output of the multiplexer 201 and the adder 2
A 32-bit data path input to 02, 21) is the output of the adder 202 and is an addition result output bus. 1) 5 is a data address bus, which corresponds to data address bus 1) 5 in FIG. 212 is feedback latch 2
Data address bus 1 held at 04 l clocks ago
)5 data is output. 2
13 and 214 are multiplexers 20l and 203, respectively.
These are a data select signal and an address hold signal for instructing the selection conditions of , and both are part of the control signal 1) 8 in FIG. 215 and 216 are multiplexers 201 . They are a first register interference detection signal and a second register interference detection signal that instruct the selection conditions of 205, and both are the register interference detection signal 1 in FIG.
) is part of 9. In addition, 217 is a multiplexer 20
There is a 32-bit data bus input to the adder 203 at the output of 5.

The operation of the information processing apparatus in the embodiment of the present invention configured as described above will be described below.

The information processing device according to the embodiment of the present invention has a four-stage vibe line configuration, performs calculations only between data in two 32-bit registers, performs inter-register calculations in which the results are stored in the registers again, and performs inter-register calculations to store the results in the registers again. It is an information processing device that uses a load/store architecture in which data is exchanged only between memory and registers.

The operation of the arithmetic instruction and the operation of the 1-clock store and 2-clock store instructions of the information processing device in the embodiment of the present invention are similar to the operation of the conventional information processing device described in the section of the prior art, and therefore will not be described in detail. is omitted.

The following describes the operation of the information processing apparatus according to the embodiment of the present invention when an instruction for setting immediate value data in a specific register and an instruction requiring memory address calculation are consecutive. Examples of instructions that require memory address calculations include:
The cases of 1 clock store instruction, 2 clock store instruction, and load instruction will be explained.

3 and 4 show that an arithmetic instruction A and a store instruction B for setting immediate value data in a specific register of an information processing device in an embodiment of the present invention are consecutive, and a subsequent store instruction B
FIG. 4 is a timing diagram showing an operation when a register used for calculating a memory address matches a register to which immediate value data is set in a preceding operation instruction A (register interference).

Figure 3 shows that when store instruction B is l-clock store, the fourth
The figure shows a case where store instruction B is a 2-clock store.

Further, FIG. 12 shows an arithmetic instruction A for setting immediate value data in a specific register in an information processing device according to an embodiment of the present invention.
and load instruction B are consecutive, and the register used for calculating the memory address of the subsequent load instruction B matches the register in which immediate value data should be set in the preceding operation instruction A. FIG.

Using FIG. 1, FIG. 2, and FIG. 3, an arithmetic instruction A and a clock store instruction B for setting immediate value data of the information processing device in this embodiment to a specific register are consecutive,
The operation when register interference occurs between the register used for calculating the memory address of store instruction B and the register to which immediate value data is to be set by the preceding operation instruction A will be described. For simplicity of explanation, the register where interference occurs is called rl.
, the immediate data of operation instruction A is (immA), and the immediate data used for address calculation of l clock store instruction B is (i
mmB), and the data in the register to be terminated is (r2).

CI cycle: (1) Processing for operation instruction A Fetch arithmetic instruction A and send it to instruction bus 1)0.

C2 cycle: (1) Processing instruction bus 1 for operation instruction A Processing instruction A sent to instruction bus 1)
Decipher 01. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immA) to the immediate data bus 1) 1.

Further, the register unit 103 sends the 32-bit 0 register data specified by the control signal 1)B to the first internal data bus 1)2.

(2) Processing for store instruction B Fetch store instruction B and send it to instruction bus 1)0.

C3 cycle: (1) Processing for operation instruction A The integer operation unit 104 processes the instruction decoding unit 101 in the C2 cycle.
or immediate data path 1) Immediate data (imm
A) is input, and addition with 0 sent from the register unit 103 to the first internal data bus 1) 2 is executed. After the calculation is completed,
The calculation result is sent to the 32-bit third internal data bus 1)4. At the same time, the immediate data (immA) sent by the instruction decoder 101 to the immediate data bus Ill in the C2 cycle.
is latched by the 32-bit immediate data latch 206.

(2) Processing for store instruction B The instruction decoder 101 decodes the store instruction B sent to the instruction bus 1)0. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immB) to the immediate data bus 1) 1.

In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 detects register interference between the register rl used for calculating the memory address of the store instruction B and the register rl to which immediate value data is to be set in the preceding operation instruction A. , register interference detection signal 1) is sent to 9. At this time, the second register interference detection signal 21 in the register interference detection signal 1) 9
6 outputs a signal for the multiplexer 205 to select the output of the immediate data latch 206. Register section 10
3 sends the 32-bit register data (r 1) used for calculating the memory address specified by the control signal 1) 8 to the second internal data bus 1) 3, and sends the 32-bit register data (r 1) to be stored in the memory. data (r2) is sent to the first internal data bus 1)2. However, the data (r1) in the 32-bit register will be invalid data because the execution of the arithmetic instruction A has not been completed.

Next, the operation of the data address generation section 106 will be explained. The multiplexer 201 sends the immediate data (
immB). The multiplexer 205
Based on the information of the register interference detection signal 216, the data (immA) of the immediate data latch 206 is transferred to the data bus 217.
(corresponding to the correct (r1)). Adder 202 adds the data output to 32-bit data buses 210 and 217, respectively, and sends the result to addition result output bus 21.
). The multiplexer 203 receives the control signal 1)
Based on the information of the address hold signal 214 sent as 8, the data of the addition result output bus 21) is output to the data address bus 1)5. In this way, the address (immB) of the data to be stored on the data address bus 1)5
) + (r 1) is sent.

C4 cycle: (1) The processing register unit 103 for operation instruction A is processed by the integer operation unit 104 in the C3 cycle.
The data (imm
A) is stored in the register rl specified by control signal 1)8 in the C2 cycle.

(2) Processing data for store instruction B Address (im
mB) + (r 1) to access the data cache. Now assume that the data cache is hit. Further, the data transfer control unit 105
Data (r2) sent to internal data bus 1)2 is latched.

C5 cycle: (1) Processing for store instruction B The data transfer control unit 105 sends the data (r2) latched in the C4 cycle to the store data bus 1) 6 and stores it in the data cache.

As described above, in the information processing apparatus in this embodiment,
Arithmetic instructions A and 1 that set immediate data in a specific register
Clock store instruction B is continuous, and the register used for memory address calculation of store instruction B and the preceding operation instruction A
When register interference occurs with a register in which immediate value data should be set, an immediate data latch 206 is provided and the multiplexer 205 is controlled by the register interference detection signal 1)9. It becomes possible to speed up the minute processing.

Next, using FIG. 1, FIG. 2, and FIG. The operation when register interference occurs between the register used for calculating the memory address of instruction B and the register to which immediate value data is to be set by the preceding operation instruction A will be described. To simplify the explanation, the register data required for address calculation during 2-clock store is expressed as (r1) and (r
2) Let the data of the register to be terminated be (r 1), the register where interference occurs as r1, and the immediate data of operation instruction A be (immA).

C1 cycle: (1) Processing for operation instruction A Fetch arithmetic instruction A and send it to instruction bus 1)0.

C2 cycle: (1) Processing instruction bus 1 for operation instruction A
01 deciphers it. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immA) to the immediate data path 1) 1.

Further, the register unit 103 sends the 32-bit 0 register data designated by the control signal 1)8 to the first internal data bus 1)2.

(2) Processing for store instruction B Fetch store instruction B and send it to instruction bus 1)0.

C3 cycle: (1) The integer arithmetic unit 104 processes the arithmetic instruction A, and the integer arithmetic unit 104 processes the instruction decoder 101 in the C2 cycle.
The immediate data (imm
A) is input, and addition with 0 sent from the register unit 103 to the first internal data bus 1) 2 is executed. After the calculation is completed, the calculation result is sent to the 32-bit third internal data bus 1)4. At the same time, in the C2 cycle, the instruction decoder 101 sends immediate data (immA
) is latched by the 32-bit immediate data latch 206.

(2) Processing for store instruction B The instruction decoder 101 decodes the store instruction B sent to the instruction bus 1)0. The instruction decoder 101 sends out the control information as a control signal 1)8. In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 detects the register rl used for calculating the memory address of the store instruction B and the register r1 to which immediate value data is to be set by the preceding operation instruction A.
Detects register interference with the register and generates a register interference detection signal 1)
Send on 9th.

At this time, the first register interference detection signal 215 in the register interference detection signal 1) 9 is a signal for the multiplexer 201 to select the immediate data latch 206 and a register part 1
03 outputs a signal for outputting 32-bit register data (r3) to be stored in the memory to the first internal data bus 1)2. The register unit 103 receives the control signal 1
) 8, the 32-bit register data (r2) used for the memory address calculation is sent to the second internal data bus 1) 3, and the 32-bit register data (r3) to be stored in the memory is sent to the second internal data bus 1) 3. The data is sent to the first internal data bus 1)2.

Next, the operation of the data address generation section 106 will be explained. The multiplexer 201 transmits the data (immA) (correct (r1
) is output. The multiplexer 205
Based on the information of the register interference detection signal 216, the data (r2) of the second internal data bus 1) 3 is output to the data bus 217. The adder 202 adds the data output to the 32-bit data paths 210 and 217, respectively,
The result is output to the addition result output bus 21). The multiplexer 203 outputs the data of the addition result output bus 21) to the data address bus 1) 5 based on the information of the address hold signal 214 sent as the control signal 1) 8. In this way, the address (r 1') + (r 2) of the data to be stored is sent to the data address bus 1)5.

C4 cycle: (1) The processing register unit 103 for operation instruction A is processed by the integer operation unit 104 in the C3 cycle.
The data (imm
A) is stored in the register rl specified by control signal 1)8 in cycle 02.

(2) Processing data for store instruction B Address (r) sent to address bus 1)5
1) Access the data cache using + (r 2). Here, assume that the data cache is hit. Further, the data transfer control unit 105
The data (r3) sent to the internal data bus 1)2 is latched.

C5 cycle: (1) Processing for store instruction B The data transfer control unit 105 sends the data (r3) latched in the C4 cycle to the store data bus 1) 6 and stores it in the data cache.

As described above, the information processing apparatus according to the embodiment of the present invention has an operation instruction A that sets immediate value data in a specific register.
and two-clock store instruction B are consecutive, and if register interference occurs between the register used for memory address calculation of store instruction B and the register to which immediate value data should be set by the preceding operation instruction A, the immediate data latch 206 is activated. established,
By controlling the multiplexer 205 and the register section 103 using the register interference detection signal l9, it is possible to speed up the processing by two clocks compared to the conventional information processing apparatus.

Finally, using FIGS. 1 and 2 and FIG. 12, an operation instruction A and a load instruction B for setting immediate value data of the information processing device in this embodiment to a specific register are consecutive,
The operation when register interference occurs between the register used for calculating the memory address of load instruction B and the register to which immediate value data is to be set by the preceding operation instruction A will be described. For simplicity of explanation, let r1 be the register where interference occurs.
, the immediate data of operation instruction A (immA), the immediate data used for address calculation of load instruction B (immB),
Let r2 be the register into which data is to be loaded.

C1 cycle: (1) Processing for operation instruction A Fetch arithmetic instruction A and send it to instruction bus 1)0.

C2 cycle: (1) Processing for arithmetic instruction A The instruction decoder 101 decodes the arithmetic instruction A sent to the instruction bus 1)0. The instruction decoder 101 sends control information as a control signal 1)8, and sends immediate data (immA) to the immediate data bus Ill.

Further, the register unit 103 sends the 32-bit 0 register data specified by the control signal 1)8 to the first internal data bus 1)2.

(2) Processing for load instruction B Fetches load instruction B and sends it to instruction bus 1)0.

C3 cycle: (1) Processing for operation instruction A The integer operation unit 104 processes the instruction decoding unit 101 in the C2 cycle.
The immediate data (imm
A) is input, and addition with 0 sent from the register unit 103 to the first internal data bus 1) 2 is executed. After the calculation is completed,
The calculation result is sent to the 32-bit third internal data bus 1)4. At the same time, the immediate data (immA) sent by the instruction decoder 101 to the immediate data bus 1)1 in the C2 cycle.
is latched by the 32-bit immediate data latch 206.

(2) Processing for load instruction B The instruction decoder 101 decodes the load instruction B sent to the instruction bus 1)0. The instruction decoder 101 sends control information as a control signal 1) 8 and sends immediate data (immB) to the immediate data bus 1) 1.

In parallel with the processing of the instruction decoding unit 101, the register interference detection unit 102 detects register interference between the register rl used for calculating the memory address of the load instruction B and the register r1 to which immediate value data is to be set in the preceding operation instruction A. , register interference detection signal 1) is sent to 9. At this time, the second register interference detection signal 21 in the register interference detection signal 1) 9
6 outputs a signal for the multiplexer 205 to select the output of the immediate data latch 206. Register section 10
3 sends the 32-bit register data (r1) used for memory address calculation specified by the control signal 1)8 to the second internal data bus 1)3. However, the data (r1) in the 32-bit register will be invalid data because the execution of the arithmetic instruction A has not been completed.

Next, the operation of the data address generation section 106 will be explained. The multiplexer 201 sends the immediate data (
immB). The multiplexer 205
Based on the information of the register interference detection signal 216, the data (immA) of the immediate data latch 206 is sent to the data path 217.
(corresponding to the correct (r1)). Adder 202 adds the data output to 32-bit data paths 210 and 217, respectively, and sends the result to addition result output bus 21.
). The multiplexer 203 outputs the restriction signal 1)
Based on the information of the address hold signal 214 sent as 8, the data of the addition result output bus 21) is output to the data address bus 1)5. In this way, the address (immB) of the data to be loaded onto the data address bus 1)
) + (r 1) is sent.

C4 cycle: (1) The processing register unit 103 for operation instruction A is processed by the integer operation unit 104 in the C3 cycle.
The data (imm
A) is stored in the register rl specified by control signal 1)8 in cycle 02.

(2) Processing data for load instruction B Address (im) sent to address bus 1)5
mB) + (r 1) to access the data cache. Now assume that the data cache is hit. The data cache is stored at the hit address (im
B) + Load data of (r 1) Data bus 1) 7
Output to.

C4 cycle: The data transfer control unit 105 sends the data sent by the data cache to the load data bus 1) 7 to the third internal data bus 1) 4 in the C3 cycle. The register section 103 stores the data on the third internal data bus 1)4 in the register r2 at the address sent as the control signal 1)8.

Also, regarding the load instruction where the address of the data to be loaded is indicated by the sum of the data of two registers (r 1) + (r 2), it is the same as the case of (rl) + (immB) described above, so the details Further explanation will be omitted. In this case, the register unit 103 transfers data in two registers used for address calculation to the first internal data path and the second internal data path, respectively.
Output to internal data path, data address generation unit 106
This differs from the above description in that it outputs the data of the first internal data path to the data path 210.

As described above, in the information processing apparatus in this embodiment,
Operation instruction A that sets immediate value data to a specific register and load instruction B are consecutive, and there is register interference between the register used for memory address calculation of load instruction B and the register to which immediate value data should be set in the preceding operation instruction A. When this occurs, by providing an immediate data latch 206 and controlling the multiplexer 205 using the register interference detection signal 1)9, it is possible to speed up processing by one clock compared to conventional information processing devices.

Here, we have explained the 1-clock store instruction, 2-clock store instruction, and load instruction as examples of instructions that require memory address calculation, but the same applies to other instructions such as branch instructions that require memory address calculation. By controlling the information processing apparatus, it is possible to speed up processing by l clocks compared to conventional information processing apparatuses.

〔Effect of the invention〕

According to the information processing device of the present invention, an instruction that requires memory address calculation (a load instruction, a clock store instruction, or a branch instruction) should set the register used for memory address calculation and the immediate value data of the preceding operation instruction. This can speed up l-clock processing when register interference with the register occurs, and furthermore, register interference occurs between the register used for memory address calculation with the 2-clock store instruction and the register to which the immediate data of the preceding operation instruction should be set. In some cases, it is possible to speed up two-clock processing, and its practical value is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of a data address generation unit in FIG. 1, and FIG. 3 is a block diagram of an information processing device according to an embodiment of this invention. Operation when an arithmetic instruction that sets a specific register and a clock store instruction occur in succession, and register interference occurs between the register used to calculate the memory address of the store instruction and the register to which immediate data should be set by the preceding arithmetic instruction. FIG. 4 is a timing diagram showing an operation instruction for setting immediate value data in a specific register in an information processing device according to an embodiment of the present invention, and a two-clock store instruction, and a register used for calculating the memory address of the store instruction and a preceding one. Fig. 5 is a block diagram of a conventional information processing device, and Fig. 6 shows data address generation in Fig. 5. FIG. 7 is a timing diagram showing the operation of an arithmetic instruction in a conventional information processing device; FIG. 8 is a timing diagram showing the operation of an l clock store instruction in a conventional information processing device;
FIG. 9 is a timing diagram showing the operation of a two-clock store instruction in a conventional information processing device, and FIG. 10 is a timing diagram showing the operation of a two-clock store instruction in a conventional information processing device. , a timing diagram showing the operation when register interference occurs between the register used to calculate the memory address of the store instruction and the register to which immediate value data should be set in the preceding operation instruction. Figure 1) shows the immediate value of the conventional information processing device When an arithmetic instruction that sets data in a specific register and a two-clock store instruction are consecutive, and register interference occurs between the register used for calculating the memory address of the store instruction and the register that should set immediate data in the preceding arithmetic instruction. Timing diagram showing the operation of
Figure 2 shows that an arithmetic instruction for setting immediate data in a specific register in an information processing device according to an embodiment of the present invention and a load instruction are consecutive, and the immediate data is stored in the register used for calculating the memory address of the load instruction and the preceding arithmetic instruction. FIG. 7 is a timing diagram showing an operation when register interference with a register to be set occurs. 101... Instruction decoding unit, 102... Register interference detection unit, 103... Register unit, 106... Data address generation unit, 1) 8... Control signal, 1) 9... Register interference Detection signal, 206... Immediate data latch.

Claims (4)

[Claims] (1) An immediate data latch that holds the immediate data specified in an instruction, two multiplexers that receive the output of the immediate data latch, an adder that adds the outputs of the two multiplexers, and a link between consecutive instructions. and a register interference detection unit that detects register interference, and when an instruction that stores immediate value data in a specific register and an instruction that requires memory address calculation are consecutive, the register interference detection unit detects the memory When a match is detected between the register used for address calculation and the register storing immediate data in the preceding instruction, the adder uses the immediate data of the preceding instruction held by the immediate data latch, which is the output from one of the multiplexers. An information processing device characterized in that the information processing device calculates a memory address. (2) An information processing device characterized in that the instruction requiring memory address calculation according to claim (1) is a load instruction, a store instruction, or a branch instruction. (3) An immediate data latch that holds the immediate data specified in the instruction, two multiplexers that receive the output of the immediate data latch, an adder that adds the outputs of the two multiplexers, and a link between consecutive instructions. A register interference detection unit that detects register interference, and a register interference detection unit that stores immediate data in a specific register and stores the data in the specific register in the memory at an address specified by the sum of the immediate data and data in another register. When instructions to store are consecutive, when the register interference detection unit detects a match between the register used for memory address calculation in the subsequent instruction and the register storing immediate data in the preceding instruction, the adder selects one of the multiplexers. An information processing device that calculates an address by adding the immediate data of the preceding instruction held by the immediate data latch, which is the output from the multiplexer, and the immediate data of the subsequent instruction, which is the output from the other multiplexer. . (4) An immediate data latch that holds the immediate data specified in an instruction, two multiplexers that receive the output of the immediate data latch, an adder that adds the outputs of the two multiplexers, and a link between consecutive instructions. It is equipped with a register interference detection section that detects register interference, and a register section that consists of multiple registers that can output data from two registers simultaneously. When instructions to store in the memory at an address specified by the sum of the data of two registers are consecutive, the register interference detection unit detects the immediate data in one register used for memory address calculation in the subsequent instruction and in the preceding instruction. When a match is detected with the register storing the data, the register section outputs the data of the other register that does not match and the data of the register to be stored in the memory, and the adder outputs the data of the immediate value output from one multiplexer. An information processing device that calculates a memory address by adding immediate value data of a preceding instruction held by a latch and data of the other register that does not match in a subsequent instruction output from the other multiplexer.