JPH03218535A - Error detection system - Google Patents

Abstract

PURPOSE:To detect not only an odd bit error but also an even bit error with the small quantity of hardware by checking parity in a vertical direction for respective bits constituting holding data in registers which are cascade-connected. CONSTITUTION:A means transmitting parity codes based on the values of a first signal being the value of a bit inputted to a first register 11, a second signal being the value of the N-th register 1N of a bit whose weight is the same as that of the bit of the first signal, and a third signal is provided. Then, means 41 and 42 holding the parity codes transmitted from a parity code transmission means and parity check means 51 and 52 checking the parity of the same weight bit based on the output are provided, and the outputs of the holding means 41 and 42 are set to be the third signal. Namely, parity check in a horizontal direction and parity check in the vertical direction, which generates the parity code after data is transmitted to the other register and detects the error by using the parity code are used together. Thus, not only the odd bit error but also the even bit error can be detected.

Description

TECHNICAL FIELD The present invention relates to an error detection system, and more particularly, to an error detection system for detecting errors in each held data of a plurality of registers connected in cascade so as to sequentially shift each bit of held data to a corresponding bit in the next stage. The present invention relates to an error detection system for detecting errors.

BACKGROUND ART In general, an information processing apparatus employing a pipeline processing method is provided with a plurality of registers connected in cascade so as to sequentially shift each bit of held data to a corresponding bit in the next stage.

Conventionally, in such information processing devices, errors are detected by performing a parity check on data held in each register. In other words, the error detection method uses the parity of each data held in multiple registers to check the validity of the data, and if it is determined to be invalid, it notifies the higher-level device and the outside. It had been adopted.

An information processing apparatus employing the conventional error detection method will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the main parts of a conventional information processing device.

In the figure, 11, 12, . . . IN are registers, which are cascade-connected so that each bit of held data is sequentially shifted to a corresponding bit in the next stage. Bits A, B, C, - . . . constitute each data. ．． A parity bit P having a value corresponding to the number of "1"s is added. That is, a parity bit P of a value such that the number of "1"s including the parity bit P is always an even number (or an odd number) is added to each bit of data and input. Therefore, each data and parity bit is processed by a parity check circuit (hereinafter abbreviated as PC circuit) 21, 22, . . . 2N.
By inputting the data into the , you can check the validity of the data held in each register.

In other words, when data is propagated from one register to another, so-called data corruption occurs, and "1" becomes "0".
Or, when "0" becomes "1", the number of 1 changes, and this is detected in each PC circuit. In addition,
An example of a PC circuit is the well-known IEX-NOR (exclusive NOR) circuit.

However, the conventional error detection method using a parity check has the drawback that although odd-numbered bit errors can be detected, even-numbered bit errors such as 2-bit errors cannot be detected. As an improvement measure, it is possible to adopt a well-known 2-bit error correction code, but this is not a good idea because it involves an increase in a large amount of hardware.

Purpose of the Invention The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to eliminate not only odd bit errors but also
An object of the present invention is to provide an error detection system capable of detecting even bit errors.

Structure of the Invention The error detection system according to the present invention comprises first to Nth registers (N is an integer of 2 or more) connected in cascade so as to sequentially shift each bit of held data to the corresponding bit 1 of the next stage. an error detection system for detecting errors in each held data, the first signal being the value of a bit input to the first register and the value of the Nth register having the same weight as the bit; parity code sending means for sending out a parity code for parity check based on the value of the second signal and further the third signal; holding means for holding the parity code sent from the parity code sending means; and parity check means for performing a parity check of the bits having the same weight based on the output of the holding means, and the output of the holding means is used as the third signal.

Another error detection system according to the present invention provides each hold in first to Nth (N is an integer of 2 or more) registers connected in cascade so as to sequentially shift each bit of held data to a corresponding bit in the next stage. An error detection system for detecting errors in data, the first signal being the value of a bit input to the first register, and the first signal being the value of the Nth register of a bit having the same weight as the bit. parity code sending means for sending out a parity code for parity check based on the value of the second signal and further the third signal; holding means for holding the parity code sent from the parity code sending means; and the holding means. a first parity check means for performing a parity check on the bits having the same weight based on the output of the means; a second parity check means for performing a parity check, the output of the holding means is used as the third signal, and an error is detected based on the results of the parity check of the first and second parity check means. It is characterized by detecting.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the main parts of an information processing apparatus employing an error detection system according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

In the embodiment, an error detection circuit using the conventional error detection method shown in FIG. 2 and an error detection circuit using a different method are provided. In other words, 21, 22, ..., 2N in the figure are error detection circuits using the conventional error detection method, and as described above, when the parity bit P is included in each bit constituting the retained data, "1" is detected. The validity of the retained data is determined based on whether the number is even or odd.

However, as described above, this method cannot detect even-numbered bit errors. Therefore, in this embodiment, an error detection circuit using a different method is provided.

In the figure, 31, 32, . . . are parity prediction (hereinafter abbreviated as PP) circuits, 41, 42, . . . , 4N are holding circuits, and 5
1, 52, . . . are parity check circuits.

Parity check circuits 51, 52. ... is input with all the bits of the same weight among the data held in each register and the output bits from the corresponding holding circuit,
Similar to the above-mentioned method, the validity of the held data is determined depending on whether the number of "1"s is an even number or an odd number.

In addition, each holding circuit 41, 42, . . . has a corresponding PP
Although the output of the circuit is held, each holding circuit 41, 42, .
The outputs of . In other words, in the PP circuit, the output of the holding circuit, that is, the previous output of its own circuit, the input to register 11, and the output of register IN, total 3.
An error detection code is generated based on the two signals.

In this case, register IN is the final stage of the registers to be checked for errors. Therefore, if it is desired to check up to an intermediate stage, the register at that stage may be set as register IN.

In addition, in the tree example, the PP circuits 31, 32,... are the well-known I
EX-OR circuit, PC circuit 51, 52, -1. It is assumed that the well-known EX-NOR circuit, holding circuits 41, 42, . . . are well-known D-type flip-flops.

The operation of the error detection system having such a configuration will be explained using FIG. 3. FIG. 3 is a truth table showing the operation of each part in FIG. 1. In the figure, the held value of the holding circuit 41, the held value of each register, the output of the PC circuit 51, the input to the register 11, and the output of the PP circuit 31 are shown in the case of N-3, that is, when there are three stages of registers. ing.

In the table, ■ is the value held in the register 11, ■ is the value held in the register 12, and ■ is the value held in the register IN. Further, in the PC circuit, when the number of "1's" is an odd number, it is determined to be normal and the output is "0", and when the number is even, it is determined to be abnormal and the output is "1".

First, at the time of resetting the device, that is, at the time of initial setting, the value held in the holding circuit 41 is "1", the value held in each register, P
All outputs of the C circuit 51 are set to “0” (item A)
.

Here, when the input to the register 11 becomes "1", the value held in the holding circuit 41 becomes "1", and the value held in the register 1N becomes "1".
Therefore, the output of the PP circuit 31, which is their exclusive OR, becomes "0" (item B).

When the first clock rises in this state, the input values are latched into each register and holding circuit. Then,
“1”, “0”, and “0” are held in the registers 11 to IN in order, and “0” is held in the holding circuit 41, so “
The number of “1” is odd, and the output of the PC circuit 51 is “0”.
and is normal (item C).

Next, when the input to the register 11 becomes "1", the value held in the holding circuit 41 becomes "O" and the value held in the register IN becomes "0".
”, therefore, the PP circuit 3 which is their exclusive OR
The output of 1 becomes "1" (item D).

When the second clock rises in this state, the input values are latched into each register and holding circuit. Then,
“1”, “1” and “0” are held in the registers 11 to IN in order, and “1” is held in the holding circuit 41, so “
The number of 1' is odd, and the output of the PC circuit 51 is "0".
and is normal (item E).

Next, when the input to the register 11 becomes "1", the value held in the holding circuit 41 becomes "1" and the value held in the register IN becomes "0".
”, so the PP circuit 3 which is their exclusive OR
The output of 1 becomes "0" (item F).

When the third clock rises in this state, the input values are latched into each register and holding circuit. Then,
The registers 11 to IN hold "1°""1" in order, and the holding circuit 41 holds "0", so the number of "1°" is an odd number, and the output of the PC circuit 51 is "0'', which is normal (item G).

Next, when the input to the register 11 becomes "1", the value held in the holding circuit 41 becomes "0" and the value held in the register IN becomes "1".
”, therefore, the PP circuit 3 which is their exclusive OR
The output of 1 becomes "0" (item H).

When the fourth clock rises in this state, the input values are latched into each register and holding circuit. Then,
“1” “1” 1” are held in the registers 11 to IN in order, and “0” is held in the holding circuit 41, so “1”
is an odd number, and the output of the PC circuit 51 is "0", which is normal (item!).

Next, when the input to the register 11 becomes "0", the value held in the holding circuit 41 becomes "0" and the value held in the register IN becomes "1".
“, so the PP circuit 3 which is their exclusive OR
The output of 1 becomes "1" (item J).

When the fifth clock rises in this state, the input values are latched into each register and holding circuit. Then,
Registers 11 to IN contain "0", "1", . “1” is held and “1” is held in the holding circuit 41, so “
The number of “1” is odd, and the output of the PC circuit 51 is “0”.
and is normal (Item K).

Next, when the human power to the register 11 becomes "0", the value held in the holding circuit 41 becomes "1", and the value held in the register IN becomes "1".
Therefore, the PP circuit 3 which is their exclusive OR
The output of 1 becomes "0" (item).

When the sixth clock rises in this state, the input values are latched into each register and holding circuit. Then,
The registers 11 to IN hold “0°”0” and “1” in order, and the holding circuit 41 holds “0”, so “1”
is an odd number, and the output of the PC circuit 51 is "0", which is normal (item M).

As described above, data is transferred from register 11 to register IN.
If the data is transmitted normally, that is, if there is no error in the data held in each register, the output of the PC circuit will always be “0”.
゜, indicating that it is normal. On the other hand, if so-called data corruption occurs when data is transmitted to another register, the output of the PC circuit becomes "1", indicating an abnormality. In addition, in this case, a validity check is performed for each bit that makes up the data held in each register, so even if there is an error in an even number of bits in one piece of held data, the error will be checked. It can be detected.

In other words, in this embodiment, a horizontal parity check is performed to detect errors in data held in one register, and a parity code is generated after the data is transmitted to other registers, and this is used to detect errors. Since it is also used with a vertical parity check that detects , it is possible to detect not only odd bit errors but also even bit errors.

In the configuration shown in FIG. 1, if an odd bit error occurs, one of the PC circuits 51, 52, .
Since the two outputs and the output of one of the PC circuits 21, 22, . , it is also possible to specify the bit position. However, in the case of an even bit error, the PC circuits 21, 22, ... 2N cannot detect the error, so the PC circuits 51, 52, ...
The occurrence of an error can be detected by only one of them.

Therefore, if you simply want to check whether an error has occurred, use the PC circuit 51 that detects errors in the vertical direction for the same weight.
, 52, . . . , and the PC circuits 21, 22, . . . 2N for horizontal errors are not required. In other words, by providing the PC circuits 51, 52, . . . for errors in the vertical direction, it is possible to detect odd number bit errors and even number bit errors, which were conventionally undetectable. In addition,
In this embodiment, the case where there are three stages (N-3) of registers has been described, but it is obvious that the present invention can also be applied to a case where the number of stages is larger. However, at least two stages are required. This is because the value of the first stage and the value of the last stage are required.

In other words, the present invention uses data to be held in each register at the next rising edge of the clock based on the value input to the first stage, the current value of the final stage, and the current parity code value. Since parity codes for the same weights are generated in advance in anticipation of the error, if an error occurs during data transmission, it can be reliably detected.

Effects of the Invention As explained above, the present invention performs a vertical parity check on each bit of data held in cascade-connected registers for each bit constituting the data.
In addition to eliminating odd bit errors with a small amount of hardware,
This has the advantage of being able to detect even-numbered bit errors. Furthermore, if a conventional horizontal check is performed in addition to the vertical check, in the case of an odd bit I error, the bit position where the error has occurred can be identified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the main parts of an information processing device that employs an error detection system according to an embodiment of the present invention;
FIG. 2 is a block diagram showing the configuration of a conventional information processing device.
FIG. 3 is a truth table showing the operation of each part in FIG. 1. Explanation of symbols of main parts 2 1 . . . 2N, 5 1 , 5 2 ・Parity check circuit 3 1 , 3 2 . . . Parity reduction circuit 4 1 , 4 2 . . Holding circuit

Claims (2)

[Claims] (1) An error that detects an error in each held data of the first to Nth (N is an integer of 2 or more) registers connected in cascade so that each bit of held data is sequentially shifted to the corresponding bit of the next stage. a detection system comprising: a first signal being the value of a bit input to the first register; a second signal being the value of the Nth register of bits having the same weight as the bit; parity code sending means for sending out a parity code for parity check based on the value of the signal No. 3; holding means for holding the parity code sent from the parity code sending means; and parity check means for performing a parity check on bits having the same weight, and an output of the holding means is used as the third signal. (2) An error that detects an error in each held data of the first to Nth (N is an integer of 2 or more) registers connected in cascade so that each bit of held data is sequentially shifted to the corresponding bit of the next stage. a detection system comprising: a first signal being the value of a bit input to the first register; a second signal being the value of the Nth register of bits having the same weight as the bit; parity code sending means for sending out a parity code for parity check based on the value of the signal No. 3; holding means for holding the parity code sent from the parity code sending means; a first parity check means that performs a parity check on bits having the same weight; and a second parity check means that is provided corresponding to each of the first to Nth registers and performs a parity check on each held data in the corresponding register. parity check means, the output of the holding means is used as the third signal, and errors are detected based on the results of the parity check of the first and second parity check means. An error detection system featuring: