JPH03218636A - Manufacture of field effect semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a method for manufacturing a field-effect semiconductor device, and is particularly suitable for improving the performance and reliability of a semiconductor device constituted by field-effect transistor elements for integrated circuits. Conventional technology In integrated circuits constructed using field-effect transistors, the miniaturization of component elements has progressed significantly, and the minimum processing size has reached the so-called sub-micron region of 1 micron or less.
One of the factors hindering this miniaturization is reliability problems such as hot carrier effects, and many improvements have been made to device structures and manufacturing methods. GOLD (Ga
te-Drain Overlapped LDD)
[Izawa & 1987 International Electron Device Meeting Technical Digest of Papers pp. 38-41 (IZAWA
etal, International Elect
ron Device Meeting Techni
cal Digest of Papers pp, 3
8-41.1987), the structure of this GOLD and its manufacturing method will be explained based on Figure 3. Figures 3(a) to (d) show the manufacturing method of the field effect transistor part of GOLD. FIG. f, a gate oxide film 10l, a thin lower polysilicon film l02, and a thick upper polysilicon film 1 on a P-type silicon single crystal substrate 100.
04. A resist pattern 108 is formed by a photolithography process on a portion of the multilayer film in which silicon oxide films 106 are sequentially formed, where a gate is to be formed (FIG. 3a). Here, the interface between the thin polysilicon 102 and the thick polysilicon 104 has a
A natural oxide film with a thickness of 1.0 nanometers is formed. An oxide film pattern 106A is formed using the resist pattern 108 as a mask.
Using 06A as a mask, the thick upper layer of polysilicon 104 is etched using dry etching that is highly selective to the oxide film.A The natural oxide film on the surface of the thin lower layer of polysilicon 102 acts as an etching stop and is thick. Even if the upper polysilicon layer 104 is isotropically etched and a polysilicon pattern 104A is formed, proceed to the next step.Oxide film pattern 106A, polysilicon pattern 10
Using 4A as a mask, phosphorus ion implantation was performed to form P-type substrate 1.
N-type semiconductor region 1 which becomes the source and drain in 00
05A. 105B (Fig. 3b). Next Oxide film pattern 106A, polysilicon pattern 104A
The oxide films 109A and 109B are left on the side surfaces of the oxide films 109A and 109B. Using 109B as a mask, the thin silicon film is etched to form a polysilicon pattern 102A that will essentially become a gate electrode (
Figure 3C). To the end Remaining oxide film 109A. 1
Using 09B as a mask, N-type semiconductor regions 107A and 107B, which will become part of the source and part of the drain, are formed in the P-type substrate 100 by ion implantation of highly concentrated arsenic (FIG. 3d).

In the GOLD manufactured through such a process, the N-type semiconductor regions 105A and 105B at the drain end sufficiently overlap the polysilicon pattern 102A for the gate electrode (0.2 micron or more). This overlap has the following characteristics (1).
) Field-effect transistor (single train) in which the electric field applied near the drain is formed by the usual method
Since it is smaller than , the generation of hot carriers is suppressed and reliability is high.(2) Resistance of overlap part <. LDD (Lig.
htly Doped Drain) structure field effect transistor. The conventional method shown in Figure 3 has the following problems (1) The extremely thin natural oxide film cannot be used as an etching stopper. Although it is necessary to use a special etchant that has a high selectivity (several hundred times) for oxide films, (2) currently, etchants that have a high selectivity for oxide films (several hundred times) are used. (3) Due to the thinning of the upper polysilicon pattern, the oxide film pattern 10
Since 6A becomes an overhang, the oxide films 109A and 10 left on the side surfaces of the polysilicon pattern 104A are
9B becomes poor, and since this oxide film is used as an etching mask for the lower polysilicon 102A that will become the gate electrode, it tends to cause variations in gate width (~ (4) The oxide film pattern 106A is located on the gate electrode. As a result, unevenness from the silicon substrate 100 increases, causing problems with the flatness of the second layer wiring. (5) Punch-through stop, LDD, etc. ion implantation causes channeling and creates a deep profile, making it suitable for miniaturization. The present invention addresses the problems encountered in forming field effect devices with gate and drain overlapping structures and provides a new method for manufacturing field effect semiconductor devices that solves these problems. Means for Solving the Problems In order to solve the above-mentioned problems, a step of forming a first insulating film for a gate on a semiconductor layer of a first conductivity type; A step of forming a first conductive film to serve as a gate electrode thereon, a step of forming a buffer film on the first conductive film, and a step of forming a second conductive film on the buffer film. and a step of etching the second conductive film into a wiring shape, using the buffer film as an etching stopper;
a step of etching the buffer film using the conductive film of the wiring shape as a mask; a step of making the first conductive film amorphous by ion implantation using the second conductive film of the wiring shape as a mask; By ion implantation using the conductive film No. 2 as a mask, impurities of the second conductivity type are transmitted through the amorphous first conductive film and implanted into the semiconductor layer of the first conductivity type. forming a first impurity region of a second conductivity type that will become a drain; leaving a third conductive film on the side surface of the second conductive film in the wiring shape and the side surface of the etched buffer film; a step of connecting the upper surface of the first conductive film and the side surface of the second conductive film via a third conductive film, and connecting the left third conductive film and the second conductive film having the wiring shape. Used as an etching mask. etching the first conductive film into a wiring shape; and etching the third conductive film left behind.
A second conductive type impurity is implanted into the first conductive type semiconductor layer by ion implantation using the conductive film and the second conductive film having the wiring shape as a mask to form a part of the source and a part of the drain. a step of forming a second impurity region of a second conductivity type, and forming a third conductive region in which the upper surface of the first conductive film having a wiring shape and the side surface of the second conductive film having a wiring shape remain. The method of manufacturing a field-effect semiconductor device characterized by electrical connection through a film has the following effects: Since the thickness can be made sufficiently large, the upper layer 'M2 conductive film can be easily etched.(2) The electrical connection between the upper layer second conductive film and the lower layer first conductive film Although the connection can be easily achieved through the third conductive film, (3) the thickness of the buffer film can be made sufficiently large, and the upper layer can be removed by anisotropic dry etching with poor etching selectivity. (4) Impurity ions can be etched onto the semiconductor substrate through the first conductive film in the lower layer. Before being introduced into the LDD, ions are implanted into the first conductive film to make it amorphous (no regular atomic arrangement), so impurity ions from the punch-through stop and LDD do not cause channeling. Embodiment 1 (Example 1) FIGS. 1(a) to 1(d) show a series of steps showing a method for manufacturing a field-effect semiconductor device according to a first embodiment of the present invention. Figure 1(a) shows a gate oxide film 101 with a thickness of lθ~20 nm on a ciP type silicon single crystal substrate 100, a polysilicon film 102 with a thickness of 50~100 nm, which will become the first conductive film, and a buffer. 10-20 nm silicon oxide film 103 that becomes a film
, a polysilicon film 104 with a thickness of 300 to 350 nm, which will become a second conductive film, is successively formed.

As shown in FIG. Use a fluorine-based etching gas such as SF● Silicon oxide M1
03 acts as an etching stopper. Next K,
The silicon oxide film 103 is selectively etched by wet etching to expose the first conductive film 102.
Next, using the gate electrode 104A as a mask, low acceleration energy is applied, for example, 30 to 40[e■], and the dose is 3E15 to I.
The polysilicon film 102 was made amorphous by implanting silicon ions under the ion implantation conditions of E16c m-'', but as shown in FIG. The third conductive film, ie, polysilicon, is transmitted through the film 102 to form L-N type impurity regions 105A and 105B implanted into the P-type semiconductor substrate 100. A film is deposited to a thickness of 200 to 300 nm, and spacers 106A and 106B made of polysilicon film are left on the side walls of the gate electrode 104A by anisotropic dry etching, and at the same time, the polysilicon film 102 is etched to form a layer 102A that will become the lower layer gate electrode. Sumo Next
By implanting impurity ions using the gate electrode 104A made of a polysilicon film and the sidewall spacers 106A, 106B as masks, arsenic ions are implanted into the semiconductor substrate to form N-type impurity regions 107A. However, in the LDD structure obtained by this method, the gate and drain overlap, and a device with high reliability and high driving force can be obtained. (1) Before performing the ion implantation to form the N-type impurity regions 105A and 105B, the silicon film 102 is made amorphous so that the implanted ions do not cause channeling. 0 on device
．． A shallow and uniform impurity distribution of 2 to 0.3 microns can be obtained, making it easy to reduce the channel length of the transistor.a (2) When using a tungsten silicide film as the gate electrode 104A, the stress of the gate electrode 104A is reduced by the buffer film. 103, the gate insulating film 1
The stress applied to 01 and the silicon substrate 100 is reduced. Further, the buffer film 103 prevents metal atoms such as tungsten from diffusing and causing reactive breakdown of the gate insulating film.

(3) Since the buffer film 103 is used as an etching stopper, the formation of the upper layer gate electrode is easy;
The width of the lower layer gate electrode, which affects transistor characteristics, is determined by the thickness of the third conductive film, so there is little variation (
~ (4) Since the combination of the first conductive film 102 and the second conductive film 104 can be arbitrarily selected, in particular, amorphous silicon can be used as the upper layer second conductive film 104 instead of polysilicon which becomes the gate electrode 104A. Non-single-crystalline semiconductor light such as silicon or metal oxide such as tungsten or molybdenum
High melting point metal compounds such as tungsten silicide K and molybdenum silicide can be used, and the gate wiring resistance can be sufficiently lowered (5) Buffer jI! The thickness of the upper layer 103 can be made sufficiently large.When using a metal compound such as tungsten, molybdenum, etc., tungsten silicide, molybdenum silicide, etc. as the upper layer second conductive film 104. (6) It is possible to reduce the resistance of the C gate electrode by using a conductive film as a buffer film. Embodiment 2) FIGS. 2(a) to 2(d) are a series of process cross-sectional views showing a method for manufacturing a field-effect semiconductor device according to a second embodiment of the present invention. In Figure 2(b), a resist pattern is formed in the area where the gate electrode is to be formed using a normal photolithography process, and the polysilicon M104 is etched to form the upper layer gate electrode 104A. The silicon oxide film 103 acts as an etching stopper using a fluorine-based material such as SFa.Next, wet etching is performed to form the silicon oxide film 1.
03 is selectively etched to expose the first conductive film 102. :, large inclination angle using the gate electrode 104A as a mask (
Although the polysilicon film 102 is made amorphous by implanting silicon ions by ion implantation (20 to 30 degrees), as shown in FIG.
), boron ions are transmitted through the amorphous silicon film 102 by similar large-angle ion implantation using the gate electrode 104A as a mask, and are then implanted into the P-type semiconductor substrate 10.
Next, LP-type impurity regions 108A and 108B are implanted into the P-type semiconductor substrate 100 by ion implantation in a substantially vertical direction using the gate electrode 104A as a mask. After implanting and forming N-type impurity regions 105A and 105B, the second
In Figure (C) 41, a polysilicon film, which is the third conductive film, is uniformly deposited to a thickness of 200 to 300 nm, and spacers 106A and 106B made of the polysilicon film are left on the side walls of the gate electrode 104A by anisotropic dry etching. At the same time, the polysilicon film 102 is etched to form the lower layer gate electrode 102A.Next: Gate electrode 104A and sidewall spacer made of polysilicon film
Using impurity ions 106A and 106B as masks, arsenic ions are implanted into the semiconductor substrate in a substantially vertical direction to form N-type impurity regions 108A and 108B having a higher concentration than N-type impurity regions 105A and 105B. In the field-effect semiconductor device obtained by the present invention, the P-type impurity regions 108A and 108B, which are higher in concentration than the substrate introduced for punch-through stop, are N.
In order to suppress the elongation of the depletion layer without increasing the substrate bias effect, the breakdown voltage can be increased and the short channel effect can be suppressed. When the silicon film 102 is made amorphous by ion implantation, the implanted ions cause channeling, and a shallow and uniform impurity distribution can be obtained, making it possible to create minute devices with short channel lengths. According to 9, a field-effect transistor suitable for miniaturization can be obtained because the second conductive film can be easily etched, there is little variation in gate width, and the impurity distribution in the semiconductor substrate can be controlled to be shallow and uniform. Since the generation of hot carriers is suppressed, there is no need to lower the power supply voltage even in integrated circuits with a minimum line width of 0.5 microns or less, and a high drive current can be obtained, which greatly contributes to miniaturization.

[Brief explanation of drawings]

FIG. 1 shows a series of process cross-sections showing a method for manufacturing a field-effect semiconductor device according to a first embodiment of the present invention. FIG. 2 shows a manufacturing method for a field-effect semiconductor device according to a second embodiment of the present invention. A series of process cross-sectional views showing the method FIG. 3 is a process cross-sectional view showing the structure and manufacturing method of a conventional field effect semiconductor device. 100...P-type silicon single crystal semiconductor substrate 101...
・Gate oxidation wind 103...Buffer 1L102,
102A, 104.104A, 104B, 106.
106A, 106B...Borisiri:'n a
105A, 105B. l07A. 107B-N type impurity region ID8A, 108B-P type impurity region

Claims (2)

[Claims] (1) A step of forming a first insulating film for a gate on a semiconductor layer of a first conductivity type, and a step of forming a first conductive film to become a gate electrode on the first insulating film. , forming a buffer film on the first conductive film, forming a second conductive film on the buffer film, and using the buffer film as an etching stopper to form the second conductive film. etching the film into a wiring shape; etching the buffer film using the wiring-shaped second conductive film as a mask; and etching the buffer film by ion implantation using the wiring-shaped second conductive film as a mask. 1
By a process of making the conductive film amorphous and ion implantation using the second conductive film having the wiring shape as a mask,
A second conductivity type impurity is transmitted through the amorphous first conductive film and injected into the first conductivity type semiconductor layer to form a second conductivity type first impurity that becomes a source and a drain. a third conductive film is left on the side surface of the second conductive film having the wiring shape and the side surface of the etched buffer film; a step of connecting the side surface of the film via a third conductive film, and using the left third conductive film and the wiring-shaped second conductive film as an etching mask,
The impurities of the second conductivity type are etched into the first conductive film by etching the conductive film into a wiring shape, and by ion implantation using the remaining third conductive film and the second conductive film having the wiring shape as a mask. forming a second impurity region of a second conductivity type that becomes a part of the source and a part of the drain by implanting the second impurity region into the semiconductor layer of the wiring shape; 1. A method for manufacturing a field effect semiconductor device, comprising electrically connecting a side surface of a second conductive film in the shape of a wiring through a third conductive film left behind. (2) forming a first insulating film for a gate on a semiconductor layer of a first conductivity type; and forming a first conductive film to become a gate electrode on the first insulating film. , forming a buffer film on the first conductive film, forming a second conductive film on the buffer film, and using the buffer film as an etching stopper to form the second conductive film. etching the film into a wiring shape; etching the buffer film using the wiring-shaped second conductive film as a mask; and oblique ion implantation using the wiring-shaped second conductive film as a mask. A first conductive type impurity is made into an amorphous first conductive film by ion implantation in an oblique direction using the second conductive film having the wiring shape as a mask. forming a first impurity region of the first conductivity type having a higher concentration than the semiconductor layer by transmitting the impurity into the semiconductor layer of the first conductivity type through the film; By substantially vertical ion implantation using the film as a mask, impurities of the second conductivity type are transmitted through the amorphous first conductive film and implanted into the semiconductor layer of the first conductivity type. and a step of forming a second impurity region of a second conductivity type to serve as a drain, and leaving a third conductive film on a side surface of the second conductive film in the wiring shape and a side surface of the etched buffer film,
The upper surface of the first conductive film and the side surface of the second conductive film are
a step of connecting via the conductive film, and a step of connecting the remaining third
etching the first conductive film into a wiring shape using the conductive film and the second conductive film having the wiring shape as an etching mask; etching the remaining third conductive film and the second conductive film having the wiring shape; The impurity of the second conductivity type is implanted into the first conductive film by substantially vertical ion implantation using the conductive film as a mask.
forming a third impurity region of the second conductivity type which becomes part of the source and part of the drain by implanting the first impurity region of the first conductivity type into the semiconductor layer of the conductivity type; Used as a punch-through stopper, the upper surface of the first conductive film in the shape of a wiring and the side surface of the second conductive film in the shape of a wire are electrically connected via a left third conductive film. A method for manufacturing a field effect semiconductor device.