JPH0321879A - Timing signal generating circuit of tester - Google Patents

Abstract

PURPOSE:To generate timing pulses to many rate widths by providing a phase clock generating circuit with plural counters, and cascading and putting them in operation as one counter or independent counters. CONSTITUTION:A control circuit 29 when receiving a two-rate setting signal from a CPU 12 as a timing phase range setting signal T sends a state setting control signal for putting the counters 25a - 25d in independent operation to state setting circuits 22 and 23 respectively. Further, when a 4-rate signal is received, a signal which cascades and puts the counters 25a and 25b, and 25c and 25d in operation is sent out to the circuits 22 and 23 respectively. Thus counted values are preset in the counters according to an RTTC signal from a pattern generating circuit 1 after rate pulses are received and then the counters are made to count up. Consequently, when the RTTC signal is generated plural times in one rate, a phase clock pulse can be generated at each time and many phase clock pulses can be set in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing signal generation circuit for a tester. The present invention relates to a timing signal generation circuit in a pattern generation system for a tester that generates waveform patterns.

[Prior Art] In an IC testing system, a multi-bit test waveform pattern necessary for performance and functional testing of an IC is
Automatically generated according to a test pattern program, etc. Therefore, in the conventional pattern generation system, the necessary data for each pin of the IC is selected from among the pattern data obtained from the pattern generator and the phase clock signal with multiple phases generated by the timing signal generation circuit. The test pattern is selected and synthesized to generate a predetermined waveform pattern, the generated test pattern is sent to a drive circuit, the output is level-converted, and then supplied to a predetermined IC pin. There is.

The phase clock signal in this case is normally used to determine the rise and fall timing of the test pattern, and the timing signal generation circuit generates a large number of different phases at a period corresponding to the test reference period (rate). A clock signal (hereinafter referred to as phase clock pulse) is generated at each phase clock output terminal.

Such phase clock pulses are generally generated by counting the reference clock signal by preset timing data, but the timing phase setting range of conventional timing generators is up to about 2 rates. For example, if the rate period is about tons, 2nns
Normally, settings can be made to generate phase clock pulses within a certain range of degrees.

[Problem to be solved] However, as the functions and speed of ICs to be measured improve,
Correspondingly, the period of the test rate has become shorter, and it is no longer possible to perform a sufficient performance test with a timing phase setting width of two rate periods, as in the past. However, if you simply increase the phase setting width to 4 rates, which is about 4 times the rate, for example, at a rate period of tons, generally 1
Since it is required to set the timing position within the rate minutely in ins units, the phase setting width is 4 for 1 rate.
Expansion to double the size would significantly increase the amount of hardware required, and its control would also become complicated.

The purpose of the present invention is to solve the problems of the prior art, and to suppress the increase in vehicle-specific hardware, and to generate timing pulses over a large number of rates. The purpose of the present invention is to provide a timing signal generation circuit for a tester that can perform the following steps.

[Thousand Steps to Solve the Problems] The configuration of the timing signal generation circuit of the tester of the present invention to achieve the above object includes a clock signal generation circuit and a clock signal from the clock signal generation circuit or from the outside. The circuit includes a rate pulse generation circuit that generates a rate pulse of a predetermined period in response to a clock signal of It is selected whether to operate the second counter independently or to connect them in series to operate as one counter, and the timing phase range setting signal indicates a predetermined n rate (n is a positive integer). Sometimes, the first and second counters are operated as one counter, and each rate pulse n receives a clock signal and counts up to the value set in the first counter in accordance with the corresponding rate pulse, and then the second counter is operated as one counter. the output of the second counter is generated as a phase clock pulse, and when the timing phase range setting signal indicates the 2n rate, the first and second counters are counted as independent counters. It receives a clock signal according to the first rate pulse corresponding to every n, counts up to the value set in the first counter, generates the output as a phase clock pulse, and generates the next rate pulse for every n. and a phase clock generation circuit that receives the clock signal in response to a pulse, counts up to a value set in a second counter, and generates the output as a phase clock pulse.

[Function] In this way, the phase clock generation circuit is provided with at least two counters, and depending on the timing phase range setting signal, these counters can be connected in cascade to operate as one counter or as independent counters. By doing this, depending on the rate pulse signal, for example, if n=1, it is possible to select whether to generate a phase clock pulse corresponding to one rate or to generate a phase clock pulse corresponding to double the rate. I can do it.

As a result, it becomes possible to easily change and test the timing phase width in the same circuit according to the function of the IC whose timing phase width is to be measured, without increasing the hardware. I can do it.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a timing signal generating circuit of a tester according to the present invention.

In FIG. 1, lO is a timing signal generation circuit, and a rate pulse generation circuit il! ? The phase clock generation circuit 2 includes a timing data memory 21, state setting circuits 22, 23, a data selector 24, and a reference clock generation IFJTI1 path 2. Fourth counter 25a. 25b. 2
5c, 25d, AND circuits 26, 27, OR circuit 28,
and a control circuit 29.

The rate pulse generation circuit 1 operates upon receiving data from the pattern generation circuit 41l, receives the clock pulse from the reference clock generation circuit 3, and divides the clock pulse according to the frequency division data received from the CPU 12 to generate rate pulses of a predetermined period. It is generated and sent to other circuits of the tester, and also sent to the phase clock generation circuit 2.

The phase clock generation circuit 2 receives rate pulses generated corresponding to the reference period of the test from the rate pulse generation circuit 1 to the control circuit 29, and receives the RTTC signal (real-time control data) from the pattern generation change 11 as its timing data. The memory 2l receives the clock pulse CK from the reference clock generation circuit 3, and the clock pulse CK is sent to the counter 25a. 25b, 25c
, 25d respectively receive this clock pulse CK and count it up to a predetermined set value.

The data memory 21 receives the RTTC signal as an address signal, is accessed by the RTTC signal, reads out data at the accessed address, and sends it to the data selector 24.

In this case, the maximum number of data read at one time is the number of data set in the counters 25a to 25b, which is distributed by the data selector 24 corresponding to each counter.

The data selector 24 transfers the data read from the timing data memory 21 to the first to fourth counters 25a, 25b, . 25c. 2
5d at the same time, or the first and second control signals
counters 25a, 25b at the same time, and the next control signal is sent to the third, fourth counters 25c, . 25d and whether to send them at the same time.

Counter 25a. 25b. 25c and 25d receive a load signal from the control circuit 29 and, in response thereto, respectively store the data sent from the data selector 24 as its preset value.

The control circuit 29 receives the timing phase range setting signal T from the CPU 12 (or from the rate pulse generation circuit 1 or the pattern generator 11), receives the rate pulse from the rate pulse generation circuit 1, and also receives the rate pulse from the rate pulse generation circuit 1. It receives an RTTC signal from. When the timing phase range setting signal T is received, a switching control signal according to the instruction of the timing phase range setting signal T is sent to the state setting circuit 22, 23 to set the internal connection state, and the timing phase range setting signal T is set. Setting signal T and RTTC
A control signal is sent to the data selector 24 in response to the signal, and the internal state of the data selector 24 is switched in accordance with the instruction of the timing phase range setting signal T. It also controls the storage of data read from the timing data memory 21 into each counter and activates the state setting circuits 22 and 23.

The state setting circuit 22 is activated in response to an activation signal from the control circuit 29, and is activated in response to a control signal from the control circuit 29. 25b is operated in a cascade connection or is operated separately.

Then, the control signal is sent to the counter 25a. 25b are operated independently, the gate of the AND circuit 26 is opened and the counters 25a. 25b respectively at predetermined timings corresponding to the rate pulses to start counting the preset values set in the respective counters, and when the counting ends (“0”). )
Then, the final output of each count is controlled so as to be outputted as phase black and phase pulses via an OR circuit 28. Further, when the control signal from the control circuit 29 indicates that these counters are to be connected in series and used as one counter, the gate of the AND circuit 26 is closed, and the enable signal a is first sent to the counter. 25a
to start counting the preset value,
When the preset value 1^ has counted up to "0" (4 points), the count end r signal is received from the counter 25a, and the enable signal b is sent to the counter 25b to operate it, and the counter 25b receives the preset value. Start counting.

Then, when the precent value is counted up to "0", the count end signal is output from the OR circuit 28 as a phase clock pulse.

The state setting circuit 23 is also a circuit similar to the state setting circuit 22, and is activated in response to an activation signal from the control circuit 29.
Further, the counter 2
5c. 25d is operated in a cascade connection, or is operated separately. Then, the control signal is sent to the counter 25c. 25d are to be operated independently, the gate of the AND circuit 27 is opened, and enable signals c+d of the counters 25c and 25d are sent out at predetermined timings corresponding to the rate pulses, and set in the respective counters. Counting of the preset values is started, and when the count ends (when it becomes "0"), the respective count end outputs are outputted as phase clock pulses via the OR circuit 28. Further, the control signal from the control circuit 29 connects these counters in series so that one
When indicating that the counter is to be used as one counter, the gate of the AND circuit 27 is closed, and the enable signal C is sent out to operate the counter 25c and start counting the preset value, so that the preset value becomes "0". When the counter 25c has counted up to 1, the counter 25c receives a count end signal and sends an enable signal d to the counter 25d to operate it. The counter 25d starts counting the preset value, and the preset value becomes "O".
When the count is reached, the count end signal is turned O.
The R circuit 28 outputs it as a phase clock pulse.

Next, the overall operation of such timing generation circuit 10 will be explained.

First, when the control circuit 29 receives a setting signal of either 2 rates or 4 rates as the timing phase range setting signal T from the CPU 12, the control circuit 29 determines whether the timing phase range setting signal T is 2 rates or 4 rates.
When the rate is the counter 25a, 25b . 25c,
A state setting control signal for operating each of the state setting circuits 22 and 25d independently is sent to the state setting circuits 22 and 23, respectively. Also,
When it is 4 rates, counters 25a and 25b1
Then, a state setting control signal for operating the counters 25c and 25d in a subordinate manner is sent to the state setting circuit 2.
Send on 2.23.

When the actual measurement state is entered and the set width is 2 rates, when the control circuit 29 receives the first rate pulse from the rate pulse generation circuit 1, the R pulse from the pattern generation circuit 1 is
It operates according to the TTC signal, and the timing data memory 21 is accessed by the RTTC signal, and the read data is sent to the counters 25a, 25a,
2 5 b. 2 5 °c. 25d at the same time. The control circuit 29 then controls the state setting circuit 2.
2, the counters 25a. 25b is controlled to operate as one counter.

As a result, the enable signal a is sent from the state setting circuit 22, and the counter 25a operates first.
counts up to "O", then the enable signal b is sent from the state setting circuit 22, the counter 25b operates, and the counter 25b counts up to "0", and the count end r signal generates the phase clock as a phase clock pulse. Output from circuit 2.

Next, when the control circuit 29 receives a rate pulse, the control circuit 29 activates the state setting circuit 23 and sets the counter 25c. 25d is controlled to operate as one counter. As a result, the enable signal C
is sent out, and then the counter 25c operates, and the counter 25c counts up to "0". Then, the enable signal d is sent out, and the counter 25d operates, and the counter 25c counts up to "0".
The count end signal of the counter 25d is output from the phase clock generation circuit 2 as a phase clock pulse.

On the other hand, the actual 7! When the control circuit 29 enters a steady state and the set width is 4 rates, when the control circuit 29 receives the first rate pulse from the rate pulse generation circuit 1, it operates in response to the RTTC signal from the pattern generation circuit 1. The timing data memory 21 is accessed,
The read data is simultaneously preset into counters 25a and 25b via data selector 24. Next, the control circuit 29 operates the state setting circuit 22 so that the counter 2
5a + 2 5b is controlled to operate as an independent counter.

As a result, the enable signal a is generated from the state setting circuit 22, the counter 25a operates, and the counter 25a becomes "0".
”, and the count end signal is output from the phase clock generation circuit 2 as a phase clock pulse.Next, when the control circuit 29 receives the rate pulse,
A state setting circuit 22 receiving a control signal from a control circuit 29
generates the enable signal b, and in response, the counter 2
5b operates, the counter 25b counts up to "0", and the count end signal is output from the phase clock generation circuit 2 as a phase clock pulse.

Then, when the control circuit 29 further receives a rate pulse from the rate pulse generation circuit 1, the control circuit 29
This time, the state setting circuit 23 is activated. As a result, the enable signal C is generated from the state setting circuit 23, the counter 25c operates, the counter 25c counts up to "0", and the count end signal is outputted from the phase clock generation circuit 2 as a phase clock pulse. Furthermore, the next time the control circuit 29 receives a rate pulse, the state setting circuit 23 that has received the control signal from the control circuit 29 generates an enable signal d, and the counter 25d operates in response to this, and the counter 25d registers " The count end signal is output from the phase clock generation circuit 2 as a phase clock pulse.

In this way, after receiving the rate pulse, the RTTC
If you preset the count value in the counter according to the signal and start counting, it is possible to generate the phase clock pulse each time by generating the RTTC signal multiple times within one rate. Yes, it is possible to set a number of phase clock pulses in real time. Also, in this case, after receiving the rate pulse, R
It controls so that each counter stores a preset value and starts counting in response to a TTC signal.
An RTTC signal may be generated before the rate pulse is generated, a preset value is set in each counter upon receiving this RTTC signal, and upon receipt of the next rate signal, the counters may start counting at that timing. In this way, phase clock pulses can be generated for each rate.

Further, the preset value of each counter may not be set in response to the RTTC signal, but may be stored from a pattern generator or the like at the start of each measurement or before each rate pulse is generated.

As explained above, in the embodiment, the timing phase width is set by switching the 2/4 rate.
In this case, if you set the timing phase with a 2-rate cap,
It is possible to set the phase with twice the accuracy as in the case of 4 rate widths. Furthermore, in the embodiment, two counters are paired and controlled in units of two rates;
The preset values may be sequentially set using the TC signal. Furthermore, since 4 counters are provided, 3
It is also possible to set the phase by sequentially switching the counter according to the rate. Therefore, in the embodiment, it is possible to vary the rate cycles from 2 to 4 and generate a phase clock for each rate cycle as a unit.

Of course, if the setting range is one rate, each of the plurality of counters may be operated independently in units of one rate.

In the embodiment, a configuration is adopted in which four counters are switched and used, but it goes without saying that more counters may be used.

Furthermore, when switching from one rate width setting to two rate widths, it is sufficient to provide at least two counters and switch whether these counters operate independently or as one counter.

In addition, in the embodiment, both the rate pulse generation circuit and the phase clock generation circuit operate by obtaining cross pulses from the same reference clock generation circuit, but they receive clock pulses from separate clock generation circuits. Of course it's a good thing.

[Effects of the Invention] As can be understood from the above explanation, in the present invention, at least two counters are provided in the phase clock generation circuit, and the counters are controlled according to the timing phase range setting signal.
By cascading them and operating them as one counter, or operating them as independent counters, you can generate phase clock pulses corresponding to one rate according to the rate pulse signal, for example, if n=1, double 2
It is possible to select to generate phase clock pulses corresponding to the rate.

That is, I should measure the timing phase on the same path with almost no increase in hardware.
It becomes possible to easily modify and test the history corresponding to the functions of C, and its settings can be easily controlled.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the timing signal generation circuit of this tester. l... Rate pulse generation circuit, 2... Phase clock generation circuit, 3... Reference clock generation circuit, 10...
Timing signal generation circuit, 11... Hattern generation W, 12... CPU21...
- Timing data memory, 22.23... Status setting circuit, 24... Data selector, 25a. 25b. 25c. 25d...First to fourth counter AND circuits, 28.27...AND circuit, 28...OR circuit, 2
9...Control circuit.

Claims (2)

[Claims] (1) A clock signal generation circuit, a rate pulse generation circuit that receives a clock signal from the clock signal generation circuit or an external clock signal and generates a rate pulse of a predetermined period, and first and second counters. have,
Depending on an external timing phase range setting signal, it is selected whether to operate the first counter and the second counter independently or to connect them in a subordinate manner to operate as one counter, and the timing phase range setting signal is a given n
When a rate (n is a positive integer) is specified, the first and second counters are operated as one counter, and the first counter receives the clock signal in accordance with the rate pulse corresponding to each rate pulse n. counts up to a value set in a counter, then counts up to a value set in a second counter, and generates the output of the second counter as a phase clock signal, and the timing phase range setting signal sets the 2n rate. 1st and 2nd when giving instructions
operate the counter as an independent counter, receive the clock signal and count up to the value set in the first counter according to the first rate pulse corresponding to each n, and use the output as a phase clock signal. and a phase clock generation circuit that receives the clock signal according to the next rate pulse every n, counts up to a value set in a second counter, and generates the output as a phase clock signal. A tester timing signal generation circuit featuring: (2) The phase clock generation circuit has first, second, third, and fourth counters, and the first counter and the second counter are controlled according to an external timing phase range setting signal. It is selected whether to operate independently or to operate these counters in a cascade manner as one counter, and to operate the third and fourth counters independently or to operate them in a cascade manner as one counter. When the timing phase range setting signal indicates two rates, the first and second counters and the third and fourth counters are each operated as one counter to obtain the first rate. It receives a clock signal in response to a pulse, counts up to a value set in a first counter, then counts up to a value set in a second counter, and generates the output of the second counter as a phase clock signal. , receives the clock signal in response to the next rate pulse, counts up to the value set in the third counter, then counts up to the value set in the fourth counter, and outputs the output of the fourth counter. When the timing phase range setting signal indicates 4 rates, the first, second, third, and fourth counters are operated as independent counters, and the first rate pulse is generated as a phase clock signal. In response to the rate pulse, the clock signal is received and counted up to the value set in the first counter, and the output thereof is generated as a phase clock signal, and in response to the next rate pulse, the clock signal is received and counted up to the value set in the first counter. A third counter counts up to a set value and generates its output as a phase clock signal, and then receives the clock signal in response to the next rate pulse, counts up to a value set in a third counter, and generates its output as a phase clock signal. a phase clock generating circuit that generates a clock signal, receives the clock signal according to the next rate pulse, counts up to a value set in a fourth counter, and generates the output as a phase clock signal; 2. The timing signal generating circuit for a tester according to claim 1, further comprising: a timing signal generating circuit for a tester.