JPH03219350A - Self-checking bus arbiter - Google Patents

Abstract

PURPOSE:To simply and quickly check the normal operation of a bus arbiter by selecting the same module in each times, confirming normal arbitration operation and detecting a failure. CONSTITUTION:A module requesting bus using right outputs arbitration numbers belonging to a code '1' to lines an0 and an6 and sets up a Comp signal and the inverse of Comp signal respectively to '1' and '0'. A module requesting in the next arbitration outputs arbitration number belonging to a code '2' to lines an0 to an6 and set up the Comp signal and the inverse of Comp signal respectively to '0' and '1'. As the result of two arbitrations, a module having respective outputs (1,0), (0,1) is regarded as a module succeeding in bus using right acquisition. The absence of the module for acquiring the bus using right indicates the existence of a failure on the arbiter of a bus line. Consequently, the abnormality of the bus line can be detected in addition to the detection of abnormality on the arbiter and the normal operation of arbitration can be confirmed.

Description

Detailed Description of the Invention (1) Purpose of the Invention [Field of Industrial Application] The self-checking bus arbiter according to the present invention can be used as an arbiter for a bus coupling system that detects internal and external failures and is required to operate reliably. It is used.

[Prior Art] There have long been methods of adding check pits to provide redundancy to the arbitration numbers held by each module, and methods of detecting abnormalities by re-examining the arbitration numbers that have survived on the bus. but,
The detection ability is low when the number of redundant bits is small, especially when failures occur within the module, and in order to improve this, the device must be complicated, resulting in a disadvantage that the time required for its operation becomes longer.

[Problems to be Solved by the Invention] It is an object to be solved by the present invention that the structure is simple and that it is possible to confirm that the bus arbiter is operating normally in a short period of time.

(2) Structure of the invention [Means for solving the problem] As shown in Fig. 1, each module has multiple types of codes (
For example, each code has arbitration numbers belonging to code 1 and code 2), and arbitration is performed multiple times using each code.
This problem can be solved by configuring the module to acquire the right to use the bus by performing arbitration multiple times and confirming that the arbitration has been completed each time.

[Operation] As an example, assume that arbitration is performed multiple times using codes that satisfy the following conditions.

Consider code 1 and code 2 belonging to two code spaces whose elements correspond one-to-one, and use them in the first and second arbitration. It is assumed that an order relationship corresponding to a binary number is determined for each code, and the order relationship of codes belonging to one space is reversed in the other space. Also, all corresponding elements in the two spaces are reversed.

Here, the module has a set of codes that satisfy this condition as its own arbitration number, and uses this number to arbitrate.The arbitration number of the first surviving module is the highest among those belonging to code 1 at that time. The arbitration number belonging to code 2 appears on the bus, but if we reverse the bit order from the upper bits to the lower bits and perform arbitration, this means that the module with the largest arbitration number This is the arbitration number belonging to code 2. This is because the numbers belonging to code 2 are in reverse order with respect to the numbers belonging to code 1. If this module survives again, the code that satisfies the condition will have all the bits on the bus inverted, so it can be confirmed that there is no failure in this arbiter. Here, the bus arbiter has a self-checking configuration.

[Embodiments] Examples of the present invention will be described below with reference to the drawings. 2, 3, and 4 illustrate a code generation method and circuit diagram used in a self-checking path arbiter according to an embodiment of the present invention. Codes that satisfy the conditions include codes such as those shown in FIGS. 2 and 3.

The code generated by the method shown in Figure 2 is called a symmetric inversion code,
Generate from half the bits of the target code. this is,
Each bit path is calculated from all the patterns, and a pattern in which each bit is inverted is added to the end of all the original patterns to generate it.

The code generated by the method shown in Figure 3 is called an inverted order code.
Generate from the code two codes before the target code. Add 0.1 and 1°0 to the left and right sides of the previous code to divide it into an upper code set and a lower code set. Furthermore, it is generated by inserting an arbitrary code that satisfies the conditions between them.

Using the code generated in this way, arbitration is performed in the circuit shown in FIG. In the first arbitration, the module requesting the right to use the bus outputs the arbitration number belonging to code 1 to anO to an6 in FIG. 4, and sets the Comp signal to 1 and the Comp signal to 0. Each module requesting the next arbitration outputs the arbitration number belonging to code 2 to anO to an6, and also sets the Comp signal to 0 and the Co2P signal to 1. This 2
The output shown in Figure 4 (Ma, Ri is (1,0
), (o, 1) is the module that successfully acquired the right to use the bus. If no module obtains the right to use the bus, it indicates a failure on the arbiter and pass line.

(3) Effects of the Invention According to the present invention, it is possible to detect abnormalities occurring not only on the path line but also inside the modules constituting the arbiter, so it is possible to confirm the normal operation of arbitration.

Therefore, using this, a highly reliable multipro
It is a constituent country of the bus arbiter.

FIG. 2 shows a method for generating a symmetric inversion code, and the third section shows a method for generating an inversion order code, taking the case of 4 bits as an example. FIG. 4 is an example of a self-checking bus arbiter circuit that operates using these codes.

Claims (1)

[Claims] 1. By performing the arbitration operation multiple times, the same module is selected each time, so that it is possible to confirm the normal operation of the arbitration, and also to detect any failure. Configured arbiter. 2. The arbiter according to claim 1, which is capable of detecting a failure occurring on a line in a system configuration in which a plurality of modules are connected to one line. 3. The arbiter according to claim 1, which performs arbitration using a plurality of codes having the same magnitude relationship and belonging to different code spaces. 4. The arbiter according to claim 1, which is capable of confirming normal operation of the arbiter and detecting failure by using a code that inverts all bits on the arbitration bus during arbitration to acquire the bus.