JPH03219359A - Interface circuit - Google Patents

Abstract

PURPOSE:To shorten the time required for transmitting/receiving data when the number of data to be transferred is increased by controlling the whole system so as to execute direct memory access to a storage means device for transferring data between plural central processing units (CPUs). CONSTITUTION:In the case of transmitting data from the CPU 1 to the CPU 2, the CPU 1 transfers transmitting data set up in a CPU memory 3 to a dual port RAM 7 based upon the memory-to-memory operation of a DMA control circuit 5. The circuit 5 outputs the DMA end signal of channel 1 to the CPU 2 and a square wave generator 8 as a data transmission end signal and the CPU 2 inputs the data written in the RAM 7. When the data written in the RAM 7 are transferred to a CPU memory 4, a DMA control circuit 6 outputs the DMA end signal of channel 2 to the CPU 2 and a square wave generator 9 as a data reception end signal. Thus, even if the number of data is increased, the time required for transmitting/receiving data can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an interface circuit, and particularly to an interface circuit used for data transfer between 020 and 020.

Prior Art Conventionally, in this type of interface circuit, the CPU
Data transfer between the two is done via dual-port RAM (random access memory), and data is written to the dual-port RAM when sending data to the other CPU, and data is transferred from the other CPU. Reading of data from the dual port RAM during reception was performed by a memory transfer command from the CPU.

In such conventional interface circuits, writing and reading data to and from the dual port RAM was performed using memory transfer instructions from the CPU, so when the number of data transferred between CPUs increases, data transmission and reception may be delayed. The disadvantage is that it takes time.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and provides an interface that can reduce the time required for data transmission and reception even when the number of data transferred between CPUs increases. The purpose is to provide circuits.

Structure of the Invention The interface circuit according to the present invention is an interface circuit that transfers data between the first and second central processing units through storage means provided in common to the first and second central processing units. control to perform direct memory access to the storage means in response to commands from the first and second central processing units, corresponding to the first and second central processing units; It is characterized by having a means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a dual port RAM 7 for an interface is provided between the CPU (Central Processing Unit) and 2, and reading and writing of data to and from the dual port RAM 7 is performed using DMA (Direct Memo
ry Access) control circuit 5.6.

The CPU memory 34 is connected to the CPU I, 2 and the DMA control circuit 5.6 via address bus a and data bus b, respectively.
The DMA control circuits 5 and 6 are connected to a dual-port RAM 7 via an address bus a and a data bus b, respectively.

Periodic square wave input signals from square wave generators 8 and 9 are input to the DMA request terminal of the DMA control circuit 5.6, and the square wave input signal of channel 1 is sent from the CPU memories 3 and 4 to the dual port RAM 7. The square wave input signal of channel 2 is used to write data from the dual port RAM 7 to the CPU memories 3 and 4.

On the other hand, the DMA end signal of channel 1 is output as a data transmission end signal to the other party's CPUs 2, 1 and square wave generator 8.9, and the DMA end signal of channel 2 is output as a data reception end signal to CPUs 1, 2 and square wave generator 8. .9 is output.

Also, both channel 1 and channel 2 are in demand release mode, memory-to-memory (meIl).

ry to memory).

That is, when the square wave input signal of channel 1 and the square wave input signal of channel 2 are high, data is transferred between the CPU memories 3 and 4 and the dual port RAM 7 via the address bus a and the data bus b. , when the square wave input signal of channel 1 and the square wave input signal of channel 2 are low, the CPU 1.2 uses address bus a and data bus b to perform processing operations, respectively.

Next, the operation of one embodiment of the present invention will be explained using FIG.

First, when sending data from CPUUI to CPU2,
The CPU transfers the transmission data set in the CPU memory 3 to the dual port RAM 7 by the memory-to-memory operation of the DMA control circuit 5.

At this time, the CPU 1 or the square wave generator 8 is instructed to output the square wave input signal to channel 1, so D
A square wave generator 8 is connected to channel 1 of the MA control circuit 5.
A square wave input signal is input manually, and the DMA control circuit 5 activates the memory-to-memory operation by enabling this square wave input signal, and transfers the transmission data set in the CPU memory 3 to the dual port RAM 7.

When the data for transmission set in the CPU memory 3 is transferred to the dual port RAM 7, the DMA control circuit 5 outputs the DMA end signal of channel 1 to the CPU 2 and the square wave generator 8 as a data transmission end signal.

The square wave generator 8 uses the data transmission end signal from the DMA control circuit 5 as a disable signal for outputting the square wave input signal to channel 1.

On the other hand, the CPU 2 uses the data transmission end signal from the DMA control circuit 5 as an interrupt signal to read data written from the CPU memory 3 to the dual port RAM 7.

That is, the CPU 2 transfers the data written in the dual port RAM 7 to the CPU memory 4 by the memory-to-memory operation of the DMA control circuit 6.

At this time, CPIJ2 instructs square wave generator 9 to output a square wave input signal to channel 2, so
A square wave input signal from a square wave generator 9 is input to channel 2 of the DMA control circuit 6, and the DMA control circuit 6 receives a square wave input signal from a square wave generator 9.
Then, by enabling this square wave human input signal, a memory-to-memory operation is started, and the data written in the dual port RAM 7 is transferred to the CPU memory 4.

When the data written in the dual port RAM 7 is transferred to the CPU memory 4, the DMA control circuit 6
The CPU 2 uses the DMA end signal as the data reception end signal.
and output to the square wave generator 9.

The square wave generator 9 uses the data reception end signal from the DMA control circuit 6 as a disable signal for outputting the square wave input signal to channel 2.

As a result, data is transmitted from the CPUI to the CPtT2, so even if the amount of data transferred between the CPUI and the CPU2 increases, the time required for data transmission and reception can be reduced.

When transmitting data from the CPU 2 to the CPU I, the data can be transmitted in the same manner as the processing operation for transmitting data from the CPU I to the CPU 2 described above.

In this way, corresponding to CPUI, 2, CPU1,
By providing DMA control circuits 5 and 6 that control direct memory access to the dual port RAM 7 in response to commands from the CPU 2,
Even if the amount of data increases at the interface between I and 2, the time required for data transmission and reception can be reduced.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, in response to instructions from the first and second central processing units, the first and second central processing units are provided in common, and each of these central processing units By providing control means corresponding to each of the first and second central processing units to control direct memory access to the storage means for data transfer, the control means for each of these central processing units can be Even when the amount of data to be transferred increases, there is an effect that the time required for data transmission and reception can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 12... CPU 34... CPU memory 56... DMA control circuit 7... Dual port RAM 89... Square wave generator

Claims (1)

[Claims] (1) An interface circuit that transfers data between the first and second central processing units via a storage means provided in common to the first and second central processing units, A control means is provided corresponding to each of the two central processing units for controlling direct memory access to the storage means in response to commands from the first and second central processing units. interface circuit.