JPH03219365A - Digital signal processor - Google Patents

Abstract

PURPOSE:To minimize the number of steps for digit reduction or a saturation processing instruction by controlling the 1st and 2nd data memories, a logical operation circuit and a computing element by common program memory, program controller and address generator. CONSTITUTION:The 1st and 2nd data memories 12, 13, the logical operation circuit 20 and the arithmetic unit 14 are constituted so as to be controlled by the common program controller 15 and address generator 16. Thereby, the data (m) of the 2nd data memory 13 are read out on the way of transfer of data a' computed by the computing element 14 to the 1st data memory 12 and both the data m, m' are inputted to the circuit 20, so that the data a' is automatically deformed (digit reduction) by the data (m) and stored in the 1st data memory 12. Consequently, the number of steps for digit reduction or the saturation processing instruction can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a common digital signal processing device for extracting image features of a digital video signal and performing signal conversion processing.

(Prior art) Among the digital signal processing processors (DSPs) that have been miniaturized using digital semiconductor integrated circuits, analog signals can be converted into analog-to-digital converters, rather than general office calculations or ordinary scientific and technical calculations. There is a digital semiconductor integrated circuit for the purpose of obtaining a time-series digital signal through a filter and then performing filter processing and signal conversion processing on this digital signal.

For example, Japanese Patent Publication No. 64-2290, Japanese Patent Publication No. 1-13
No. 764 discloses a construction method for high-speed calculation of a digital filter. Although the present invention also aims to improve processing speed, it is aimed at improving the calculation speed not only in digital filter calculations but also in more general digital signal processing.

As a more general example, a commercially available digital signal processing device will be described as a conventional example.

FIG. 4 is a block diagram showing a conventional digital signal processing device. 1 is a program memory (RAM) that stores system execution instructions, and 2 and 3 are data memories (RAM) that store initial values before executing instructions and values during execution.
). 4 is an arithmetic unit (ALU) that performs calculations such as accumulation, multiplication, logical sum, and logical product; 5 is a program controller that interprets instructions and controls each component; 6 is a computer that calculates address values for each memory; It is an address generator to control.

Initial values and constant values of data are transferred and stored in the data memory 2.3 from external devices through data buses B1 and B2, and instructions are transferred and stored in the program memory 1 from external devices through bus B3. Ru.

At the start of calculation, when the address generator 6 is initialized and the program controller 5 is initialized from an external device via the bus B3, the instructions in the program memory 1 are read by the program controller 5, and specific calculation processing is performed. will be started.

If you try to apply the above signal processing device to perform the processing necessary for filter operations, you will not only be able to perform arithmetic operations such as accumulation, multiplication, logical sum, and logical product, but also digit loss,
Processing such as signal amplitude saturation is required.

When processing such as digit loss and saturation is executed in the above system, the following steps are taken.

Sl... It is assumed that data a before digit loss is obtained by the arithmetic unit 4 and held.

S2...Load: Transfer data m at address M of data memory 2Q to the internal register of arithmetic unit 4.

S3 . . . AND: Executes bit-by-bit logical product of data a' and data m inside the calculating unit 4, and holds the logical product a in a register inside the calculating unit 4.

S4...Store: Transfer data a inside the arithmetic unit 4 to address A of the data memory 1.

(Problem to be solved by the invention) Although the calculation elements are simple if the precision reduction is executed by hardware as described above, if it is executed entirely by software, it will require more than one instruction step. .

For image data, especially moving image data for tens of seconds,
It is about 5*108 pieces of data and takes 10 instruction cycles.
"see (loOnsec)" requires 50 seconds.This instruction requires 100 to 200
If so, it would be 5,000 to 10,000 seconds longer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a signal processing device that can minimize the number of steps of digit loss and saturation processing instructions.

[Structure of the Invention (Means for Solving the Problems) This invention provides an arrangement in which an output terminal of a logic operation circuit is connected to a data input terminal of a first data memory, and an arithmetic operation circuit is connected to one input terminal of the logic operation circuit. A first data bus to which is connected is connected to the other input terminal, a second data bus to which a second data memory is connected is connected to the other input terminal, and the first and second data memories, logical operations The circuit and arithmetic unit are configured to be controlled by a common program controller and address generator.

(Function) With the above means, while data a' calculated by the arithmetic unit is being transferred to the first data memory, data m from the second data memory is read out, and the two data a' and m are logically combined. When passed through the arithmetic circuit, data a' is automatically transformed (with digits dropped) by data m and stored in the first data memory.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

Reference numeral 11 is a program memory (RAM) for storing system execution instructions, and 12 and 13 are data memories (RAM) for storing initial values before executing the instructions and values during execution. 14 is an arithmetic unit (ALU) that performs calculations such as accumulation, multiplication, logical sum, and logical product; 15 is a program controller that interprets instructions and controls each component; and 16 is a program controller that controls the address values of each memory. It is an address generator that calculates and controls.

Instructions are transferred from an external device through the data bus B3 and stored in the program memory 11. The data memory 13 is connected to a data bus B from an external device.
1, data such as initial values are accumulated.

In addition, in the data memory 14, is it possible to transfer and store data from an external device via the data bus B2, and also to store data in the middle of a calculation from the arithmetic unit 14? A logic circuit 20 is provided in the middle.

The logic circuit 20 can obtain the results of the digit loss and saturation processing, and supplies the output to the data input terminal of the data memory 12. One data bus of this logic circuit 20 is coupled to data bus B2, and the other data bus is coupled to data bus B1. Therefore, data read from data memory 13 can also be supplied to logic circuit 20. Also connected to logic circuit 20 is a control bus which is connected to program controller 15 and address generator 16 . Therefore, the conduction bit lines and direction of the logic circuit 20 are controlled on and off through the control bus.

FIG. 2 shows an example of an arithmetic path for one bit in the logic circuit 20.

The bit line b21 is a line from the arithmetic unit 14, and the bit line bll is a line from the data bus B]. The bit lines b21 and bit are connected to the AND circuit 201, and the bit line b21 is also connected to the input part of the three-state buffer circuit 202 and the output part of the three-state buffer circuit 203. The output of the AND circuit 201 is connected to the input part of the three-state buffer circuit 204. The output portions of the three-state buffer circuits 202 and 204 and the input portion of the three-state buffer circuit 203 are commonly connected to the input portion of the data memory 12.

Here, each three-state buffer circuit 202.203.
Each bit line of the control bus is connected to the control terminal 204.

The operation of the logic circuit 20 in each case will be explained below.

(1) When data is transferred from the data memory 12 to the arithmetic unit 14 (loading).

Three-state buffer circuit 203 is on, 202.2
04 is controlled to be off, and a read address is given to the data memory 12.

(2> Arithmetic unit) When data in data memory 12 is transferred from 4 (no decimal drop is performed) (store 1).

Three-state buffer circuit 202 is on, 203.2
04 is controlled to be off, and a write address is given to the data memory 12.

(3) When data in the data memory 12 is transferred from the arithmetic unit 14 (digits are dropped) (store 2).

Three-state buffer circuit 204 is on, 202.2
03 is controlled to be off, and a write address is given to the data memory 12. A read address is also given to the data memory 13. At this time, the calculation result from the arithmetic unit 14 is given to one side of the AND circuit 201, and the decimal constant from the data memory 13 is given to the other side. This results in
AND circuit 201, three cheese pad sofa circuit 20
4, the data with digits dropped is input to the data memory 12.

According to the above system, data processing is performed in the following steps.

Sl... It is assumed that the data a' before digit loss is calculated by the calculator 14 and held.

It is also assumed that data m, which is a constant for digit loss, is stored at address A of the data memory 13.

Furthermore, the data a after the digit drop is stored in the data memory 12, and is assumed to be stored at the same address A corresponding to the previous data m.

S2...If the settings are as described above, the data memory 12 is designated for writing and the data memory 13 is designated for reading. Further, data m is applied to the logic circuit 20 through the data bus B1, and data a' is applied to the logic circuit 20 through the bus B2, and each three-state buffer circuit is controlled by the control of the program controller 15. Then, data a with digits dropped automatically is obtained from the logic circuit 20 and stored at address A of the data memory 12.

Although the addresses of the data memories 12 and 13 can be specified by the same address data, that is, A, different addresses may be used. However, if the addresses are the same, addressing can be done using the same bus, and addresses can also be generated easily.

The above example shows an example in which data is transferred from the arithmetic unit 14 to the data memory 12, but conversely, introducing digit-drop data from the data memory 12 to the arithmetic unit 14 can also be easily achieved by simply changing the connections. In addition to the decimal drop, saturation processing is also possible depending on the contents of the constants from the data memory 13.

FIG. 3 shows another embodiment of the invention.

Components that are the same as those in FIG. 1 are designated by the same reference numerals. The difference is the method of providing control signals to the logic circuit 20. That is, in this embodiment, a control code memory 21 for the logic circuit 20 is provided, and a control signal can be given to the logic circuit 20 via the switch 22.

The data width of the control code memory 21 is twice the number of bits of the control signal, and stores the control signal C1 when writing data to the data memory 12 and the control signal C2 when reading data from the data memory 12. be able to.

When the switch 22 selects one side, the control signal for writing data to the data memory 12 is read from the control code memory 21, and when the switch 22 selects the other side, the control signal is read from the data memory 12. A control signal when data is read is read from the control code memory 21. Therefore, as the signal for controlling the switch 22, the write/read signal of the data memory 12 can be used as is. Note that when storing the control signal in the control code memory 21, the switch 23 is turned on;
It is stored from an external device via bus B1. Further, the addresses of the control code memory 21 also correspond to the addresses of the data memory 12, so that address control can be easily performed.

According to this embodiment, there is no need to improve the instruction code output from the program controller 15 to the control bus.

In the above embodiments, an AND circuit is shown as a logic operation section inside the logic circuit 20, or an operation section using an OR circuit, an exclusive OR circuit, or a combination of these for a specific purpose. good.

Further, in the above embodiment, the data width of the control code memory 21 was explained as being twice that of the data memory 12, but the address width of the control code memory 21 was
The address width is twice the address width of the data memory 12, and the address form given to the control code memory 21 is switched in accordance with writing and reading to the data memory 12, so as to distinguish between writing and reading of read control signals. You can.

[Effects of the Invention] As explained above, according to the present invention, it is possible to minimize the number of decimal places and the steps of saturation processing instructions.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of this invention, FIG. 2 is a circuit diagram showing a part of the logic circuit in FIG. 1, FIG. 3 is a circuit diagram showing another embodiment of this invention, and FIG. FIG. 4 is a circuit diagram showing a conventional signal processing device. 11...Program memory, 12.13...Data memory, 14...Arithmetic unit, 15...Program controller, 16...Address generator, 20...Logic circuit, 21...Control code memory , 22.23...Switch.

Claims (3)

[Claims] (1) Connecting an output terminal of a logic operation circuit to a data input terminal of a first data memory, and connecting a first data bus to which an arithmetic unit is connected to one input terminal of the logic operation circuit; A second data bus connected to a second data memory is connected to the other input terminal, and the first and second data memories, the logic operation circuit, and the operation unit are connected to a common program memory and a program controller. A digital signal processing device characterized in that it is configured to be controlled by an address generator. (2) The program memory, program controller, and address generator are further associated to control a third data memory, and the output section of the third data memory is connected to the control signal input section of the logic operation circuit. 2. The digital signal processing device according to claim 1, wherein the digital signal processing device is configured to be controlled to be conductive or non-conductive. (3) The third data memory has two sets of addresses corresponding to the addresses of the second data memory, and furthermore, the read data of the third data memory is read from and written to the second data memory. 3. The digital signal processing device according to claim 2, wherein one of the address outputs is selectively switched according to the signal.