JPH03219497A - Memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device constituted by a ROM, and particularly relates to a memory device that is connected to a CPU having a pipeline control function to increase its operating speed. .

[Conventional technology]

As CPUs become faster, memory devices connected to them are also required to operate at higher speeds. On the other hand, ROM is advantageous in terms of cost and integration, but the time from the start of the access operation to the output of data (hereinafter referred to as access time) is longer than other memories, and the CPU It is no longer able to cope with higher speeds.

Pipeline control is widely used as a method to solve this problem. In this case, the CPU outputs information regarding the memory access operation in advance before performing the access operation. Therefore, the memory device can start an access operation upon receiving this information, and the access time can be lengthened by the amount of this advance output.

However, in pipeline control, when access operations are performed continuously, a phenomenon occurs in which the minimum repetition time (hereinafter referred to as cycle time) of the access operations becomes shorter than the access time.

Since the memory integrated circuit cannot start the next access operation before finishing the access operation, the access time ≦
Cycle time. Therefore, even when connected to a CPU that performs pipeline control, the access time of the memory integrated circuit cannot be made longer than the cycle time of the CPU.

To solve this problem, an interleave control method has been proposed as a method of making the cycle time seen from the memory integrated circuit longer than the cycle time of the CPU. (Known example: 1985 edition 80286 Hardware Reference Manual) In this method, a memory device is configured with a plurality of memory banks, and when access operations are continuous, each memory bank is accessed alternately. Assign. As a result, the cycle time seen from the memory bank can be made longer than the CPU cycle time, and the access time seen from the memory can be made longer than the CPU cycle time.

[Problem to be solved by the invention]

In the interleave control method, by making the cycle time seen from the memory integrated circuit apparently longer than the cycle time of the CPU, the memory integrated circuit can be operated even if access time>cycle time in pipeline control.

However, in the interleave control method, it is necessary to configure the memory device with a plurality of memory banks, and the number of control circuits for controlling the memory integrated circuit is also required as many as the number of memory banks. As a result, the size of the memory device increases, making it difficult to apply it to small-scale memory devices.

An object of the present invention is to realize a memory device that can be directly connected to a CPU that performs pipeline control and that can simplify the control circuit by operating the ROM device with the apparent access time>cycle time.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a ROM section and the R.
In a ROM device having an output buffer that outputs read data from the OM section, a read data holding means is provided between the ROM section and the output buffer, and the ROM is
This is achieved by holding the read data output from the section by the read data holding means and then outputting it to the outside by the output buffer, and by performing the following access operation in the ROM section.

[Effect]

Since the access time of the ROM device is the sum of the access time of the ROM section, the delay time of the read data holding means, and the delay time of the output buffer, the access time of the ROM section is shorter than the access time of the ROM device. For this reason, a read data holding means is provided between the ROM section and the output buffer, and the ROM section can start the next read operation by holding the read data output from the ROM section and outputting it to the outside. The next read operation can be performed before the ROM device outputs the read data.

As a result, the cycle time of the ROM device appears to be
The cycle time is shorter than the access time of a ROM device.

This allows the ROM device to connect to the CP that performs pipeline control.
It becomes possible to connect directly to U.

〔Example〕

Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is a CPU, 2 is a memory control circuit, 3 is a ROM device,
4 is a ROM section, 5 is a data latch, and 6 is an output buffer.

CA is an address signal for the CPU1, CD is a data signal for the CPU1, and MR8 is a memory read operation start signal for the CPUI, and these signals are output from the CPUI.

OE is the read data output control signal of the ROM device 3, DL
E is a read data latch control signal and is output from the memory control circuit 2.

MDO is a read data signal of the ROM section 4, LMDO is a latched read data signal, and these signals are R
This is an internal data signal of the OM device 3.

The CPUI performs a memory retrieval operation.

Drives MR8 and notifies that it is a memory access
Data is read through D.

The memory control circuit 2 detects a memory access operation using the MR8 and drives OE and DLE to operate the ROM device 3.

The ROM device 3 includes a ROM section 4. It is composed of a data latch 5° and an output buffer 6. Read data of the memory circuit is output to MDO, and MDO is connected to LMDO via data latch 5. Further, the input terminal of the data latch 5 is connected to DLE. Furthermore, LMDO is outputted to CD via the output buffer 6. Further, address information is input from the MA, and the ROM section 4 performs a read operation based on the address information input from the MA. The data latch 5 outputs the data on the input terminal as it is to the output terminal Q when LE becomes LL I II, and when LE becomes LL I OI.
When it becomes I, the data from the input terminal immediately before it is transferred to the output terminal Q.
to hold.

As a result, when DLE becomes II 1'', the read data output to MDO is output as is to LMDO,
When DLE becomes 1'0'', the data at the input terminal immediately before that is held in LMDO.

The output buffer 6 outputs the data of the input terminal A to the output terminal Y when the input terminal EN becomes 0''', and puts the output terminal Y into a high impedance state when the input terminal EN becomes 0'''.

As a result, when OE becomes "110", LMDO data is output to CD, and when OE becomes "1", LMDO and C
D is separated.

FIG. 2 is a timing diagram showing the operation of the present invention. In the figure, T i (1) and T i (2) are idle cycles in which the CPU is not performing memory access operations;
s (1) and T s (2) are status cycles in which the CPUI notifies the outside of the start of the access operation, and 7 T c (1) and T c (2) are command cycles in which the access operation continues.

Through pipeline control, the CPUI outputs address information to the CA in advance from the cycle immediately before the status cycle. Therefore, in an access operation consisting of Ts(1) and Tc(1), from the beginning of T;(1) address information A1
is output and supplied to the ROM section 4.

The ROM unit 4 performs a read operation on the address information A1 at the time when the address information A1 is supplied, and performs a read operation R.
Output DI to MDO. The access time Tac of the ROM unit W3 is the sum of the access time Tac' of the ROM unit 4 and the delay time Toe of the output buffer 6, and Tac is
It will be shorter than c'. For this reason, the memory control unit 2 sets DLE to 110'' from the time when the read data RDI is determined on the MDO until the end of Tc(1), and causes the data latch 5 to hold the read data RDI output to the MDO.

Furthermore, the memory control circuit 2 outputs the read data RDI held in the LMDO to the CD by setting OE to "0" from the middle of Ts(1) to the end of Tc(1), and the CPUI outputs the read data RDI held in the LMDO to the CD. Read the read data RDI output to the CD at the end of (1).

At this time, the next read operation T s (2), T c (
2) address information A2 is CA from the beginning of Tc(1)
is output to. Then, the ROM section 4 starts a read operation for the address information A2, but at this time, the read data RDI is held in the data latch 5, so it does not affect the read operation of the ROM device 3. This allows R
The OM unit 4 can start the next read operation while the ROM device 3 is performing the read operation.

Therefore, according to the present invention, even if the access time Tac of the ROM device 3 is smaller than the cycle time Tcy of the CPU,
If the access time Tac' of the ROM unit 4 is shorter than Tcy, the read data can be held in the data latch 5, and the ROM device 3 operates without problems.

As a result, even if the CPUI cycle time becomes shorter than the access time of the ROM device 3 due to pipeline control, R
It becomes possible to operate the OM device 3.

〔Effect of the invention〕

According to the present invention, the cycle time of a ROM device can be made shorter than the access time, and a ROM device that can be directly connected to a CPU that performs pipeline M control can be realized. This makes it possible to reduce the minimum capacity of the memory device compared to the interleave control method, and also simplifies the memory control circuit, making it applicable to small-scale memory devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the present invention. 1... CPU, 2... memory control circuit, 3... ROM device, 4... ROM section, 5... data latch, 6...
Output buffer, 7... Input buffer, 8... Address latch, CA, CD... Address of CPUI, data signal, MR8... Memory read operation start signal of CPUI, MA... Address of memory circuit 4 Signal, OLE. ○E・OR, M device 3 operation control signal, MD○.

Claims (1)

[Claims] 1. In a memory device that performs a read operation by controlling a ROM device that has a ROM section and an output buffer that outputs read data from the ROM section to the outside, there is a space between the ROM section and the output buffer. Read data holding means for holding read data from the ROM section is provided, and after holding the read data output from the ROM section during a read operation in the read data holding means, the output is outputted to the outside by an output buffer. A memory device characterized in that the following access operation is performed on the ROM section. 2. The memory device according to claim 1, further comprising a ROM device in which the ROM section, the read data holding means, and the output buffer are configured in the same integrated circuit.