JPH03219747A - Frequency drift detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an analog component, to attain no adjustment and to reduce power consumption by detecting a phase difference between a modulation wave and a reference signal with digital processing and obtaining a data proportional to a frequency drift of a carrier from the distribution of phase differences. CONSTITUTION:A reference signal C0 obtained by a detector 20 is inputted to a phase difference detection means 40 and converted into a phase shift signal of n-phase C1-Cn by phase shift means 31,33. On the other hand, a same angular modulation wave is inputted to FFs 411-41n and latched in response to the phases C1-Cn. Phase difference data D1-Dn between the angular modulation wave from the FFs 411-41n and each phase shift signal are sent to a phase difference distribution detection means 50. The means 50 latches the data D1-Dn and the output obtained through phase difference classification is counted by counters 551-55n and the result is sent to a frequency drift detection means 60. The means 60 applies a prescribed arithmetic processing to obtain a data proportional to the frequency drift of the carrier depending on the distribution state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention detects frequency drift of a carrier wave and provides stable detection processing in a detector that modulates a carrier wave and demodulates a transmitted modulated signal. This invention relates to a frequency drift detection circuit for.

[Conventional technology]

Phase modulation and frequency modulation make a modulation signal correspond to the phase angle of a carrier wave, and these are collectively called angle modulation. To demodulate this angle modulated wave, a signal corresponding to the carrier wave (hereinafter referred to as "reference signal") is generated from the angle modulated wave, and the angle modulated wave and the reference signal are multiplied (phase comparison).
The phase difference component obtained is used as the detection output.

FIG. 14 is a block diagram showing the basic configuration of a differential detector used for demodulating such an angle modulated wave.

In the figure, the angle modulated wave is input to a delay circuit 81 and is delayed by one bit of data. The reference signal obtained by this delay is multiplied by the angle modulated wave input by the cosine phase comparator 83, and the obtained phase difference component is extracted as a detection output.

At this time, the conditions required of the delay circuit 81 are: (1) the delay time must correspond to approximately 1 bit of the transmission data; and (2) the delay time must be an integral multiple of the period of the carrier wave.

By the way, since it is not easy to manufacture a delay line having such a predetermined precision and suitable for integrated circuit implementation, a shift register is generally used as the delay circuit 81. In FIG. 14, reference number 85 is a clock generator that serves as an input clock for the shift register.

In a configuration using such a shift register, the delay time is determined by an integral multiple of the period of the input clock. That is, since one cycle of the input clock causes an error in the delay time, the clock cycle is set to be sufficiently smaller than the carrier wave cycle.

On the other hand, since the delay time is determined by the clock frequency and the number of stages of the shift register, if these cannot be varied, the frequency of the carrier wave that satisfies the conditions for differential detection must be fixed.

However, the frequency of the carrier wave may drift,
In that case, the detection characteristics deteriorate because the condition (2) for delayed detection described above is no longer satisfied (the condition (2) is almost satisfied for some changes in the carrier frequency). FIG. 15 shows error rate characteristics when the carrier frequency drifts from a predetermined frequency when the clock frequency and the number of stages of the shift register are fixed. The horizontal axis shows the amount of drift from a predetermined frequency, and the vertical axis shows the corresponding error rate.

In this way, the delay detector has the disadvantage that its characteristics deteriorate due to the drift of the carrier wave frequency.

Therefore, various circuits for correcting carrier frequency drift have been devised.

One method is to adjust the clock frequency and the number of shift stages of the shift register according to the frequency drift of the carrier wave. FIG. 16 shows an example of a circuit configuration that realizes this (Noh Nakamura, "Study of QPSK delayed detection demodulator for digital mobile communications", 1989, Institute of Electronics, Information and Communication Engineers Spring National Conference B-837).

In the figure, the angle modulated wave is delayed by a delay circuit 91, and the delayed angle modulated wave (reference signal) is input to a cosine phase comparator 921, and is also input to a cosine phase comparator 921 via a π/2 shift circuit 93. 922, each of which is multiplied by an angle modulated wave, and each of the obtained phase difference components is taken out as a delayed detection output.

In such a delay detector, the delay detection output is 4
The signal is inputted to a multiplier circuit 94 to remove modulation components, and passed through a loop filter 95 to obtain a phase difference output proportional to the drift of the carrier frequency. Furthermore, a control voltage corresponding to the obtained phase difference output is applied to a clock generator (voltage controlled oscillator) 96 that supplies clocks to the shift registers constituting the delay circuit 91 to control its clock frequency. In this way, the delay amount corresponding to the frequency drift of the carrier wave is obtained and corrected.

In this case, the loop filter output should be analog/
It is also possible to correct the delay amount by converting it into digital data and adjusting the number of stages of the shift register using the digital data.

[Invention or problem to be solved]

By the way, in the conventional carrier frequency drift compensation circuit shown in FIG. 16, information corresponding to the amount of carrier frequency drift is extracted as an analog signal and processed by a loop filter, voltage controlled oscillator, and other analog circuits. While essential, it was also unsuitable for digital integrated circuits.

In addition, even in a configuration in which the detection output is converted to analog/digital and drift correction is performed by digital signal processing, an analog/digital converter is required, making it difficult to reduce power consumption. It wasn't easy either.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency drift detection circuit that can simplify the circuit and reduce power consumption, and is suitable for no adjustment and complete digital integration.

[Means to solve the problem]

FIG. 1 is a block diagram showing the principle configuration of the present invention,
FIG. 2 is a block diagram in which the phase difference detection means has a different configuration.

The present invention provides a detector that generates a predetermined reference signal corresponding to a carrier wave from a received modulated wave and detects the modulated wave using this reference signal, in which the phase of the reference signal and the phase of the modulated wave are different. A phase difference detection means that detects a phase difference and outputs phase difference data; a phase difference distribution detection means that latches this phase difference data at each identification timing and detects the distribution state of the phase difference; and this phase difference distribution data. and a frequency drift detection means for calculating the amount of frequency drift of the carrier wave according to the frequency drift of the carrier wave.

Further, the phase difference detection means is replaced with a phase shift means for generating n-phase phase-shifted signals having the same frequency as the reference signal and different phases from each other, and comparing the phase of the n-phase phase-shifted signal and the modulated wave. However, it is configured as a phase latch means for detecting a phase difference between the phase of the reference signal and the phase of the modulated wave.

Furthermore, when the drift amount of the frequency drift of the carrier wave does not exceed a predetermined value within a predetermined time, means is provided for resetting the calculated drift amount by a timeout of a timer provided in the frequency drift detection means. ing.

[Effect]

A phase difference detection means generates n-phase phase shifted signals having the same frequency as the reference signal used for detection and different phases from each other,
The phase of each phase-shifted signal and the phase of the modulated wave are compared to detect the phase difference between the reference signal and the modulated wave.

When a frequency drift occurs in the carrier wave, the phase difference distribution of the modulated wave with respect to the reference signal changes, so this phase difference distribution is detected by the phase difference distribution detection means, and the frequency drift detection means performs predetermined arithmetic processing. Data proportional to the frequency drift of the carrier wave can be obtained from the distribution state.

Note that by feeding back data corresponding to this frequency drift to a circuit that can vary the frequency of the reference signal of the detector, it is possible to correct the frequency drift of the carrier wave, and stable detection operation can be performed.

Furthermore, by resetting the frequency drift data upon timeout using a timer circuit provided in the frequency drift detection means, it becomes possible to tolerate frequency errors within a certain range, and stable control of frequency drift compensation becomes possible.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the frequency drift detection circuit of the present invention. Note that similar effects can be obtained by constructing the phase difference detection means in this figure by the phase shift means and phase latch means according to claim 2.

In this embodiment, the angle modulated wave input to the input terminal 11 has already had amplitude fluctuations removed by a limiter circuit and other devices, and has been converted into a binary quantized digital signal (with a duty ratio of 50%). It is assumed that Therefore, the signal is input to the input terminal 11 as a phase-modulated signal.

Furthermore, a delay detection circuit is used as the detector 20.

In FIG. 3, the angle modulated wave input to the input terminal 11 is input to the detector 20, and is detected by the cosine phase comparator 23 using the reference signal obtained via the delay circuit 21, and the detected signal is is output to the output terminal 13.

The reference signal (phase C,) obtained by the wave detector 20 is input to the phase difference detection means 40. This phase difference detection means 40 is
A phase shift means consisting of a shift register 33 and a tarlock generator 31, and D flip-flops 411 to 41, for example.
It is constituted by phase latch means consisting of ffi. The reference signal is input to this phase shift means and converted into an n-phase (C, to C,) signal by a shift register 33 that performs a shift operation in accordance with a clock output from a clock generator 31. Note that this n-phase signal is, as described later,
This is a signal obtained by shifting the input angle modulated wave by 1/2n periods.

Each phase shift signal C to C0 output from the phase shift means is
n flip-flops 41 forming phase latch means
, ~41. ．． are supplied as each clock. On the other hand, the same angle modulated wave is input to each of the flip-flops 411 to 41, and is latched in accordance with each phase shift signal C1 to C, which is outputted from the phase shift means. Phase difference data D1 to D7 between the angle modulated wave and each phase shift signal outputted from each flip-flop 411 to 41fi is sent to phase difference distribution detection means 50.

The phase difference distribution detecting means 50 latches the input phase difference data D1 to D, . Each classification output obtained by the phase difference classification circuit 53 is
The data is sent to the corresponding counters 55 to 551 for counting processing.

Each counter 55. The output of ~55o is sent to frequency drift detection means 6o.

Next, the operation of each means will be explained.

The shift register 33 of the phase difference detection means 40 (phase shift means) divides the half period of the input reference signal into n equal parts by setting the phase of the input reference signal as 00, and generates phase shifted signals c1 to C, . If the eight-stage shift register 33 is used with =8, eight phase-shifted signals c1 to Cs obtained by shifting the half cycle of the reference signal by 22.5 (360/16) degrees can be obtained. By these phase shift signals 01 to c8, one period of the reference signal is divided into 16 phase regions ap as shown in FIG. 4(a).

Phase difference detection means 40 for 8 phase phase shifted signals C1 to C8
Then, the input angle modulated waves are latched by eight flip-flops 41+ to 41a, respectively.

Here, the modulation phase of the received angle modulated wave is shown in Fig. 4 (
As shown in a), phase shifted signals C3 and C4 with C6 as a reference.
(phase region d), and as shown in FIG. 4(b), the rising edge of the received angle modulated wave becomes the phase shifted signal C.
3 and C4, the phase difference data (D, C2...D,) output from each flip-flop 41 to 418 becomes (00011111). Since this phase difference data varies depending on the phase of the angle modulated wave, the phase difference between the angle modulated wave and the reference signal can be determined from this phase difference data.

In the phase difference distribution detection means 50, a latch circuit 51 latches each phase difference data output from the phase difference detection means 40 at each identification timing. The phase difference classification circuit 53 detects the position of the angle modulated wave in the phase region a-p based on the latch output. Here, it is assumed that a pulse is generated at a terminal indicating a phase region (d) in which the phase of the angle modulated wave is located, for example. Note that this phase difference classification circuit 53 can be easily configured with a simple sequential circuit. Each counter 551-55 corresponding to each phase region. (m=16) is
Each pulse output from the phase difference classification circuit 53 is counted in a predetermined period. With such a configuration,
It is possible to observe the distribution in which the phase of the angle modulated wave is detected in each phase region a-p. Here, if the angle modulated wave is a QPSK signal, for example, four phases (.) shown in FIG. 5 are detected at the identification timing. However, if a frequency drift occurs in the carrier wave of the angle modulated wave,
The detected phase shifts in the positive direction or in the negative direction.

For example, if a positive drift occurs, the detected phase (◎) shifts in the positive direction, and if a negative drift occurs, the detected phase (◎) shifts in the negative direction.

FIG. 6 shows an example of the output of the phase difference distribution detection means 50 when a negative frequency drift exists. The horizontal axis represents the phase region, and the vertical axis represents the number of times the angle modulated wave is detected, which is counted by a counter 55° to 55°.

However, in the case of a Q P S K signal, in order to degenerate the four modulation phases, for example, phase regions a, e, i, m
and the number of times the angle modulated wave is detected. In the figure, the dashed line is the distribution when there is no frequency drift, and its peaks are at C2 and C6 for the modulation phase or carrier half cycle, so the phase region b (f, L n) and the phase region C ( g, k, 0). On the other hand, the solid line shows the distribution when there is a negative frequency drift, and the phase of the angle modulated wave is shifted to the right from the detected region or the central phase region. Also, in the case of a positive frequency drift, it shifts to the left.

Next, an estimation method in which the frequency drift detection means 60 estimates the amount of frequency drift of the carrier wave based on the output of the phase difference distribution detection means 50 will be described.

Note that three methods will be described here.

[Method 1] FIG. 7 is a diagram showing the phase region (vertical axis) in which the number of times the angle modulated wave is detected is maximum relative to the drift frequency (horizontal axis). However, the phase regions were degenerated into four, a, b, c, and d. Therefore, the phase region a is the phase region e,
i and m, and the same applies to other phase regions.

As shown in FIG. 7, the output (
Counters 551-55. By detecting the maximum phase region from each output value), the magnitude of the frequency drift (±Δf) can be estimated. However, the smaller the size of the phase regions divided at this time, the smaller the frequency drift estimation error becomes.

Here, FIG. 8 shows an example of a circuit configuration for detecting a phase region in which the number of times the angle modulated wave is detected (each output of the phase difference distribution detection means 50) is maximum.

In the figure, a subtracter 611 takes the difference between the number of detections a of the first phase region a and the number of detections of the second phase region Select b). Next, the subtracter 612 and the multiplexer 63 . The difference between the output of
Select the larger data of and C. Next, subtractor 6
13, the difference between the output of the multiplexer 63□ and the number of detections d of the fourth phase region d is taken, and the multiplexer 633 selects the larger data of a, b or C and d according to the code data F2, and the final The detection number G of the phase region that has been detected most often is output.

Therefore, in this circuit configuration, each subtractor 61° to 61
3 code data (FO, Fl, F2), it is possible to detect which phase region has the maximum number of detections. In addition, in the configuration shown in the figure, if the input value of the upper stage of each subtracter 611 to 61s is larger than the input value of the lower stage, F1 = 0, and conversely, if the input value of the lower stage is large, F1 = 0. l=1
becomes.

Here, if (Fil, Fl, F2)=(110), then a<b, b<c, cod, and it can be seen that the number of detections in phase region C is maximum.

The distribution of phase difference with respect to frequency drift is determined by the delay circuit 21
Since the delay time can be known in advance by calculation using the delay time, data corresponding to the frequency drift can be created from data in the phase region where the number of detections (count value) is maximum.

Note that the data obtained here can be used, for example, to control the amount of delay of the delay circuit 21 in the detector 20, thereby correcting the frequency drift of the carrier wave.

On the other hand, if the configuration is such that a reference signal is supplied from the outside and the angle modulated wave is detected using that reference signal, it is possible to similarly correct for the frequency drift of the carrier wave by directly controlling the frequency of the reference signal. .

[Method 2] FIG. 9 is a diagram showing the number of times angle modulated waves are detected in a designated phase region (vertical axis) with respect to the drift frequency (horizontal axis).

By observing the number of detections of angle modulated waves in a designated phase region, the amount of frequency drift can be estimated from previously measured data. Note that the conversion circuit from the number of detections to the amount of frequency drift can be easily configured using a memory that stores measured data.

[Method 3] Figure 1O shows the difference in the number of detections of angle modulated waves in two specified phase regions (
(vertical axis). Note that the two phase regions include phase regions on both sides of the modulation phase (for example, phase region C).

As shown in the figure, by observing the positive and negative signs of the difference in the number of detections, the direction of the frequency drift, that is, the polarity of the drift can be detected.

By the way, although this method does not directly estimate the amount of frequency drift, for example, the delay circuit 21 in the detector 20
If the delay amount is changed little by little in the direction of correcting the frequency drift based on this data, it is possible to almost converge to a constant delay amount with the frequency drift corrected. Note that the correction error at this time depends on the width of the delay amount to be changed.

Also, in this method, if a reference signal is supplied from the outside and the angle modulated wave is detected using the reference signal, the frequency of the reference signal is directly changed little by little in the direction that corrects the frequency drift of the carrier wave. control.

Note that the configuration for compensating for frequency drift of the carrier wave (frequency error between the carrier wave of the modulated signal and the reference signal) and enabling stable detection operation was published in October 1989 by the same applicant.
It is described in detail in the specification (Japanese Patent Application No. 1-275662, Digital Demodulator) filed on May 23rd.

FIG. 11 is a block diagram showing the configuration of a second embodiment of the frequency drift detection circuit of the present invention. It should be noted that the phase difference detection means 40 can be configured by the phase shift means and phase latch means according to the second aspect of the present invention, and similar effects can be obtained.

Note that in this embodiment, the configurations of the detector 20 and the phase difference detection means 40 are common to each of the first embodiments shown in FIG. 3, and a description thereof will be omitted here. In the figure, a phase difference determination circuit 57 in the phase difference distribution detecting means 50' determines whether the rising edge of the angle modulated wave is determined based on the phase difference data between the angle modulated wave and the reference signal output from the phase difference detecting means 40. It is determined whether the wave exists in the phase region α or β shown in FIG. 13 (however, the angle modulated wave is assumed to be a QPSK signal).

Note that this phase difference determination circuit 57 is similar to the phase difference classification circuit 53.
can be constructed using a simple sequential circuit.

Here, if there is no frequency drift of the carrier wave, the time the angle modulated wave spends in the phase region α and the time it spends in the phase region β are almost equal, so by comparing these, the frequency drift can be reduced. The direction (positive or negative) can be determined.

Frequency drift detection means 60 that performs such determination processing
1 is composed of an up/down counter 65, a clock generator 67 that supplies a clock to the up/down counter 65, and a count detection circuit 69 that detects the number of counts in the up/down counter 65.

The up/down counter 65 up-counts the clock output from the clock generator 67 when the phase of the angle modulated wave stays in the phase region α according to the output of the phase difference determination circuit 57, When staying in area β, the clock is counted down. The count number detection circuit 69 monitors the count number of the up/down counter 65, and when each count number in the up direction or down direction exceeds a predetermined value, the count number detection circuit 69 outputs the corresponding output terminals 710.
A detection pulse is sent to 71o. From this detection pulse, it is possible to determine whether the frequency drift is positive or negative (direction).

On the other hand, as shown in FIG.
When counting the clock output from the clock generator 67, the timer circuit 100 simultaneously starts counting the clock. At this time, if the count number of the timer circuit 100 reaches a preset value in the timer circuit before the count number of the up-down counter 65 exceeds the predetermined value of the count number detection circuit 69, the timer circuit starts the up-down counter 65. Reset and re-count. In this case, the output terminals 71U, 71. No detection pulse is sent. By inserting the timer circuit 100 in this manner, it becomes possible to tolerate frequency errors within a certain range, and stable control of frequency drift compensation becomes possible. This method of allowing a frequency error within a certain range by inserting a timer circuit is also applicable to Method 1 and Method 2 described above. That is, this is possible by outputting the drift amount when the frequency drift amount exceeds a required value within a value set in advance in the timer circuit, and not performing drift control when the frequency drift amount does not exceed the required value.

For example, if the delay amount of the delay circuit 21 in the detector 20 is changed little by little in the direction of correcting the frequency drift based on this data, it will almost converge to a constant delay amount with the frequency drift corrected. I can do it. Note that the correction error at this time depends on the width of the delay amount to be changed.

Furthermore, if a reference signal is supplied from the outside and the angle modulated wave is detected using the reference signal, control is performed to directly change the frequency of the reference signal little by little in a direction that corrects the frequency drift of the carrier wave.

The phase difference detection means 40 and phase difference distribution detection means 5 shown above
0.50' and frequency drift detection means 60.60'
can be constructed as a digital circuit,
It is possible to obtain frequency drift information by digital signal processing.

In addition, in the embodiments described above, the frequency drift detector suitable for angle-modulated waves in which the frequency drift of the carrier wave has a large influence on its detection has been described, or the frequency drift detection circuit of the present invention depends on the modulation method. It's not a thing.

〔Effect of the invention〕

As mentioned above, the frequency drift detection circuit of the present invention has the following features:
It is configured to detect the phase difference between the modulated wave and the reference signal through digital processing, and obtain data proportional to the frequency drift of the carrier wave from the distribution of the phase difference, and can be realized entirely by digital circuits. That is, analog parts are no longer required, and only the fixed oscillator that serves as the clock for the phase shift means and frequency drift detection means is externally connected, and the rest can be realized as a complete one-chip digital integrated circuit. In the past, it became possible to eliminate adjustment and reduce power consumption, which led to lower costs.

Note that the data obtained by the frequency drift detection circuit of the present invention can be fed back to a circuit that can vary the frequency of the reference signal of the detector to correct the frequency drift of the carrier wave, achieving stable detection operation. It becomes possible to do so.

Furthermore, by configuring a feedback loop connected to a circuit that can vary the frequency of the reference signal using this data, it is possible to always perform correction even when the frequency drift of the carrier wave changes over time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle configuration of a frequency drift detection circuit according to claim 1. FIG. 2 is a block diagram showing the principle configuration of the frequency drift detection circuit according to claim 2. FIG. 3 is a block diagram showing the configuration of the first embodiment of the present invention. FIG. 4 is a diagram explaining the operation of the phase difference detection means. FIG. 5 is a diagram explaining frequency drift. FIG. 6 is a diagram showing an output example (phase difference distribution state) of the phase difference distribution detection means when a negative frequency drift exists. FIG. 7 is a diagram showing a phase region where the number of times an angle modulated wave is detected is maximum with respect to a drift frequency. FIG. 8 is a block diagram showing a circuit configuration for detecting a phase region where the number of detections of an angle modulated wave is maximum. FIG. 9 is a diagram showing the number of times angle modulated waves are detected in a phase region specified with respect to a drift frequency. FIG. 1O is a diagram showing the difference in the number of detections of angle modulated waves in two specified phase regions with respect to the drift frequency. FIG. 11 is a block diagram showing the configuration of a second embodiment of the frequency drift detection circuit of the present invention. FIG. 12 is a block diagram showing an embodiment of the frequency drift detection circuit according to claim 3. FIG. 13 is a diagram explaining the operation of the phase difference determination circuit. FIG. 14 is a block diagram showing the basic configuration of a delay detector. FIG. 15 is a diagram showing error rate characteristics due to carrier wave frequency drift. FIG. 16 is a block diagram showing the configuration of a conventional carrier frequency drift compensation circuit. 11...Input terminal, 13...Output terminal, 20...
Detector, 21...Delay circuit, 23...Cosine phase comparator, 31...Clock generator, 33...Shift register, 40...Phase difference detection means, 41...Free knob flow - Knob, 50.50'... Phase difference distribution detection means, 51... Latch circuit, 53... Phase difference classification circuit,
55... Counter, 57... Phase difference determination circuit, 60
．． 60'... Frequency drift detection means, 61... Subtractor, 63... Multiplexer, 65... Up/down counter, 67... Clock generator, 69...
Counter number detection circuit, 81...delay circuit, 83...
Cosine phase comparator, 85...Clock generator, 91...
・Delay circuit, 92...Cosine phase comparator, 93...π
/2 shift circuit, 94...4 multiplier circuit, 95...loop filter, 96...clock generator (voltage controlled oscillator), 100...timer circuit Fig. 1 Fig. 2 Angle modulated wave (a ) (b) Figure 4 Figure 5 Figure 6 Figure 7 - Δf 0 + Δr Frequency drift Figure 9 - Δf + Δf Frequency drift Figure 1 0

Claims (3)

[Claims] (1) In a detector that generates a predetermined reference signal corresponding to a carrier wave from a received modulated wave and detects the modulated wave using this reference signal, a phase difference between the phase of the reference signal and the phase of the modulated wave is determined. a phase difference detection means for detecting a phase difference and outputting phase difference data; a phase difference distribution detection means for latching this phase difference data at each identification timing and detecting a distribution state of the phase difference; and this phase difference distribution data. A frequency drift detection circuit comprising: frequency drift detection means for calculating a drift amount or a drift direction of the frequency drift of the carrier wave according to the frequency drift of the carrier wave. (2) A detector that generates a predetermined reference signal corresponding to a carrier wave from a received modulated wave and detects the modulated wave using this reference signal, which has the same frequency as the reference signal and different phases. a phase shifter that generates a phase-shifted signal; and a phase latch that compares the n-phase phase-shifted signal with the phase of the modulated wave and detects a phase difference between the phase of the reference signal and the modulated wave. means for detecting a distribution of the phase difference by latching the phase difference data at each identification timing; and detecting the amount or direction of the frequency drift of the carrier wave according to the phase difference distribution data A frequency drift detection circuit comprising: a frequency drift detection means for calculating . (3) The frequency drift detection means according to claim 1 or 2 outputs the amount of drift or its polarity only when the amount of frequency drift exceeds a predetermined amount within a predetermined time. 3. The frequency drift detection circuit according to claim 1, further comprising means for controlling.