JPH03219958A - Video data control circuit - Google Patents

Abstract

PURPOSE:To perform the printing of a bold face at high speed without applying a burden to a firmware by including a second latch having a capacity for one line of video data for latching a signal from a parallel/serial conversion part on a second latch clock delayed a fixed time from a first latch clock and an OR gate inputting signals from the first and second latches. CONSTITUTION:When printing data is developed from a CPU1 to an FB 2 to be printed in a boldface, a signal C is turned ON ('1'), and the printing data is read from the FB 2 and converted to serial data by a parallel/serial conversion part 3. The serial data is latched in a latch 4 on a latch clock (a). After a fixed time delay, the same data is latched in a latch 5 on a latch clock (b). When the data for one line are stored each in the latches 4, 5 the data in the latches 4, 5 are read by the CPU 1. The data in the latch 4 is ORed with the data in the latch 5 by an OR gate 7, whereby video data (d) in a bold face is generated. In the case of normal printing, the signal C is turned OFF ('0'), all 0 are latched in the latches, and normal video data (d) is generat ed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video data control circuit, and more particularly to realizing bold font printing by a video data sending method in an electrophotographic printer.

[Conventional technology]

In the video data control circuit of a conventional electrophotographic printer, there is only one latch that latches one line of video data.
I only had one, so I printed it in bold font.
This was achieved by editing the U's firmware.

[Problem to be solved by the invention]

In the video data control circuit of the conventional electrophotographic printer described above, printing in bold fonts is achieved through editing processing of the firmware of the CPU, which has the disadvantage of placing a burden on the firmware and requiring additional editing time. There is.

[Means to solve the problem]

The video data control circuit of the present invention includes a frame buffer, a parallel/serial converter connected to the frame buffer, and one video data line that latches a signal from the parallel/serial converter using a first latch clock. and a second latch clock that is delayed by a certain period of time from the first latch clock to transmit the signal from the parallel/serial converter.
Video data 1 latched by the latch clock of
It has a second latch for the line, and an OR gate that inputs signals from the first and second latches.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the printing result of bold font printing in this embodiment.

1 is a CPU, 2 is a frame buffer (hereinafter abbreviated as FB), and 3 is a parallel/serial converter.

4 and 5 are latches for latching one line of video data, 6 is an AND gate, 7 is an OR gate, a and b are latch clocks for latching video data (however, a and b are ), C is a signal that turns the latch 5 ON10FF, and d is video data to be printed.

First, when printing the print data in bold font by expanding it to FB2 by CPU, turn signal C ON<'1''), read the print data from FB2, serially convert it by parallel/serial converter 3, and latch it. Latch 4 is latched by clock a, and after a certain time delay, the same data is latched by latch clock b.When data for one line has accumulated in latches 4 and 5, latches 4 and 5 are latched by the CPU. The data is read out from , and the data in latch 4 and the data in latch 5 are logically summed by OR gate 7 to generate video data d in bold typeface.In the case of normal printing,
By setting the signal C to 0FF (“0°’>), all 0s are latched in the latch 5, and normal video data d
is generated.

〔Effect of the invention〕

As explained above, the present invention has the effect of allowing bold font printing to be performed at higher speed without imposing any burden on firmware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing the printing results of bold font printing of this embodiment. 1...CPU, 2...Frame buffer, 3...
・Parallel/serial converter, 4, 5...Latch, 6
・・・AND gate, 7-OR gate, a-b latch・
Clock, d...video data. Figure 1

Claims (1)

[Claims] a frame buffer, a parallel/serial converter connected to the frame buffer, and a first latch for one line of video data that latches a signal from the parallel/serial converter using a first latch clock;
A second latch clock for one line of video data that latches the signal from the parallel/serial converter using a second latch clock delayed by a certain period of time from the first latch clock.
A video data control circuit comprising: a latch; and an OR gate inputting signals from the first and second latches.