JPH03220462A - Reference voltage setting circuit - Google Patents

Reference voltage setting circuit

Info

Publication number
JPH03220462A
JPH03220462A JP1591890A JP1591890A JPH03220462A JP H03220462 A JPH03220462 A JP H03220462A JP 1591890 A JP1591890 A JP 1591890A JP 1591890 A JP1591890 A JP 1591890A JP H03220462 A JPH03220462 A JP H03220462A
Authority
JP
Japan
Prior art keywords
reference voltage
voltage
terminal
lsi
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1591890A
Other languages
Japanese (ja)
Inventor
Shuichi Kameyama
修一 亀山
Hidemitsu Saito
斉藤 秀光
Takehiro Kudou
工藤 健宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1591890A priority Critical patent/JPH03220462A/en
Publication of JPH03220462A publication Critical patent/JPH03220462A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable the setting of a reference voltage handily and safely by connecting a variable resistance and an internal power source within an LSI between a reference voltage applying terminal and the ground. CONSTITUTION:When resistance elements 14-1, 14-2... are made the same in resistance value, a level of a reference voltage to be applied to comparators 3-1, 3-2... is set for a microprocessor 17 beforehand. At first, an internal power source 8 is connected to a terminal 9 without driving relay contacts 15-1, 15-2.... A voltage of the terminal 9 is measured by a voltage measuring means 16 to be informed to the microprocessor 17 to judge. Then, when some of the relay contacts 15-1, 15-2... are driven, the voltage of the terminal 9 can be set to a specified value easily. Then, when resistance values of the elements 14-1, 14-2... are set so that they become binary therebetween beforehand, the resistance value is given by R1=R2/2=R3/4=... = Rn/2<n-1>. In this case, a change in voltage of the terminal 9 can be made easy to be linear thereby facilitating the changing of a reference voltage to a set value.

Description

【発明の詳細な説明】 [概要コ 論理回路などを含み動作試験のされるLSIに印加する
参照電圧を設定する参照電圧設定回路に関し、 スキャン処理によりLSIを順次に試験するとき、簡易
、安全に参照電圧を設定できる参照電圧設定回路を提供
することを目的とし、 被試験電圧端子と、参照電圧印加端子とに接続され、両
端子の電圧の大小を比較するコンパレータを具備し、該
コンパレータの出力をスキャンアウト信号端子から取り
出すことにより、論理回路を含むLSIの被試験電圧端
子に現れる電圧をチェックする機能を有するLSIの参
照電圧設定回路において、参照電圧印加端子と接地との
間に接続された可変抵抗及びLSI内の内部電源とを具
備することで構成する。
[Detailed Description of the Invention] [Summary] This invention relates to a reference voltage setting circuit that sets a reference voltage to be applied to an LSI that includes a logic circuit and the like and is subjected to an operation test. The purpose of this circuit is to provide a reference voltage setting circuit that can set a reference voltage, and includes a comparator connected to a voltage under test terminal and a reference voltage application terminal to compare the magnitude of the voltage at both terminals, and the output of the comparator In an LSI reference voltage setting circuit that has the function of checking the voltage appearing at the voltage terminal under test of an LSI including a logic circuit by taking it out from the scan-out signal terminal, the It is constructed by comprising a variable resistor and an internal power supply within the LSI.

[産業上の利用分野コ 論理回路などを含み動作試験のされるLSIに印加する
参照電圧を設定する参照電圧設定回路に関する。
[Industrial Application Field] This invention relates to a reference voltage setting circuit that sets a reference voltage to be applied to an LSI including a logic circuit and the like, which is subjected to an operation test.

論理回路などで構成されるプリント基板上のLSIをス
キャン処理により順次に試験するとき、LSIの動作測
定のため直流参照電圧を外部から印加する必要がある。
When testing LSIs on a printed circuit board, which are comprised of logic circuits and the like, sequentially through a scanning process, it is necessary to externally apply a DC reference voltage to measure the operation of the LSIs.

その参照電圧は外部直流電源を使用していたから、誤操
作や故障のとき高電圧をLSIに印加して、基板上の全
部のLSIを破壊することがあった。そのためLSIを
破壊させない安全な参照電圧印加用の電源装置を開発す
ることが要望された。
Since the reference voltage used an external DC power supply, in the event of an erroneous operation or failure, a high voltage would be applied to the LSI, potentially destroying all the LSIs on the board. Therefore, it has been desired to develop a power supply device for applying a safe reference voltage that will not destroy the LSI.

[従来の技術] プリント基板に搭載され、論理回路などを含んで構成さ
れるLSIについて、動作試験を行い、スキャン処理に
より順次にチェックしている。このとき、通常は機能試
験とネット試験を行う。複数のLSIを搭載した基板同
士のコネクタ端子から、所定の入力信号を与え、入力信
号に応した期待値が各LSIの出力端子から得られてい
るかどうかを調べて、各LSIの機能試験を行う。即ち
、LSIに印加する端子電圧が成る基準値より上である
か下であるかによって、当該LSIの出力値“1”0”
の判定を行い。その論理が期待値と一致しているかどう
かを判定する。
[Prior Art] Operation tests are performed on LSIs that are mounted on printed circuit boards and are configured to include logic circuits and the like, and are sequentially checked by scanning processing. At this time, a functional test and a network test are usually performed. Perform a functional test on each LSI by applying a predetermined input signal to the connector terminals between boards equipped with multiple LSIs and checking whether the expected value corresponding to the input signal is obtained from the output terminals of each LSI. . In other words, depending on whether the terminal voltage applied to the LSI is above or below the reference value, the output value of the LSI will be "1" or "0".
Make a judgment. Determine whether the logic matches the expected value.

またネット試験とは基板上に配置された前段LSIの出
力端子と、後段LSIの入力端子とを結合している配線
について試験する。配線の両端電圧をそれぞれ比較器で
、参照電圧と比較して配線両端間に生じた電圧降下の大
小により配線が適正かどうかを8周べることである。
In addition, the net test tests the wiring that connects the output terminal of the preceding stage LSI and the input terminal of the succeeding stage LSI arranged on the board. The voltage at both ends of the wiring is compared with a reference voltage using a comparator, and the accuracy of the wiring is determined eight times based on the magnitude of the voltage drop that occurs between the two ends of the wiring.

第3図は参照電圧の設定回路を示す。前記試験のため参
照電圧との比較用に、コンバータを使用するが、そのコ
ンパレータの一方の端子に参照電圧を与えるため、8−
1は例えば−1,3■の直流電源、8−2は抵抗素子を
示し、この部分は内部電源である。また10は電圧が可
変にできる外部直流電源を示している。参照電圧印加端
子9を開放とすれば、参照電圧Vrは−1,3■に固定
された値となる。参照電圧印加端子9を電源10と接続
するときは、端子9の電圧は電源10の電圧と等しくな
る。そのため外部直流型SIOの値により参照電圧を任
意の値に調整できる。
FIG. 3 shows a reference voltage setting circuit. A converter is used for comparison with the reference voltage for the above test, and in order to apply the reference voltage to one terminal of the comparator, 8-
Reference numeral 1 indicates, for example, a -1,3■ DC power supply, and reference numeral 8-2 indicates a resistor element, which is an internal power supply. Further, numeral 10 indicates an external DC power source whose voltage can be varied. If the reference voltage application terminal 9 is left open, the reference voltage Vr will be a fixed value of -1.3. When the reference voltage application terminal 9 is connected to the power supply 10, the voltage of the terminal 9 becomes equal to the voltage of the power supply 10. Therefore, the reference voltage can be adjusted to any value by the value of the external DC type SIO.

[発明が解決しようとする課題] 第3図の回路により各コンパレータの参照電圧側端子に
参照電圧Vrを印加している。そしてLSIのチップは
プリント板に多数並置され、共通の参照電圧印加端子9
を使用して多数のLSIに必要な参照電圧を与えている
。そのため第3図の直流型a10の故障またはオペレー
タに誤操作があると、端子9に外部直流電源10の異常
な高電圧が直接印加されるということが発生する。その
ときLSIは全てが一瞬のうちに破壊されるという危険
性を有している。
[Problems to be Solved by the Invention] The circuit shown in FIG. 3 applies a reference voltage Vr to the reference voltage side terminal of each comparator. A large number of LSI chips are arranged side by side on a printed board, and a common reference voltage application terminal 9 is used.
is used to provide the necessary reference voltage to a large number of LSIs. Therefore, if the DC type a10 shown in FIG. At that time, there is a risk that the entire LSI will be destroyed in an instant.

本発明の目的は前述の欠点を改善し、スキャン処理によ
りLSIを順次に試験するとき、簡易、安全に参照電圧
を設定できるようにした参照電圧設定回路を提供するこ
とにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a reference voltage setting circuit which can overcome the above-mentioned drawbacks and easily and safely set a reference voltage when sequentially testing LSIs through scan processing.

[課題を解決するための手段] 第1図は本発明の原理構成としてLSIのネット試験を
行う場合の、後段側LSIを示す図である。第1図にお
いて、1はLSI、2は論理回路、3−1.3−2−−
−はコンパレータ、4はスキャン制御回路、5はスキャ
ン制御回路の制御用信号端子、6はスキャンアウト信号
端子、9は参照電圧印加端子、8は内部電源(内部抵抗
Ri)、12は可変抵抗(例えばRe)、13は接地を
示している。
[Means for Solving the Problems] FIG. 1 is a diagram showing a rear-stage LSI when conducting a net test of an LSI as the principle configuration of the present invention. In Figure 1, 1 is an LSI, 2 is a logic circuit, 3-1.3-2--
- is a comparator, 4 is a scan control circuit, 5 is a control signal terminal for the scan control circuit, 6 is a scan out signal terminal, 9 is a reference voltage application terminal, 8 is an internal power supply (internal resistance Ri), 12 is a variable resistor ( For example, Re), 13 indicates grounding.

被試験電圧端子11−1.11−2− と、参照電圧印
加端子9とに接続され、両端子の電圧の大小を比較する
コンパレータ3−L3−2−を具備し、該コンパレータ
3−1.3−2−の出力をスキャンアウト信号端子6か
ら取り出すことにより、論理回路2を含むLSIの被試
験電圧端子11−1.11−2−に現れる電圧をチェッ
クする機能を有するLSIの参照電圧設定回路において
、本発明は下記の構成としている。即ち、 参照電圧印加端子9と接地13との間に接続された可変
抵抗12とり、SI内の内部電源8とを具備することで
構成される。
A comparator 3-L3-2- is connected to the voltage terminal under test 11-1. Reference voltage setting for an LSI having a function of checking the voltage appearing at the voltage terminal under test 11-1.11-2- of the LSI including the logic circuit 2 by taking out the output of 3-2- from the scan-out signal terminal 6 The circuit of the present invention has the following configuration. That is, it includes a variable resistor 12 connected between the reference voltage application terminal 9 and the ground 13, and an internal power supply 8 within the SI.

[作用] 第1図に図示しない前段LSIの出力電圧が、被試験電
圧端子1l−Lll−2−に現れたとき、その電圧を参
照電圧印加端子9の電圧とを対応するコンパレータ3−
1.3−2−で比較する。端子11の電圧が参照電圧よ
り小さいとき、各コンパレータ3の出力は“0”、大き
いとき出力は“1”となる。
[Function] When the output voltage of the preceding stage LSI (not shown in FIG. 1) appears at the voltage under test terminal 1l-Lll-2-, that voltage is connected to the voltage of the reference voltage application terminal 9 by the corresponding comparator 3-.
Compare 1.3-2-. When the voltage at the terminal 11 is smaller than the reference voltage, the output of each comparator 3 is "0", and when it is larger, the output is "1".

スキャン制御回路の制御用信号端子5に印加される信号
は、被試験電圧端子11と関連してコンパレータ3の出
力をスキャンアウト信号端子に出力すべく印加する。そ
のためスキャンアウト信号端子6から、“1”または“
0”を得て、前段LSIとの間の配線について良否を判
定できる。またコンパレータ3との結線を変更して機能
試験を行えば、論理回路2について良否を判定できる。
A signal applied to the control signal terminal 5 of the scan control circuit is applied in order to output the output of the comparator 3 to the scan out signal terminal in relation to the voltage terminal under test 11. Therefore, from scan out signal terminal 6, “1” or “
0'', it is possible to judge whether the wiring between the circuit and the previous stage LSI is good or bad.Furthermore, by changing the connection with the comparator 3 and performing a functional test, it is possible to judge whether the logic circuit 2 is good or bad.

この時、参照電圧印加端子9の電圧は内部電源8の電圧
を抵抗分割したものである。即ち、内部電源マの内部抵
抗Riと外部抵抗Reとの比で定まる。
At this time, the voltage of the reference voltage application terminal 9 is obtained by dividing the voltage of the internal power supply 8 by resistance. That is, it is determined by the ratio between the internal resistance Ri of the internal power source and the external resistance Re.

ReをO−■まで変化させることにより、参照電圧印加
端子9の電圧はOVから電源8からの電圧例えば1.3
vまで可変に出来る。外部抵抗12には高圧の電源を具
備しないから、LSIが破壊される危険性はなくなった
By changing Re to O-■, the voltage at the reference voltage application terminal 9 changes from OV to the voltage from the power supply 8, for example 1.3.
It can be varied up to v. Since the external resistor 12 is not equipped with a high-voltage power source, there is no risk of the LSI being destroyed.

[実施例] 第2図は本発明の実施例として、第1図の可変抵抗12
について具体的な構成を示す図である。
[Embodiment] FIG. 2 shows an example of the present invention in which the variable resistor 12 of FIG.
FIG.

第2図において、14−1.14−2− は抵抗素子、
15−1゜15−2−−はリレー接点、16は電圧測定
手段、17はマイクロプロセッサのような制御手段を示
す。
In Fig. 2, 14-1.14-2- is a resistance element;
Reference numerals 15-1 and 15-2 indicate relay contacts, 16 a voltage measuring means, and 17 a control means such as a microprocessor.

なお制御手段17はLSIの試験を行うためのLSlテ
スタの中央処理装置と兼用すると有効である。抵抗素子
14−Li2−2−  を同一抵抗値とした場合、コン
パレータ3−L3−2−・に印加すべき参照電圧の大き
さを予めマイクロプロセ・ノサ17に設定して置き、当
初はリレー接点15−1.15−2−を駆動することな
く、内部電源8を端子9と接続する。
Note that it is effective to use the control means 17 also as the central processing unit of an LSI tester for testing LSI. When the resistance element 14-Li2-2- is set to the same resistance value, the magnitude of the reference voltage to be applied to the comparator 3-L3-2- is set in advance in the microprocessor 17, and initially the relay contact The internal power supply 8 is connected to the terminal 9 without driving the terminals 15-1 and 15-2-.

電圧測定手段16により端子9の電圧を測定してマイク
ロプロセッサ17に通知し、マイクロプロセ、す17が
判断する。そしてリレー接点15−Li2−2−の幾つ
かを駆動すれば、端子9の電圧が所定値に容易に設定す
ることが出来る。
The voltage at the terminal 9 is measured by the voltage measuring means 16 and notified to the microprocessor 17, which then makes a determination. By driving some of the relay contacts 15-Li2-2-, the voltage at the terminal 9 can be easily set to a predetermined value.

次に抵抗素子14−1.14−2・・・・・の抵抗値を
互いにバイナリとなるように設定しておくと、抵抗値は
R1=R2/  2  =R3/  4 −−−=Rn
/  2 I′I−直となり、この場合は端子9の電圧
変化を直線的にすることが容易に出来る。したがって参
照電圧の設定値変化が容易に出来る。
Next, if the resistance values of the resistance elements 14-1, 14-2, etc. are set to be binary, the resistance values are R1=R2/2=R3/4---=Rn
/2I'I-direct, and in this case, the voltage change at the terminal 9 can be easily made linear. Therefore, the set value of the reference voltage can be easily changed.

[発明の効果〕 このようにして本発明によると、コンパレータに印加す
る参照電圧を抵抗のような受動素子のみで設定できるか
ら、電圧制御部において故障や誤操作があっても、プリ
ント基板に搭載されたLSIを破壊することがない効果
を有する。
[Effects of the Invention] In this way, according to the present invention, the reference voltage applied to the comparator can be set using only passive elements such as resistors. This has the effect of not destroying the LSI.

1−・LSI 2−・論理回路 3−L3−2−−コンパレータ 6−・スキャンアウト信号端子 8・・・内部電源 9−・・参照電圧印加端子 11−1.IL2−・被試験電圧端子 12−可変抵抗 13−接地1-・LSI 2-・Logic circuit 3-L3-2--Comparator 6-・Scan out signal terminal 8...Internal power supply 9--Reference voltage application terminal 11-1. IL2-・Voltage under test terminal 12-variable resistor 13-Grounding

Claims (1)

【特許請求の範囲】 I 、被試験電圧端子(11−1)(11−2)・・・
・・と、参照電圧印加端子(9)とに接続され、両端子
の電圧の大小を比較するコンパレータ(3−1)(3−
2)・・・・・を具備し、該コンパレータ(3−1)(
3−2)・・・・・の出力をスキャンアウト信号端子(
6)から取り出すことにより、論理回路(2)を含むL
SI(1)の被試験電圧端子(11−1)(11−2)
・・・・・に現れる電圧をチェックする機能を有するL
SIの参照電圧設定回路において、 参照電圧印加端子(9)と接地(13)との間に接続さ
れた可変抵抗(12)とLSI(1)内の内部電源(8
)とを具備することを特徴とする参照電圧設定回路。 II、請求項第1項記載の可変抵抗として、抵抗・リレー
の直列回路を複数組並列接続し、該直列回路の両端に接
続した電圧測定器の測定値をマイクロプロセッサに印加
し、該マイクロプロセッサは、前記直列回路の両端の電
圧が所望値となるように前記リレーの接点のメーク位置
を制御することを特徴とする参照電圧設定回路。
[Claims] I, voltage terminal under test (11-1) (11-2)...
... and a reference voltage application terminal (9), and a comparator (3-1) (3-
2)..., the comparator (3-1) (
3-2) Connect the output of... to the scan out signal terminal (
6), L containing the logic circuit (2)
Test voltage terminals (11-1) (11-2) of SI (1)
L that has the function of checking the voltage appearing on...
In the SI reference voltage setting circuit, the variable resistor (12) connected between the reference voltage application terminal (9) and the ground (13) and the internal power supply (8) in the LSI (1)
) A reference voltage setting circuit comprising: II. As the variable resistor according to claim 1, a plurality of series circuits of resistors and relays are connected in parallel, and a measured value of a voltage measuring device connected to both ends of the series circuit is applied to a microprocessor. The reference voltage setting circuit is characterized in that the make position of the contact of the relay is controlled so that the voltage at both ends of the series circuit becomes a desired value.
JP1591890A 1990-01-25 1990-01-25 Reference voltage setting circuit Pending JPH03220462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1591890A JPH03220462A (en) 1990-01-25 1990-01-25 Reference voltage setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1591890A JPH03220462A (en) 1990-01-25 1990-01-25 Reference voltage setting circuit

Publications (1)

Publication Number Publication Date
JPH03220462A true JPH03220462A (en) 1991-09-27

Family

ID=11902160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1591890A Pending JPH03220462A (en) 1990-01-25 1990-01-25 Reference voltage setting circuit

Country Status (1)

Country Link
JP (1) JPH03220462A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014027593A (en) * 2012-07-30 2014-02-06 Fujitsu Ltd Determination circuit and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014027593A (en) * 2012-07-30 2014-02-06 Fujitsu Ltd Determination circuit and semiconductor device

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