JPH0322048A - Address generating circuit and signal processing processor using this circuit - Google Patents

Abstract

PURPOSE:To increase the signal processing speed by using a second register, a second selector, an address increment means, and a third selector to generate a private address for packet data transfer. CONSTITUTION:A second register 160 holds an address signal for packet transfer data and outputs this address signal as a second address signal S200 synchronous ly with a latch clock signal 1.S160. An address increment means 150 adds one to the value of the second address signal S200, and a second selector 140 selects the addition result and a prescribed address signal, and the selection result is outputted to a second register 160. A third selector 170 selects a first address signal S100 or the second address signal S200. Thus, the signal processing speed is increased.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention generates addresses of random access memory (hereinafter simply referred to as RAM) used in digital signal processing processors such as semiconductor integrated circuits. The present invention relates to an address generation circuit and a signal processing processor using the same.

(Prior Art) Conventionally, there have been the following technologies in this field. The structure will be explained below using diagrams.

FIG. 2 is a configuration block diagram showing an example of a conventional signal processing processor.

This signal processor is used for packet communication in which a long message is sent and received by dividing it into several parts.

It has an A/D converter 1 that converts an analog audio input signal DI into a digital signal, and the A/D converter 1 is connected to a digital signal processing section (hereinafter referred to as DSP) 2.

In addition to a memory section consisting of an address generation circuit, RAM, etc., the DSP2 has an arithmetic logic unit (hereinafter referred to as ALU),
It consists of an arithmetic section consisting of a multiplier, registers, etc., and a control section. The output of this DSP 2 is connected to a switching line network (not shown) via a transmitting unit 3 consisting of a packet transmitting serial buffer, and the packet signal from this switching line network is connected via a receiving unit 4 consisting of a packet receiving serial buffer. and is connected to DSP2.

Further, the DSP 2 is connected to an analog audio output signal AO via a D/A converter 5.

FIG. 3 is a block diagram of the address generation circuit shown in FIG. 2.

This address generation circuit is a circuit that generates a RAM address, and is a circuit that generates an address signal S1 and an address change signal S2.
It has an adder 2a that adds the. The adder 2a
An output signal S3 is connected to the input side of the selector 2b, together with an address initial value signal S4 that determines the initial value of the address. The selector 2b is a circuit that selects the signal S4 and the output signal S3 of the adder 2b in accordance with the control signal S5, and its output side is connected to the register 2c. The register 2C is a circuit that stores the output of the selector 2b based on the synchronization of the latch clock signal S6, and the output of the register 2c is connected to the address signal SL.

The signal processing processor configured as described above operates as follows.

When the analog audio input signal DI is input to the A/D converter 1, it is converted into a digital signal by the A/D converter 1 and input to the DSP 2. The DSP 2 not only removes mixed noise and determines the presence or absence of voice, but also converts the digital voice signal into a packet data format and stores the data format in the built-in RAM.

When a certain amount of packet data is stored in the RAM, for example, when the packet transfer enabled flag is set, the transmission buffer 4
Packet data is sequentially transferred to and output to the outside.

FIG. 4 is a flowchart of FIG. 3, showing the flow of processing when the address generation circuit performs transfer.

If the packet transfer enable flag is set, first, address information in the RAM at that time is temporarily saved in another register (not shown) (step l>).

After that, in the selector 2b, the address initial value signal S
4 is selected by the control signal S5, the address initial value signal S4 is stored in the register 2c in synchronization with the latch clock signal S6. A certain address word St outputted from this becomes the initial address value of the RAM. In this way, the initial address value of the packet data to be transferred is set (step 2). Further, the contents of the RAM corresponding to the set address are read out and transferred to the transmitter 3 {step 3}. Then, in order to generate the address of the packet data to be transferred next, the address change signal S2 is input to the adder 2a, and the change signal S2 and address signal S1 are added, and the output signal S3 is the addition result. is input to the selector 2b. In the selector 2b, the output signal S3 is selected by the control signal S5, and the output signal S3 is stored in the register 2C in synchronization with the latch clock signal S6. The address signal S1 output from the register 2c becomes a new address value of the RAM that is added by +1 to the initial address value (step 4).

Furthermore, this new transfer address is saved in another register (not shown) (step 5). Finally, step l
The address saved in step 6 is reset and the process returns to the process before packet transfer (step 6).

Conversely, when packet data is input to the reception buffer 5, a packet transfer enabled flag is similarly set and the DS
The data is sequentially transferred to the internal RAM of P2 and stored. Thereafter, packet data is reproduced in the DSP 2, and an analog audio output signal AO is obtained through the D/A converter 5. In the series of operations described above, after the DSP 2 executes a transfer command, it performs other processing while the next transfer command is being issued, thereby improving processing efficiency.

(Problems to be Solved by the Invention) However, in the address generation circuit with the above configuration, when transferring packet data, it is necessary to save the address, set a new address, generate the next address, and restore the old address. As a result, the signal processing becomes complicated and many processing steps are required.This hinders the increase in signal processing speed and makes it difficult to solve the problem.

The present invention provides an address generation circuit and a signal processing processor using the same, which solves the problem of the prior art that signal processing is complicated, which hinders the increase in signal processing speed. It is something.

(Means for Solving the Problem) In order to solve the problem, in the invention No. 2, a first register for holding an address that outputs the address signal No. An address generation circuit comprising: an arithmetic unit that calculates an address change signal for a signal; and a first selector that selects an output of the arithmetic unit or a predetermined address signal of packet data and outputs the selected address signal to the first register, The following measures were taken.

a second register for holding data that outputs a second address signal; an address increment means for incrementing the second address signal; A second selector outputs the signal to the register, and a third selector selects the first or second address signal.

A second invention includes a digital signal processing section that performs predetermined digital processing on a digital input signal, a transmitting section that drives and transmits data from the digital signal processing section, and a transmitting section that receives external data and processes the digital signal. The signal processing processor includes a receiving section that drives and outputs signals to a signal processing section, and takes the following measures.

The digital signal processing section includes an address generating circuit according to claim 1, and connects an occasional memory holding circuit whose output specifies an address, and the occasional memory holding circuit to the transmitting section and the receiving section. An internal data bus is provided.

(Function) According to the first invention, since the address generation circuit has been designed as described above, the second register holds the address signal for packet transfer data, and based on the synchronization of the latch clock signal, the second register holds the address signal for packet transfer data. A signal is output in the form of a second address signal. The address increment means adds +l to the second address signal, and the second selector
The addition result and a predetermined address signal are selected and the selection result is output to the second register. The third selector selects the first or second address signal.

According to the second invention, the occasional memory holding circuit operates to quickly store and transfer packet transfer data. The internal data bus serves to convert discrete packet transfer data to serial data.

Therefore, the above problem can be solved.

(Embodiment) FIG. 5 is a block diagram of a signal processing processor showing an embodiment of the present invention.

This signal processing processor is used for packet communication, and includes, for example, an oversampling type A/D converter 1o that converts an analog audio input signal Di into a digital signal, and an oversampling type A/D converter 1o that converts the digital signal into an analog audio output signal Ao.
For example, it has an oversampling type D/A converter 2o. And those A/D converters 1
0 and a D/A converter 20 are connected to the DSP 30, respectively.

The DSP 30 is a device that removes mixed noise from the digitized audio input signal Di, determines the presence or absence of audio, and stores the memory section 31. Arithmetic unit 32 and control unit 33
etc., including a memory section 31, a calculation section 32, and a control section 3.
3 is connected to the internal data bus 34 along with the A/D converter 10 and the D/A converter 2o. Connected to the internal data bus 34 are, for example, a transmitting section 40 consisting of a packet transmitting serial buffer and a receiving section 50 consisting of a packet receiving serial buffer. It is connected.

Here, the arithmetic unit 32 is a circuit that includes an ALU, a multiplier, a register, an accumulator (ACC), etc., and performs arithmetic operations and logical operations.
It controls the function of P30 and is composed of an instruction register and the like. The memory unit 31 is, for example, a circuit that stores a packet data format, and is composed of a RAM 31a that is a memory holding circuit at any time, an address generation circuit 3lb that generates an address signal for the RAM 31a, and the like. The input/output of the RAM 31a is via the internal data bus 3.
Connected to 4.

FIG. 1 is a block diagram of the address generation circuit 3lb in FIG. 5, showing an embodiment of the present invention.

This address generation circuit 3lb generates a first address signal S
It has an arithmetic unit 110 that adds IOO and address change signal S101. Output signal S1 of the arithmetic unit 110
02 is connected to the input side of the selector 120 together with an address initial value signal 8103 that determines the initial value of the address. This selector 120 is a circuit that selects the signal S103 and the signal S102 by the control signal 8104,
Its output side is connected to a register 130.

The register 130 is a circuit that stores the output of the selector 120 and outputs the first address signal SIOO based on the synchronization of the latch clock signal S105.

On the other hand, the selector 140 is a circuit that selects between the output of the adder 150 and the address initial value signal S103 in accordance with the control signal S140, and its output is connected to the register 160. Register 160 receives latch clock signal S16
This circuit temporarily holds the output of the selector 140 based on the synchronization of 0, and the second address signal S200, which is the output of the register 160, is connected to the input side of the adder 150 and the third address signal S200.
is commonly connected to one input side of the selector 170. Further, the other input side of the third selector 170 is connected to an address signal SIOO.

Here, the adder 150 is a circuit that adds +1 to the address signal S200, and the selector 170 is a circuit that adds +1 to the address signal S200.
0, the address signal St00. Of S200,
This circuit selects one and outputs an address output signal OUT.

FIG. 6 is a flowchart of FIG. 1, and FIG. 7 is a flowchart of packet transfer.
The operations in FIGS. 1 and 5 will be explained.

When the analog audio input signal Di is input to the A/D converter ↓0, the input signal Di is converted into a digital signal by the A/D converter 10 and input to the DSP 30.

The DSP 30 removes noise mixed in the digital audio input signal Di, determines the presence or absence of audio, and then converts the audio input signal Di into a packet data format and stores it in the RAM 31a.

When a certain amount of packet data is stored in the RAM 31a,
For example, when the packet transfer enable flag is set, the control signal S170 of the selector 170 is changed to the second address signal S2.
It is controlled to select 00. Now, assuming that the first address of the packet transfer data is determined in advance and the initial address is input to the register 160 by the address initial value signal S103 (step ■ in FIG. 6), the output address signal S200 is output to the RAM 31a in the form of an address output signal OUT, and as a result, packet data corresponding to the address signal S200 is read out and transferred to the transmitter 40 (step 2 in FIG. 6).At the same time, the register A latch clock signal S160 is supplied to the register 160, and a value obtained by adding +1 to the current address is newly stored in the register 160. After that, the control signal S170 of the selector 170 is set to select the first address signal SIOO. The DSP 30 returns to other processing.

RAM. When packet data stored in 31a is sequentially transferred to the transmitter 40, until the transmitter 40 completely sends out the data to the outside, that is, until the transmitter 40 becomes empty, The DSP 30 cannot transfer the next data to the transmitter 40. Therefore, as shown in Figure 7,
The processing speed of the DSP 30 and the processing speed of the transmitter 40 are 1
If the ratio is 64, packet data will be sent from the DSP 30 to the transmitter 40 by the transfer command x times in 64 steps. Further, packet data is usually composed of bytes, and FIG. 7 shows a transfer operation of 16 bytes of packet data. In other words, it shows the process of a transfer operation that is repeated 16 times. At that time, for example, in transfer 1, first, address address 0 of RAM 31a
The data stored in 000H is read and sent to the transmitter 40. When the packet transfer in this transfer 1 is completed, the DSP 30 starts another signal processing.

When the signal processing at address 2F31H at step 64 is completed, the second packet transfer 2 is started. Thereafter, the process is repeated in the same manner up to transfer 16.

Conversely, when packet data is input to the reception buffer 50, a packet transfer enabled flag is similarly set and the D
The data is sequentially transferred to the RAM 31a of the SP 30 and stored therein. Thereafter, packet data is reproduced in the DSP 30, and an analog audio output signal AO is obtained through the D/A converter 20.

This embodiment has the following advantages.

(1) In the conventional address generation circuit, six processing steps were required, including operations for saving an address, setting a new address, generating the next address, and restoring the old address. However, by selecting the second address signal by the selector l70, the address can be saved and a new address can be set. Furthermore, the generation of the next address has already been executed by the adder 150, and by holding the output of the adder 150 in the register 160 at the same time as the packet data transfer, this information can be retained. Therefore, the number of processing steps is reduced compared to conventional circuits, and packet transfer is possible with two processing steps.

(2> When writing packetized data to or reading from RAM 31a, RAM 3 1
The address generation of a can be sequentially controlled only by the latch clock signal 8160. moreover,
Since a conventional address generation circuit is also included, input/output access of packet data can be performed reliably and easily when necessary without confusing the conventional addressing function.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following variations.

(I> The adder 150 may be, for example, a half adder or a program counter.

(II) The arithmetic unit 32 can also be horizontally implemented, for example, by a full adder or the like.

(Effect of the invention) As explained in detail above, according to the first invention, the second invention
Since a dedicated address for packet data transfer is generated using the register, the second selector, the address increment means, and the third selector, the processing steps can be significantly reduced and the signal processing speed can be increased. can be achieved.

In the second invention, since the address generation circuit of the first invention is used to specify the address of the memory holding circuit at any time, D
The SP can perform other signal processing without being bothered by packet data transfer processing.

[Brief explanation of the drawing]

Fig. 2 is a block diagram of an address generation circuit showing an embodiment of the present invention, Fig. 2 is a block diagram of a conventional signal processing processor, and Fig. 3 is a block diagram of a conventional address generation circuit. 4 is a flowchart of FIG. 3, FIG. 5 is a horizontal block diagram of a signal processing processor showing an embodiment of the present invention, FIG. 6 is a flowchart of FIG. 1, and FIG. 7 is a flowchart of packet data transfer. be. 30... DSP, 31a... Occasional memory holding circuit, 3lb... Address generation circuit, 34
...Internal data bus, 40...Transmitter, 50...Receiver, 110...Arithmetic unit, 120, 140, 170...・First, second. 3rd selector, 130.160... 1st, 2nd
Register, 150... Adder, SIOO...
...First address signal, 3101...Address change signal, S102...Output signal, S1
03...Predetermined address signal, S104, S14
0, S170... Control signal, S105, S16
0... Latch clock signal, S200...
...Second address signal, Di...Analog audio input signal, Ao...Analog audio output signal.

Claims (1)

[Scope of Claims] 1. A first register for holding an address that outputs a first address signal, a computing unit that computes the first address signal and an address change signal for the address signal, and the computing unit a first selector that selects a predetermined address signal of a device output or packet data and outputs the selected address signal to the first register; a register; address incrementing means for incrementing the second address signal; a second selector for selecting the output of the address incrementing means or the predetermined address signal and outputting it to the second register; An address generation circuit comprising: a third selector for selecting a second address signal. 2. A digital signal processing section that performs predetermined digital processing on a digital input signal, a transmitting section that drives and transmits data from the digital signal processing section, and a receiving section that receives external data and sends it to the digital signal processing section. A signal processing processor comprising a receiving section that drives and outputs the digital signal processing section, wherein the digital signal processing section has the address generating circuit according to claim 1, and an occasional storage holding circuit whose output specifies an address; A signal processing processor comprising: an internal data bus that connects a memory holding circuit to the transmitting section and the receiving section at any time.