JPH0322052A - memory mapper device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory mapper device that accesses a block address of a memory having a plurality of blocks divided into blocks of predetermined capacity.

[Prior Art] Recently, small electronic devices such as calculators and electronic notebooks with multiple functions have been put into practical use, but these electronic devices require large-capacity memories due to the increase in the number of program steps and the amount of data. It is now possible to

By the way, for CPUs used in such electronic devices that have 16 memory address lines, the address space that can process direct memory access is 2" - 6 5 5 3 6 (in the case of an 8-bit machine) is 64 Kbytes). Therefore, in order to handle a larger address space, it is necessary to extend the address by supplementing the memory address line by some method.

Therefore, as a conventional method to solve such problems,
It is being considered that the CPU output port is used to add an address bus. However, although this method can be programmed, there are many restrictions on the software, and in particular, the address at which the command to switch the output port is issued and the address after the command is executed are not consecutive. For example, 80
When the output port is switched to 3 at address 012h, the execution address of the next instruction becomes 30013h.

This became an obstacle when designing programs, and the range of applicability was limited.

On the other hand, as another method, a method using a memory mapper is also considered. This method is expanded by setting the memory address space as a set of logical memory units (segments) of a predetermined length, and generating the memory real address by adding an offset address value to the segment start address value that makes up the logical address. I'm trying to get an address. According to this method, it is possible to access one segment space, but it is not possible to access consecutive segments or segment spaces located far apart, which limits the flexibility of memory space access. For these reasons, it had the disadvantage of making program design troublesome.

[Problems to be Solved by the Invention] As described above, in the conventional method that uses the CPU output port to add an address bus, the address at which the command to switch the output port is issued and the address after execution are not consecutive. This becomes an obstacle in program design and limits the range of applicability, and those using memory mappers cannot access consecutive segments or segment spaces located far apart. However, there were drawbacks such as limited flexibility in accessing memory space, which made program design troublesome.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a memory mapper device that can process non-contiguous spaces as if they are continuous and can simplify program design.

[Means for Solving the Problems] The present invention provides a memory mapper device that accesses a block address of a program area or a data area of a memory having a plurality of blocks divided into blocks of predetermined capacity. A plurality of address registers specifying block addresses of the program area or data area of the memory directly accessed by the address space, a register selection means for selecting and specifying one of the address registers according to the memory access state, and the register selection means It consists of a rewriting means for arbitrarily rewriting the contents of the selected address register.

[Operation] According to the present invention, each block address of a program area or a data area of a memory having a plurality of blocks divided into blocks of a predetermined capacity can be accessed by selecting and specifying an address register. Further, by selectively specifying the address registers corresponding to the address space of the divided CPU, it is also possible to successively access the block addresses specified by these address registers.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit structure of the same embodiment. In the figure, 1 is an 8-bit CPU, and this CPU is provided with 8 data lines DO to D7 and 16 address lines AO to Al5, making the address space capable of direct memory access processing 64 Kbytes. Further, this CPUI has an address space configured into two banks of 32K bytes each.

The data line DO-D7 prepared for the CPUI is connected to the memory mapper 2 and also connected to the memories 3 to 6, and among the address lines AO to Al5, the address lines AO,
AI and Al5 are connected to the memory mapper 2, and an address line An-AI4 is connected to the memories 3 to 6.

Memory mapper 2 is a program address register (IBR).
)21 and data address register (BRO) (BRI
) 22, 23.

These address registers 21 to 23 are connected to address lines AO,
It is selected by the address signal of Al, and data writing to the data lines DO to D7 is performed when the register set signal RS is "1". Further, the address register 21 is read out at the timing when both the address signal and data signal DT on the address line A15 are "1" and the fetch signal FE is "1", and in the same way, the address signal and data signal on the address line Al5 are read out. When DT is both rOJ and the fetch signal FE is "1", the address register 22
read, the address signal of address iAl5 is “1”
, the data signal DT is rOJ, and the fetch signal FE is “1”.
The address register 23 is read out at the timing of "."

Here, the address registers 21 to 23 are composed of 1 byte of DO-D7 as shown in FIG.
o-D4 is a memory block designation byte, and DB and D7 are memory designation bytes. The contents of the block designation byte DO-D4 here are output to the address lines A15 to Al9 as an extended address signal, and
It is applied to the memories 3 to 6 together with the address signals O to Al4. Further, the contents of the memory specifying bytes D6 and D7 are outputted as an enable signal of EO-E3 by the combination shown in FIG. 7, and are applied to the memories 3 to 6. Here, the enable signal EO is given to the memory 3, the enable signal El to the memory 4, the enable signal E2 to the memory 5, and the enable signal E3 to the memory 6.

Memories 3 to 6 have a space of IM bytes, and each space is divided into 32 blocks of 32K bytes BLO-
It is divided into BL31.

FIG. 2 shows the connection relationship between the memory mapper 2 and the memories 3 to 6. In this case, logical address signals AO to A
Of l5, the address signal Al5 is given to the register selection unit 24 of the memory mapper 2, and the address signal Al5 is sent to the address registers 21 to 23.
Select and specify one of the corresponding items, and extract the contents of this item. In this case, one of the memories 3 to 6 is designated by the enable signal EO-E3 corresponding to the memory designation bytes D6 and D7 of the contents of the selected address registers 21 to 23, and the block designation pi}DO~ D
A specified memory block is designated by address signals A15 to Al9 corresponding to 4, and this address signal AI
The address of the memory block specified by the logical address signals AO to Al4, which together with 5 to Al9 constitute a 20-bit real address, is accessed.

FIG. 3 shows a specific circuit configuration of the memory mapper 2. As shown in FIG. In this case, the data line DO-D7 is connected to the program address register 21 and the data address registers 22, 23 from the CPUI, and a register set signal RS is applied thereto. Further, the address line AO1Al is connected to the decoder 25 constituting the register selection section 24 from the CPUI. Decoder 25 is address line A
Address registers 21 to 23 are selected and designated by a combination of address signals AO and AI of O and At. The outputs of address registers 21 to 23 are then given to multiplexer 26.

The multiplexer 26 is supplied with an address signal Al5 from an address line A15 of the CPUI, as well as a data signal DT and a fetch signal FE.

Further, the address signal A15 of the address line Al5 is applied to the inverter 27, and the data signal DT is directly applied to the address generation section 28.

Here, the multiplexer 26 outputs both the address signal Al5 and the data signal DT to "1" as shown in FIG.
specifies the register address "2", specifies the program address register 21, and sends the fetch signal F.
E reads the data of the same register 21 with “1”,
Further, the address signal Al5 and the data signal DT are both "o", indicating the register address "0" and specifying the data address register 22, and the edge signal FE is "1", indicating the data in the register 22. is read, the address signal Al5 is "1" and the data signal DT is "0".
” specifies the register address “1” and specifies the data address register 23, and the fetch signal FE changes to “
1", the data in the address register 23 is read, and furthermore, the address signal Al5 is "0" and the data signal D is
T is rlJ, which indicates that there is no address register address. That is, the address register is selected and specified depending on the output states of address signal Al5 and data signal DT. The memory block designating byte DO-D7 of each address register 21-23 output from the multiplexer 26 is output as an extended address signal to the address lines A15-Al9,
, D7 are given to two decoders as memory designation signals. As shown in Figure 7, the two decoders are configured with memory specification bytes DB and EO to E depending on the combination of the contents of D7.
3 enable signals are output.

On the other hand, the address generating section 28 generates an output when the address signal of the address line Al5 is "0" and the data signal DT is "1". , ro O O to address lines A15 to Al9 as block designation signals.
O OJ is output.

Therefore, in such a structure, first, a case in which data is written to the program address register (IBR) 21 of the memory mapper 2 will be described. In this case, Fig. 5 (a
), of the address lines AO-Al5 of the CPUI, the address signals AO, Al of the address lines AO, Al
is sent to the memory mapper 2. These address signals AO
, At are applied to the decoder 25 of the memory mapper 2, and the register 21 is selected by the combination of the address signals AO and Al at this time. In this state, when the register set signal RS is applied together with the data write signal WR, the CPU sends the data DO to D on the data lines DO to D7.
7 is written to register 21.

On the other hand, the data address register (B
When writing data to RO) (BRI) 22 and 23, it is the same as above, and the address signal A of the address lines AO and A1 is
With the registers 22 and 23 selected and specified by O and AI, data DO to D7 are written via data lines DO to D7 of the CPUI.

Next, the case where a program is read by the CPUI will be explained. In this case, the CPU divides the address space into banks of 32K bytes each, BANKO, as shown in FIG. 8(a).
In banks BANKO from oooo to 7FFF, the address signal of the address line Al5 is "0" and the data signal DT is "1". Then, the address generator 28 outputs the enable signal EO via the OR circuit 30, and r0 0 0 0 0J is output to the address lines AI5 to Al9 as an extended address signal for block designation. As a result, memory 3 is specified and bank BANKO
logical addresses AO to Al4 and extended addresses A15 to A
Since the real address consisting of 19 is output, the block BLI of the memory 3 is unconditionally specified by the extended address signal, and the program is read into this block BLI.

Next, in bank BANK 1 from 8000 to FFFF,
As shown in FIG. 5(b), both the address signal and data signal DT on the address line A15 become "1", and the program address register 21 is designated. When the fetch signal FE becomes "1" in this state, the data in the register 21 is read out. In this case, register 2
The contents of memory block designation bytes DO to D7 are output as extended address signals to address lines AI5 to Al9, and the contents of memory designation bytes DB and D7 are given to two decoders; −
If rOJ is specified, enable signal EO is output and memory 3 is designated. In addition, addresses aA15 to Al9
The block designation signal output to bank BAN
It is output as a real address along with the logical addresses AO to Al4 of KI, but if block BL20 is specified by the extended address signal, the program will be read into block BL20 of memory 3. Become. In other words, in this case, 0000-7F
For FF bank BANKO, the program is fixedly loaded into block BLI of memory 3,
Following this, at BANKI 8000-FFFF, a program is read for an arbitrary block, block BL20 here. This state is shown in Figure 8 (b
).

Next, a case in which a CPU program refers to data will be described. In this case, in banks BANKO from 0000 to FFFF of the CPU 1, both the address signal and the data signal DT on the address line Al5 become "O" as shown in FIG. 5(C), and the data address register 22 is designated.

When the fetch signal FE becomes "1" in this state, the data in the register 22 is read out.

In this case, the memory block designation byte D of register 22
The contents of O to D7 are output to address lines Al5 to Al9 as memory block designation signals, and are output to memory designation bytes DB.
, D7 are given to the decoder 29, where DB-rlJ, D? - I'l'', then
Enable signal E1 is output, and memory 4 is designated. Furthermore, the block designation signals output to the address lines A15 to A19 are output as real addresses together with the logical addresses AO to Al4 of bank BANKO, but here, if block BL2 is designated by the extended address signal, For example, data reference is executed to block BL2 of memory 4.

Next, in bank BANK 1 from 8000 to FFFF,
As shown in FIG. 5C, the address signal on the address line A15 becomes "1" and the data signal DT becomes "1", and the program address register 23 is designated. and,
When the fetch signal FE becomes "1" in this state, the data in the register 23 is read out. In this case, the contents of the block designation bytes DO to D7 of the register 23 are output as memory block designation signals to the address lines AI5 to AI9, and the contents of the memory designation bytes D6 and D7 are given to the decoder 29; - rlJ, D7
- rlJ, enable signal E3 is output and memory 6 is specified. In addition, address lines A15 to A
The extended address signal for block designation output to l9 is the logical address AO to Al4 of bank BANK1.
At this time, it is output as a real address, but if block BL21 is designated by the extended address signal, data reference will be executed for block BL21 of memory 6. In other words, in this case, 0
For bank BANKO from 000 to 7FFF, data reference is executed to block BL2 of memory 4,
Following this, in the bank BANK1 from 8000 to FFFF, data reference is executed for the block BL21 of the memory 6. This state is shown in FIGS. 9(a) and 9(b).

Therefore, in this way, the extended address signal can be added to the logical address signal of the CPUI by the memory mapper, so that it is possible to handle an address space larger than the address space that can be processed by the CPUI. In addition, the space that can be processed by the CPU is stored in the bank BANKO.
, BANKI, and each bank BANKO.
Since any memory blocks BLO to BL31 of memories 3 to 6 can be allocated to , BANKI,
Not only contiguous spaces but also non-contiguous spaces can now be accessed as if they were contiguous, increasing the flexibility of memory space access and reducing restrictions on program design. Easy design can be achieved without any problems.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist.

For example, in the above embodiment, when the CPUI reads a program, the bank BA of 0000 to 7FFF of the CPUI is
In NKO, memory 3 is generated by the output of address generator 28.
Although the block BLI is specified unconditionally, two registers corresponding to the program address register 21 may be provided to perform the same operation.

[Effects of the Invention] According to the present invention, each block address of a program area or data area of a memory having a plurality of blocks divided into blocks of a predetermined capacity can be accessed by selecting and specifying an address register, so that processing is not required by the CPU. It can handle address spaces larger than possible. In addition, the address register is divided into two CPUs.
The block addresses specified by these address registers can be accessed consecutively, so not only continuous spaces but also non-contiguous spaces can be accessed as if they were continuous. The memory space can be accessed as if the memory space is accessed, increasing the flexibility of memory space access and simplifying program design.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, Fig. 2 is a diagram for explaining the connection relationship between the memory mapper and memory of the embodiment, and Fig. 3 is used in the embodiment. FIG. 4 is a diagram for explaining the selection and designation of the address register of the same embodiment. FIG. 5 shows the operation of the same embodiment. FIG. 7 shows the contents of the memory designation byte of the address register. FIGS. 8 and 9 are diagrams showing the relationship between enable signals, and are diagrams for explaining the operation of the same embodiment. 1...CPU, 2...Memory mapper, 21...Program address register, 22, 23...Data address register, 25, 29...Decoder, 26...
・Multiplexer, 28...Address generation section, 3 to 6
···memory.

Claims (1)

[Claims] In a memory mapper device that accesses block addresses of a program area or data area of a memory having a plurality of blocks divided into blocks of predetermined capacity, the program area or data of the memory is accessed directly by an address space of a CPU divided into at least two parts. A plurality of address registers for specifying block addresses of an area, a register selection means for selecting and specifying one of the address registers according to the memory access state, and a register selection means for arbitrarily writing the contents of the address register selected and specified. A memory mapper device characterized by comprising: means for changing the memory mapper.