JPH0322053A - Move in buffer control system - Google Patents

Abstract

PURPOSE:To shorten the waiting time of an arithmetic processor even at the time of the continuous occurrence of data requests to quickly perform the processing by providing plural move in buffers which store data of information from a main storage device in a buffer storage device after holding this data to be stored in the buffer storage device. CONSTITUTION:Main storage access registers 5 and 6 and move in buffers 7 and are operated as pairs respectively. When a part of the actual address stored in a logical address register 1 of the main storage access register 5 and the page address outputted from a conversion index buffer means 4 are stored in the main storage access register 5, data outputted from the main storage device is stored in the move in buffer 7. When they are stored in the main storage access register 6, the output of the main storage device is stored in the move in buffer 8. The waiting time of the arithmetic processor is shortened even for continuous requests because plural move in buffers 7 and 8 are provided, and the processing is quickly performed.

Description

[Detailed Description of the Invention] [Summary] Regarding a move-in buffer control method when the data requested in response to a main memory access request does not exist in the buffer storage device, the main memory The purpose is to reduce the waiting time of the arithmetic processor and enable high-speed processing without depending on the response order of the storage device, and includes a part of the supplied page address and real address along with the request to the main storage device. a logical address register for storing a requested address; and at least a portion of the requested address stored in the logical address register;
a buffer storage device that holds a copy of some of the information in the main storage device and at least a portion of the requested address stored in the logical address register; A tag for storing a real address in a storage device, a translation index buffer means for holding the latest page address obtained by adding address address translation and at least a part of the request address stored in the logical address register, and the translation index buffer means a plurality of main memory access registers for storing the real address of the main memory consisting of the page address part obtained from the page address field and a part of the address in the request address, and for accessing the address of the main memory; a plurality of move-in buffers that form a one-to-one pair with a main memory access register and store data from the main memory to be stored in the buffer storage after the data is stored in the buffer storage; It is configured to have the following.

[Industrial Application Field] The present invention relates to a computer system having a move-in buffer, and more specifically to move-in buffer control when data requested in response to a main memory access request does not exist in the buffer storage device. Regarding the method.

[Conventional technology]

Computer systems having buffer storage devices have been developed and put into practical use in various fields for the purpose of high-speed calculation. Conventionally, in a computer system having such a buffer storage device, a tag holding the main memory address of a valid data block stored in the buffer storage device is searched, and as a result, it is determined that the desired data exists in the buffer storage device. If not, the page obtained from the address translation index buffer
Sets the real address consisting of the address part and the real address in the request address in the main memory access register,
Data is requested from the main memory from its main memory access register.

FIG. 3 is a diagram showing the structure of the conventional system. Logical address register (LAR: Logical Address
A request address from a request source, which is an arithmetic processor, is added to the register 10, and the request address is stored. That is, when a data request is generated from an arithmetic processor, a request address that is the address of the required data is added from the arithmetic processor, and this request address is stored. This requested address is a logical address from an arithmetic processor, in other words, a processing device.

When a logical address, which is a request address, is added to the logical address register 10, the logical address register 10 stores the conversion index buffer 11, the tag 12, and the buffer memory l3.
Add that address and refer to it. Note that the tags 1 and 2 are memories that hold main memory address information of valid data blocks stored in the buffer storage device 13, and the buffer memory 13 forms a pair with the tag and stores main memory address information of valid data blocks. This is a memory that holds part of the information in the main storage device indicated by .

Then, the real page address in the translation index buffer 11 and the real page address in the logical address register lo are stored in the real address register (SAR O, SAR
1: Storage Access Register
er portO, 1) 1 4. 1 to 5. Referring to the above-mentioned tag, if the data for the requested address does not exist in the buffer memory 13, the real address register l4 or the real address register l
5 outputs a data move-in request to the main storage device.

Data output from the main memory, so-called move-in data, is moved in via a data path, for example.
The data is stored in the buffer 16. The move-in buffer 16 is located between the main storage device and the buffer storage device 13, and is a register that temporarily stores valid data blocks sent from the main storage device.

The aforementioned move-in data output from the main storage device is set in the move-in buffer, and the data is sent to the request source. In other words, move in
It is output from the buffer l6 via the selection circuit 17. Note that when data is to be sent, that is, when data is to be output, data is started to be moved in from the move-in buffer 16 to the buffer memory 13. In other words, the data output from the move-in buffer is stored in the buffer memory 13.

When all the data from the move-in buffer 16 is stored in the buffer storage 13, that is, when the move-in is completed, a bit is set to ensure the validity of the data, that is, in the corresponding entry in the tag. The above-mentioned request address, that is, a logical address is added to the tag 12, and a bit that guarantees validity is set corresponding to this logical address. Note that the above-mentioned operation is performed when the buffer memory 13 does not store data corresponding to the request address added from the request source. If it does, data is sent from the buffer memory 13 to the request source via the selection circuit 17. Output the memorized data. This selection is dictated by the outputs of translation lookaside buffer 11 and tag 12 and logical operations within logical address register 10.

On the other hand, if the above-mentioned requests occur consecutively, the request that is the subsequent instruction will use the real address that stores the previous real address.
It is stored in the other real address register of register 14 or real address register l5. For example, if the previous real address is stored in real address register l4, the following real address is stored in real address register l5.
is stored in Next, the tag 12 is referred to for the manually entered real address, and if there is no data corresponding to the real address in the buffer storage 13, a data move-in request and the real address are output to the main memory.

In the above operation, conventionally, when a data request occurs from an arithmetic processor or the like, the request address is added consecutively, but by providing two real address registers 14 and 15, for example, the request is The system is designed to be able to meet the demands even if there is an increase in demand.

[Problems to be Solved by the Invention] In the conventional move-in buffer control described above, for example, two real address registers 14 and 15 are provided, so that successive requests can be handled. However, unless one move-in operation is completed, the other move-in operation may be put on hold.

In other words, for consecutive requests, the move-in data requested later is stored in the move-in buffer 16.
If the previously requested move-in data is stored in the move-in buffer 16, the requesting arithmetic processing processor stops processing until the previously requested move-in data is stored in the move-in buffer 16. After storing it in the buffer 16 and reading it out, the move-in operation is performed again for subsequent requests.

Also, when two consecutive move-in operations occur, the move-in data output from the main memory may not necessarily be in the requested order, and the data requested later may be moved in first. Sometimes.

In such a case, after the move-in is finished,
The previously requested data will be moved in. Therefore, until the previously requested data is output to the request source,
The arithmetic processing device has a problem in that the so-called arithmetic processor cannot proceed with processing during that time.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the waiting time of an arithmetic processor and enable high-speed processing without depending on the response order of the main memory even if data requests occur continuously.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

Logical address register l stores the request address, which includes a portion of the page address and real address supplied with the request to main memory.

At least part of the requested address stored in said logical address register 1 is applied to a buffer store 2, a tag 3 and a translation index buffer means 4.

The buffer storage device 2 is a copy of some information in the main storage device,
That is, it holds some data in the main memory.

The tag 3 stores the real address in the main memory of the valid data block held in the buffer storage 2.

The translation index buffer means 4 holds the latest page address that has been translated.

The main memory access registers 5 and 6 store the real address of the main memory device consisting of the page address section obtained from the conversion index buffer means 4 and a part of the address in the request address, and also access the main memory device.

A plurality of move-in buffers 7.8 form one-to-one pairs with the plurality of main memory access registers 5.6, and store data from the main memory to be stored in the buffer memory 2. After holding, it is stored in the buffer storage device.

[For production]

When a requested address is added to the logical address register 1, the logical address register stores the requested address and converts at least a portion of the requested address into the index buffer 4.
, tag 3, is added to buffer storage 2. By adding this address again, the converted address is output from the conversion index buffer means 4, and the logical address
Part of the real address of register 1 and the page address output from conversion index buffer means 4 are added to main memory access register 5 and main memory access register 6. and main memory access register 5. One of the main memory access registers 6 stores the address for the request and accesses the main memory.

When the main memory is accessed, data corresponding to the request is added to the move-in buffer 7 and the move-in buffer 8 from the main memory.

Main memory access register 5 and move-in buffer 7, and main memory access register 6 and move-in buffer 8, operate in pairs, and main memory access register 5 has logical address register 1. When the main memory access register 5 stores part of the real address stored in , and the page address output from the conversion index buffer 4, the data output from the main memory is stored in the move-in buffer 7. Ru. Further, when those addresses are stored in the main memory access register 6, the output of the main memory device is stored in the move-in buffer 8.

There are multiple move-in buffers, so even if requests are made consecutively, data for the next request can be stored in other move-in buffers by simply storing it in the move-in buffer. For example, a processing unit can read data at the same time it is stored in a move-in buffer. [Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. In addition, in the figure, circuits that are the same as those of the conventional circuit are designated by the same reference numerals, and a description thereof will be omitted. The requested address from the arithmetic processor is applied to the logical address register IO, and the output of the logical address register IO is applied to the translation lookaside buffer 11, the tag 12, the buffer store 13, and the real address register 14.15.

The page address of the conversion index buffer l1 is also added to the real address register 14.15 and further to the control 1 unloading circuit 22. The outputs of the real address registers 14,15 are also added to the main memory address as well as to the control circuit 22. Control circuit 22 always uses real address register 14.1
5 and this real address register 14
．． 15, and if they match, the move-in buffers (BO, Bl) 24, 25 corresponding to the matching one are compared.
The selection circuit 23 selects the output. The output of the selection circuit 23 is applied to the buffer memory l3 and the selection circuit 17.

When a request is generated from the arithmetic processor and a corresponding page address is added and stored in the real address register, the selection circuit 18 is selectively operated by a control circuit (not shown) and outputs the real address stored in the main memory. do. The main memory outputs data, which is information corresponding to the real address, to the move-in buffers 24 and 25.

At this time, for example, the real address is stored in the real address register (
If the address is stored in SARO) 14, move-in buffer 24 stores the data. Furthermore, when the real address register (SARl) 15 is outputting a real address, the move-in buffer B1 stores move-in data from the main memory. The selection circuit 23 is operated by the control circuit and selects the output of the move-in buffer to which the move-in data is added, and outputs it to the selection circuit 17 and the buffer memory 3.

If data requests are not added consecutively, the operation will be the same as before, but if data requests are made consecutively, the real address
Register 14.15 and move-in buffer 24.2
5 operates in pairs, e.g. real address register 1
4 is adding an address to the main memory via the selection circuit 18, the move-in buffer 24 makes a corresponding response and adds it to the request source via the selection circuit 23. In addition, if the response is multiple, that is, for example, two addresses are stored in the real address register, two requests will be generated to the main memory, and the move will be performed when the responses are output from the main memory. - In buffer 24.
25 stores the paired move-in data.

For example, data requested earlier may be added after data requested later, but conventionally, the data requested later is stored in the move-in buffer 25 and then stored in the buffer memory 13, and then added later. data from must be stored in buffer storage 13. However, in the embodiment of the present invention, if data requested later is added as move-in data first, it is temporarily stored in the move-in buffer, and subsequently added data is stored in the remaining move-in buffer. After storing, the selection circuit 23 selects the move-in buffer and outputs it to the arithmetic processor. Within that time, later requested move-in data is stored in the buffer storage 13 from the move-in buffer (previously stored). Then, the move-in data stored in the move-in buffer requested later is stored in the buffer memory.

For example, the first real address added first is stored in the real address register 14, and the second real address corresponding to the second requested address added next is stored in the real address register l.
If the move-in data corresponding to the second real address is first output from the main storage device, the move-in data is stored in the move-in buffer 25 first. Then, the move-in data output corresponding to the first real address stored in the real address register l4 is stored in the move-in buffer 24. The move-in data stored in the move-in buffer 24 is selected by the selection circuit 23 (under the control of the control circuit 22) and output to the selection circuit 17 and further to the buffer storage I3. At this time, the selection circuit 17 selects the moop.
Selects the output of the in-buffer 24 (huffer memory 13
The data in the move-in buffer 24 is output to the requester (who performed the move-in because the data is not in the move-in buffer 24).

Conventionally, if the previously requested data cannot be added because there is only one item, the data is stored in the move-in buffer 16, and after that data is stored in the buffer storage 13, the next data to be added is moved.・According to the embodiment of the present invention, data requested later is added first, and even if it is input to the move-in buffer, it is not stored in the buffer storage 13. Data that does not need to be stored immediately; the previously requested move-in data is manually generated, output to the request source, and stored in buffer storage, and then later requested and stored in the move-in buffer. The transfer time can be shortened.

As described above using the embodiments of the present invention, the move-in buffers 24.25 and the pair of real address registers 14.15 are two sets, but are not limited to this. By providing the same number of address registers and corresponding move-in buffers, it is possible to achieve even higher speeds for a larger number of consecutive requests.

〔Effect of the invention〕

As mentioned above, in response to multiple consecutive data requests,
There is no need to perform a move-in operation again, and the performance of the system can be improved. Also,
By incorporating the path from the move-in buffer into the path to the request source, it is possible to send the requested data corresponding to the requested address from this move-in buffer, as in the prior art.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a composition diagram of an embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a conventional system. 1...Logical address register, 2...buffer storage device, 3...tag, 4... Conversion index buffer means,

Claims (1)

[Scope of Claims] A logical address register (1) for storing a request address including a supplied page address and a part of the real address together with a request to the main memory; a buffer storage device (2) containing at least a part of the requested address and holding a copy of the information of the part of said main memory; and at least a part of the requested address stored in said logical address register (1) being added; , a tag (3) for storing a real address in the main memory of a valid data block held in the buffer storage device (2); and at least a part of the requested address stored in the logical address register (1). translation index buffer means (4) for holding the latest page address that has been added and whose address has been translated;
and stores a real address in the main memory device consisting of the page address part obtained from the conversion index buffer means (4) and a part of the real address in the request address, and also stores the real address in the main memory device which is made up of the page address part obtained from the conversion index buffer means (4) and a part of the real address in the request address, and also stores the real address in the main memory device which is made up of the page address part obtained from the conversion index buffer means (4) and a part of the real address in the request address. memory access registers (5, 6) and the plurality of main memory access registers (5, 6);
, 6) and form a one-to-one pair with the buffer storage device (2).
) A move-in buffer control method characterized by having a plurality of move-in buffers that hold information from the main storage device to be stored in the buffer storage device (2) and then store it in the buffer storage device (2). .