JPH0353657B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that improves memory access management in the operation of the data processing device using a cache.

The data processing device of the present invention includes a central processor (central processing unit), a main memory (main memory) controlled by a memory control device, and a plurality of peripheral processors (e.g., terminal devices, printers, communication devices, etc.). and other similar devices). The data processing device is further provided with a cache memory. A cache is a high speed memory local to a central processor that contains a time-varying subset of main memory contents.

A cache can significantly reduce the average memory access time associated with central processor memory operations, since very high speed memory reads can be satisfied by using a high speed cache. . Regarding the reduction in memory read attempts, it is necessary to interrupt the operation of the central processor in order to bring the requested data from main memory to the central processor. In the data processing system described herein, the cache is read directly by the central processor and written to by cache write circuitry that is responsive to cache misses or main memory write operations of the central processor. Peripheral processors read from and write to main memory through the memory controller, but do not read from or write to the cache, which is dedicated to central processor operations.

Three problems arise with this type of data processing system, among others, in the operating conditions of such a cache, all of which reduce the operating speed of the data processing system.

The first problem is that if the peripheral processor does not write to the cache, but the peripheral processor writes to a location in main memory, the contents of that main memory location are moved to the cache. The cache needs to be inspected to find out whether the cache is
(done by setting the valid/invalid bit to a state indicating the entry), because the entry no longer corresponds exactly to the main memory contents. This means that at a particular time there may be a conflict between a cache read attempt and a certain peripheral processor's attempt to check the contents of the cache after a main memory write operation (tag check). are doing.

The second problem is that the cache cannot be written to and read from at the same time, so at a particular time, the central processor tries to read the cache and misses the previous cache (cache update).
There may be contention with the cache write logic attempting to write to the cache in response to. Conflicts may also exist if the cache write logic attempts to write an invalid bit after a previous tag check has demonstrated a tag match condition.

A final problem is that if the central processor reads from the cache while the memory controller is writing to the cache to update the previous write to main memory after the central processor has finished writing to main memory, Conflicts may exist at certain times.

In conventional data processing devices, caches operate in the following manner:
(1) With respect to the first problem more specifically, where overhead time must be spent quelling race conditions; (2) with respect to cache updates after a previous cache miss; (3) it is required to maintain the central processor inactive during the cache cycles provided to refresh the cache contents; It is required that the central processor be stopped during the memory cycles provided to update the write contents. All of the above problems cause memory access delays, which in turn slow down central processor performance.

The data processing device of the present invention avoids all of these disadvantages in conventional data processing devices mentioned above.

A cache typically has an operating cycle as long as the central processor's memory operating microinstruction cycle. In the data processing device of the present invention, the cache operation cycle is divided into two subcycles used for mutually exclusive operations.
divided into The first subcycle is provided for accepting central processor memory read requests along with their addresses. A second subcycle is provided for each of the other types of cache operations. More specifically, these operations are: (a) accepting an address from a peripheral processor to check the contents of the cache after the peripheral processor has written to main memory; or (b) checking the cache for a match. Either an invalid bit is obtained after the cache is obtained, or a cache miss occurs or the central processor writes anything to the cache containing later data written to main memory. By the above-described means of the present invention, race conditions are eliminated so that overhead time does not have to be spent quelling the race conditions, and write operations are "differentiated" from central processor cache read operations. transparent). From the central processor's perspective, the cache is always available for read operations. Regardless of the fact that the contents of the cache are being examined, invalidated, or updated ``simultaneously'' after the central processor writes, the central processor writes the cache uninterrupted in successive central processor microinstruction cycles. Reading can be continued. Although the central processor must be shut down after a cache miss to allow cache updates, the central processor can be The operation can be restarted in an earlier cycle than the restart of the operation.

Additionally, the memory management structure according to the invention is particularly circuit economical, reducing both cost and size requirements.

According to the present invention, the data processing device of the present invention includes:
a central processor having memory address register means for providing memory address signals and a memory data register for accepting and providing data signals;
and a control signal store coupled to the central processor for providing control signals representing microinstructions to the central processor. A particular control signal of the microinstruction represents a read or write memory access operation, and the central processor generates a memory address signal in response to the memory access control signal and stores the memory address signal in a memory address register. have it placed. The data processing device further includes a physical memory addressable by the memory address signals and adapted for storing data signals.

This physical memory consists of relatively slow access main memory and relatively fast access cache memory. A central processor memory address register is connected to the physical address to provide a memory address signal to the physical memory. The central processor also provides memory access control signals to the physical memory. The data processing apparatus further includes master timing generation means connected to each of the central processor and physical memory, the master timing generation means providing timing pulses to the central processor and physical memory. .
The particular timing pulse defines a central processor operating cycle, which has a fixed length of time for operations including memory accesses. At least one peripheral processor is connected to the physical memory for read and write access to the physical memory, and the peripheral processor provides memory address signals, memory access control signals, and data signals to the physical memory. provide,
Accepts data signals from physical memory.

The cache memory has memory timing means responsive to the master timing generation means for providing a plurality of timing pulses defining a cache operating cycle.

The cache includes data signal storage means for storing data signals, addressing means for addressing the data signal storage device by providing a memory address signal received from the aforementioned physical memory, and the presence or absence of specific data in the cache. comparator means responsive to the applied address signal and the stored data signal to generate an output signal indicative of the specified data; and comparator means responsive to the applied address signal and the stored data signal to generate an output signal representative of the data; and signal generating means responsive to the output of the means.

The cache addressing means is responsive to the cache memory timing means to provide a first portion of the cache operating cycle for applying only address signals received from the central processor to the cache data signal storage means and comparator means; The cache addressing means is responsive to the cache memory timing means to initiate a cache operation cycle for one of a plurality of operations including applying address signals received from the peripheral processor to the cache data signal storage and comparator means. the second of
provide a portion of

The master timing generating means inhibits timing pulses of the central processor in response to a first state of the status signals representing the presence or absence of specific data from the cache data storage means, thereby stopping the central processor. The physical memory is responsive to a first state of the status signals in conjunction with a memory access control signal received from the central processor to cause the physical memory to perform a main memory access operation, the main memory access operation being configured to address particular data. the operations of applying memory address signals received from the central processor to the main memory; and providing specific addressed data to the central processor. The cache signal generating means generates a status signal having a second state in response to completion of a main memory access operation, and the master timing generating means generates a central processor timing pulse in response to the second state of the status signals. , thereby restarting the central processor.

The physical memory further comprises cache writing means. The cache further has validity information storage means cooperating with the data storage means, each having one of two states and being addressable by a memory address signal. It has multiple valid bits.
The cache write means is responsive to the output of the comparator means, the output of the comparator means being generated in response to applying a peripheral processor memory address signal to the cache data storage means and the comparator means; A write operation is executed, and the write operation is
The act of applying a memory address signal of the peripheral processor to address a location in the valid information storage means and setting the valid bit at the location to a first state representing invalid. The cache write means is responsive to the cache timing means to perform the first write operation during a second successive portion of the cache operation cycle. The cache signal generation means is also responsive to the first state of the valid bit. to generate a state signal having a first state.

The cache write means is responsive to completion of the main memory access operation and to memory address signals and memory access control signals received from the central processor to perform a second write operation, the write operation comprising:
the cache writing means being responsive to the cache timing means, comprising applying a memory address signal to address a location in the cache data storage means and writing the resulting particular data to the location; and causing a second write operation to be performed during a second portion of the cache operation cycle.

Other objects, features and advantages of the invention will become clearer from the following description of the preferred embodiments taken in conjunction with the accompanying drawings.

The present invention will be described below with reference to the drawings. First, FIG. 1 shows in a simplified form the entire system related to a data processing apparatus as an embodiment of the present invention. Data processing system 10 is provided with a central processor 12, a control signal storage 14, and a master clock 20. The data processing device is further provided with a main memory 16, which is controlled and accessed by a memory controller 18. Various peripheral devices (terminal devices, printers, disk storage devices, magnetic tape storage devices, communication equipment, and similar devices to those mentioned above, etc.) 9
a to 9c are coupled to the data processing device 10 to form the system of the present invention.

Each peripheral device contains one processor, called the peripheral processor. A plurality of peripheral processors are connected to one of the bus adapters 22, which in turn is connected to the memory controller 18. There may be multiple bus adapters. The purpose of bus adapter 22 is to provide a buffer between the 64-bit data lines internal to the data processing system and the 16-bit data lines connecting peripheral devices to data processing system 10. Memory controller 18 provides access to main memory 16 for the central processor and peripheral processors, and also transfers instructions from central processor 12 to peripheral processors in a manner not of interest to the present invention. ) can be transmitted.

Central processor 12 is connected to a high speed local memory or cache 24 which contains a time varying subset of the data stored in main memory. Cache 24 is also connected to memory controller 18. The particular cache in the preferred embodiment is directly mapped and has 32K bytes. The cache is used as a write-through strategy, ie, the cache is updated whenever the central processor writes data to main memory.

Cache 24, main memory 16 and memory controller 18 form the physical memory of the data processing system.

The data and address paths flowing through the data processing apparatus system of the present invention are shown more specifically in FIG. Central processor 12 has a 24-bit address bus 26 which conveys address lines labeled as the mnemonic "MA (for memory addresses) 0-23" to cache 24. The central processor 12 has a 32-bit data input bus 28 which carries data lines labeled as the mnemonic "MM (for main memory) 0-31";
It has a bit data output bus 30 which carries data lines labeled as a simple signal "WD (for write data) 0-31".

Cache 24 accepts address lines MA0-23 on bus 26 from central processor 12;
It is further connected to a bus 32 which carries address lines from the bus adapter 22 labeled as the abbreviation "BMA (for bus adapter memory addresses) 0-23". This address information is used to keep information updated when corresponding information in main memory is changed by one of the peripheral processors, as will be discussed in more detail below.

The cache 24 is connected to an address output bus 34 which conveys address lines labeled as the abbreviation "CMA (for cache memory addresses) 0-23" to the memory controller 18. Cache 24 is further connected to a bus 36 which conveys address lines labeled as the mnemonic "BMAR 3-20" (for buffered memory registers) to main memory 16.

The cache 24 has one data input bus and one
The data input bus 38 has two data output buses, the memory controller 1 designated by the abbreviation "CAWD (for cache write data) 0-63".
transmits the data line from 8. Data input bus 38 is used in memory controller 18 to write data to the cache after a cache miss, or is responsive to central processor writes to main memory, as will be discussed in more detail below. Data input bus 38 is also used to transmit data to bus adapter 22 in a manner not of interest here. Data output bus 40 is connected to central processor 1 connected to bus 28.
The data lines from cache 24, designated as mnemonic symbols MM0-31, are transmitted to provide input to cache 24. After a cache hit, data output bus 40 provides data to central processor 12 in response to a read request from the central processor, as will be discussed in more detail below.

Main memory 16 accepts address lines BMAR3-20 from cache 24 on bus 36 previously mentioned, along with memory module select signals which are not shown and are not of interest to the present invention. Main memory 16
has a 64-bit data input bus 42 connected to the memory controller 18, designated by the abbreviation MMWD (for main memory write data) 0-
63” transmits the data line displayed as “63”.
All data written to main memory 16 is transferred to bus 4.
This is the input above 2. Main memory 16 is connected to a 64-bit data output bus 4 to memory controller 18.
4, the data output bus carries data lines labeled as the abbreviation "MMRD (for main memory read data) 0-63." All data read from main memory 16 is read out on bus 44.

Bus adapter 22 responds to peripheral processor memory access requests and outputs address bits to cache 24 over bus 32 previously described in a manner not of interest to the present invention. The bus adapter 22 has a 64-bit data output bus 46 connected to the main memory controller 18 carrying data lines labeled as the mnemonic "BARD (Bus Adapter for Read Data) 0-63," and BAWD (for bus adapter write data)
It has a 64-bit data input bus 48 connected to bus 38 through a buffer circuit 50 carrying data lines labeled 0-63. "Bus adapter read data" relates to data read from the peripheral device processor to the main memory 16, and "bus adapter write data" relates to data read from the main memory 16 and data written to the peripheral device processor. It should be noted that

Additionally, bus adapter 22 outputs certain control signals to cache 24. These control signals are
MRBA (bus adapter memory request signal) and
BAC (bus adapter control signal) 0-2. Applicable
The BAC0-2 signals are latched inside the cache for convenience of use, and in their latched form they are shown as BBAC0-2.

As mentioned above, memory controller 18 receives data from main memory 16 on bus 44, data from bus adapter 22 on bus 46, or data from central processor 12 on bus 30. Main memory controller 18 is connected to cache 2 on bus 34.
Accept address data from 4. Main memory controller 18 outputs data to data latch circuit 50 onto bus 38 for output to cache 24 and bus adapter 22. Memory controller 18 also outputs data onto bus 52 (through latch circuit 54) to central processor 12 carrying data lines designated as the mnemonic "DIRD (for diagnostic or read data) 0-31."
As will be explained more fully later, in the case of a main memory read following a cache miss,
A “cache miss extension” is introduced in response to a cache miss condition in the method described below.
Extended) signal allows data from bus 52 to be transmitted to bus 28 through data latch circuit 54, thereby transmitting the data to the central processor.

Referring to FIG. 3, only the two elements of central processor 12 that are of interest to the present invention are shown in the drawing. These elements are connected to the bus 28
(MM0-31), and a memory address register 58 which loads the cache with an address to be output onto bus 26 (in a manner not of interest to the present invention). be.

If the central processor is not stopped (i.e., when the STCP inverted signal is "high", the derivation of this signal is discussed below), then the address signal from memory address register 58 is
It is transferred to the cache 24 at the time of L0 (for timing signals that include L0, the 12th
(described in relation to the figure).

4-9 illustrate various types of data and address formats that are relevant to the operation of the data processing system.

FIG. 4 illustrates one byte of data, where one byte of data consists of eight bits. FIG. 5 illustrates a word of data, which word consists of 4 bytes or 32 bits. Figure 6 illustrates one double word, and the one double word is one
It consists of three even words and one odd word, each of 32 bits. Data is stored in main memory in doubleword units.

Figure 7 shows a 24-bit physical address as handled in main memory, which is a 12-bit page frame number (expandable by powers of 2 as memory is increased).
and an 11-bit offset that positions the byte within the page.

Figure 8 is the same as Figure 7 as interpreted in the cache.
It shows a 24-bit physical address, which consists of a 9-bit tag (index) and a 12-bit index. The lower 2 bits are ignored. The reason is that they are used to select one byte of a word, whereas the cache always transmits one word to the central processor, which then selects the particular byte needed. . The third bit from the right selects whether it is an even word or an odd word of a pair of double words. FIG. 9 illustrates the data format as it is stored in the cache. Each pair of even and odd words of a double word is stored with a 9-bit tag.
This set of 72 bits totals 12 of the physical addresses.
Addressed by bit index.

The use of indexes and tags to address direct-mapped caches is well known in the art in the art of data processing equipment. For general information on how to manage cache memory, see, for example, Computer Engineering by Bell, Matsuji, and McNamara, Digital Press, 1978.
(2013).

FIG. 10 shows a control signal storage device 14 containing control signals, which are accessed in groups of 48 output signals of 48 parallel lines. The signal on each line can be either "high (1)" or "low (0)," and the signal can be routed directly to central processor hardware circuitry to control the operation of central processor 12. applied.

The 48 signals on the line consist of microinstructions, only some of which are of interest to the present invention. The objects of interest are signals 0-6
(referred to as "micro OPCODE") and signal 22~
29 and the signals 0-16 are decoded together to determine the action to be performed (e.g.
signals 22-29 are decoded together to perform a memory operation (memory address register selection, memory data register selection read or write, etc.). (not relevant to the present invention).
These signals are shown in FIG. 2 as "memory control signals." Certain of the control signals accessed by the central processor are connected directly from the central processor to the cache and memory controllers and will be discussed in more detail below. Methods for accessing and decoding each group of these control signals (microinstructions) during operation of a data processing device are well known in this field as conventional techniques.
It will not be described here.

FIG. 11 shows the system master clock device 20.
The parts of interest of the present invention are shown. The master clock signal for the data processing device is driven by a 50 MHz crystal oscillator, the output of which is the input to a timing signal generation circuit 60, which performs the data processing of the present invention in a manner well known in the art. Generate appropriate timing signals for equipment systems. The basic timing signal (CLOCK) has a period of 40 nanoseconds (nS) and a pulse width of 20 nanoseconds (nS). Signal TA, TO, T1, T2; LA,
L0, L1, L2; CLOCK: and inverted CLOCK is the first
This is shown in the timing chart in Figure 2. These pulse signals are input to central processor 12.

Signals LA, L0, L1 and L2 are free-running signals without dependencies, while signals TA, T0, T1 and T2
are signals that depend on the operating state in the central processor and other devices. Additionally, L and T pulse signals may be generated under the conditions described below, but are not shown in FIG. 11 and are not of interest to the present invention.

Two gating signals GT1 and GT2 are generated in a manner that will be described more specifically later.
The GT1 signal is the central processor timing signal TA.
and gate (allow or disallow) T0,
The GT2 signal gates timing signals T1 and T2. The central processor cycle is defined starting from the TA pulse signal. Therefore, the operation of the central processor can be stopped after the T0 pulse signal or after the T2 pulse signal. The GT2 signal is subordinated to the GT1 signal, but in the manner described later, if a (cache miss) signal occurs, the GT2 signal is inhibited and pulses T1 and T2 cannot occur, even if pulses TA and T0 Even if it occurs.

The central processor microinstruction cycle length varies depending on the nature of the microinstruction. A central processor cycle (of arbitrary length) is defined starting from pulse TA. Most microinstructions that involve memory operations and are of interest to the present invention require 160 nanoseconds to execute. For these microinstructions, pulse signals TA, T0, T1 and
T2 forms a cycle as shown in FIG.
Other instructions require longer than 160 nanoseconds for execution, and additional T-pulse signals must be generated for such instructions (T5-T8, not shown). To determine the number of T-pulse signals to be generated, the current microinstruction control signals 0-6 (“Micro
OPCODE) is sent from the central processor 12 to the decoder and counter 6 in response to the CLOCK signal from the circuit 60.
2, the counter is set based on the nature of the operation determined by the decoder, and at the appropriate time a signal COB (end of cycle) is generated to indicate completion of a microinstruction cycle. This COB signal resets circuit 60 and causes the next cycle starting at the TA pulse signal. and generates a signal synchronized with the T pulse signal. However, if gate signals GT1 and GT2 are not specifically indicated, the T-pulse signal within the cache and memory controller will not stop when the central processor stops.

A cache cycle is the same length as a central processor read or write cycle, or 160 nanoseconds. However, the cache cycle is L1
Pulses L1, L2, LA and
L0, which means that the cache cycle is offset every 60 nanoseconds from the central processor cycle, as seen in FIG. The memory control cycle is offset every 40 nanoseconds from the central processor cycle, and the memory control cycle is pulsed T0, T1,
Consists of T2 and TA.

Additionally, certain timing pulse signals are applied directly to cache 24 from the central processor to cause events to occur that are synchronized with particular central processor events. Such a cash event is
This cannot occur if the central processor is stopped even if the cache is not stopped.

13, 14, 15, 17, 18, and 20, cache 24 generally includes an addressing section (FIG. 13), a data storage and tag comparison circuit section (FIG. 14), and FIG. ), and various control signal decoding circuits (Figures 15, 17,
18 and 20). Although the circuitry shown in FIG. 16 and some portions of the circuitry shown in FIG. 15 are physically located inside the cache, they are conceptually part of the memory controller because they This is because the function is related to main memory management.

Referring first to FIG. 18, the address of the central processor (not shown in this figure) arrives at cache 24 along with control signals CM22-29 of the 48 signal group that control current central processor operation. As previously mentioned, control signals 22-29 are memory access control signals that control the nature of memory operations to be performed at addresses defined by the central processor. For convenience in use in the cache 24, some of the control signals are delayed by being latched or buffered, and the delayed signals are designated as "CCM" based on their delay, as shown in FIG. ”, “BCM”, “LCM”
or designated as “MCM”.

Referring to FIG. 16, memory control device 1
8 is provided with a main memory access priority determination circuit 140. This circuit is designed to give main memory access priority to any bus adapter request (on behalf of a peripheral processor). Central processor 12 gains access to main memory for either writes or reads after a cache miss only when a bus adapter memory request is not in progress. The input signal LC (last cycle) arrives from the timing circuit of the memory control device shown in FIG. 15, which will be described later, and is generated at the end of the memory access operation. At the completion of any current memory operation, if no bus adapter memory request is being processed, the default signal BA goes low, causing the address of the pending central processor to be transmitted to main memory 16. Ru. Therefore, there may be a cycle delay after a cache miss until main memory is available to the central processor. During this time, the central processor remains in a stopped state, which will be discussed later.

This prioritization of main memory accesses between the central processor and the bus adapters, conditioned by the presence or absence of bus adapter memory requests, results from the division of cache cycles between central processor memory reads and other operations. must be clearly distinguished, but this will be discussed in detail later. The cache cycle splitting circuit is a free running operation with no dependencies from other devices and operates in such a way that it is determined whether any request of either the central processor or the bus adapter is being processed.

Regarding Figure 17, "BA enable"
The signal indicates that the memory control circuit is ready.
R/B) is generated by a flip-flop internal to enable circuit 142 at time TA in response to any bus adapter memory request (MRBA). The BA enable signal is applied to the circuit shown in FIG.
input the address of the BA memory operation for (proceduve).

The timing signal of the main memory 16 is mainly the first
It is generated by the circuit shown in FIG. 5, the main part of which is a functional part of the memory controller 18. The timing and method of operation of main memories for data processing devices of the type described herein are generally well understood in the art and do not form a feature of the present invention. Therefore, the method of generating the timing signal will not be described in detail, but the parts related to the present invention will be described.

Regarding FIG. 15, the control signal CCM2
2-29 (from FIG. 18) is the decoder circuit 138
to determine whether the central processor's memory operation is a write or a read. If the memory operation is a read, the decoded control signal generates a ``READ'' signal, which indicates that the central processor memory operation is a read, and is used in the cache. This "READ" signal is required internally to cache 24 and enables the cache miss signal to be discussed later.

If the central processor's memory operation is a write (to main memory), the decoded control signal
CCMs 22-29 provide write signals WRITE8 (ie, bits), WRITE32, and WRITE64, which define write operations of one byte, one word, or one doubleword. (The write signal WRITE16 is not generated as a control signal for the central processor because, unlike the peripheral processors, the central processor does not write half words.) (Memory access control signal) from bus adapter 22 BAC 0
-2 is decoded in operation decoder 139 in a manner similar to that described above to derive a read or write signal as input to circuit 138. The write signal of the bus adapter is WRITE8, WRITE16, WRITE32 or
It can be WRITE64. The MRBA (Bus Adapter Memory Request) signal is also an input from bus adapter 22.

The CP/BA input signals (from Figure 16) indicate priorities for main memory accesses. (CP can be "high" when the central processor has priority;
When peripheral processors have priority
BA can be "high". ) When a cache miss is satisfied by a main memory operation and the requested data is placed in the central processor's memory data register (FIG. 3), a cache miss clear signal is generated within cache 24 in the manner described below. be done. As can be seen from Figure 15, the "MOP (memory operation)" signal is the bus adapter memory operation (BBAC1, BBAC2 and BA priority).
or central processor memory operations (MCMs 24 and 25, and CP priority).

Circuit 138 generates appropriate memory control and timing signals from the aforementioned input signals. Control signals “WRITE8”, “WRITE16”, “WRITE32”
and "WRITE64" have already been described, but the "READ64B" control signal is a signal that defines the read operation of one double word. R.W.
(READ/WRITE: Read when R is “high”,
The WRITE signal and the WRITE pulse signal are conventional input signals to the main memory 16. Memory timing signals are CAS (column address strobe), CEN (column enable)
and RAS (row address strobe), all of which are conventional signals and are input signals to main memory 16 for addressing main memory 16 in a manner known in the art.

Signals C1, C2, and C3 are used internally within the cache and are used for the three instruction cycles required for main memory operations (each
160 nanoseconds) to maintain order. How these signals are used will be discussed later. Signal LC (Last Cycle) is 160 nanoseconds long and is typically synchronized to the last cycle of memory operations. The LC signal is the reset input signal for flip-flop 141, which defers the CP priority signal (from FIG. 16) to provide a Latched CP (LCP) signal, the use of which will be described below. Flip-flop 137 is used to delay the cache miss signal during central processor read operations and provides a "MISS EXT" (inverted) output signal, the use of which will be described below.

The inverted cache miss signal is normally “high” and
The STCP (Stop Central Processor) signal, which is the output signal from flip-flop 135 which is normally "high", is maintained. The STCP inverted signal is an input signal to the master clock device (Figure 11) and is also an input signal to the central processor's memory address register 58.
(Fig. 3). As long as the STCP inversion signal is "high", the central processor is not stopped and the timing pulse signals TA, T0, T1 and T2
is generated and gated as the output of the central processor's memory address register 558. 14th
When a cache miss signal is generated in the manner described in connection with the figure, the cache miss inversion signal goes "low" and on the next L1 timing pulse signal (the L0 inversion signal is "low") the STCP
The inverted output signal goes "low". This signal stops generating the T-pulse signal for the central processor and also prevents the memory address from unlatching to the cache.

FIG. 13 depicts certain portions of cache 24 that are particularly relevant to cache storage addressing and main memory addressing. This circuit divides the cache cycle and provides divided alternating cache subcycles to perform specific functions. A first cache subcycle is provided for processing read addresses of the central processor, and a second cache subcycle is provided for processing read addresses of the bus adapter for checking the cache or for writing to the cache. Used for any of the following: A write to the cache may include writing the invalid bit of a particular cache entry after a cache check (performed in a previous cycle) has determined that a tag match condition exists, or a cache miss may occur with respect to main memory 16. It may involve either writing to the cache data store and tags to update the cache after completion of a write to the central processor's main memory that is not satisfied.

The circuit shown in Figure 13 accepts addresses from two sources. One address (MA 0-
23) is accepted from the central processor 12 for memory operations (read or write) and the other address (BMA
0-23) are accepted from bus adapter 22 for cache verification or invalidation operations. The circuit shown in FIG. 13 decides to output the address to the comparator circuit shown in FIG. 14 to be compared, and also decides to output the address to main memory 16 for memory operations. Generally, this circuit includes multiplexers 102 and 104 for selecting the index and tag to be applied to the cache storage and the comparator circuit shown in FIG. Latch circuit 11 for holding
0 and 108, and a multiplexer 112 for selecting the address to be sent to main memory for a memory operation.

It should be noted that the circuit shown in FIG. 13 operates regardless of whether the central processor's memory operations are read or written. The "READ" signal from the circuit of FIG. 15 is an input signal to the circuit of FIG. 14, and the cache miss signal can be generated only for read operations. For central processor write operations, all operations are performed until a cache miss signal is generated, and no cache miss signal is generated. This is because, according to the present invention, this subcycle is used to process the address of the central processor's memory operations, and no other operations can be performed during the execution of this subcycle. , so these "wasted" operations do not waste time.

Continuing to discuss Figure 13, bus 26
is the address line MA0- from the memory address register 58 (FIG. 3) of the central processor 12.
23, and the address line is latched at time L0, which provides when the central processor is not stopped (STCP inverted signal is "high"). Bus 32 carries address lines BMA0-23 from bus adapter 22. bus adapter 2
2 is stored in the latch circuit 100, and the address from the latch circuit 100 is stored in the BA from the circuit of FIG.
Gated (at time TA) by an enable signal.

Regarding the signals arriving at the central processor address bus 26, lines 9-20 (carrying signals consisting of the index, see FIG. 8) are inputs to the index multiplexer selection circuit 102, and lines 0-8 (carrying signals consisting of the index, see FIG. 8) are inputs to the index multiplexer selection circuit 102; The tag (see FIG. 8) is an input to the tag multiplexer selection circuit 104. The signal arriving at the bus adapter address bus 32 is the input of the buffer circuit 106 and is the “BA write” from the bus adapter 22.
(BBAC1) signal and is split into the same signals as above, lines 0-8 (tag)
is the input to tag multiplexer 104 and line 9-20 is the input signal to index multiplexer 102.

The input signal to the index multiplexer selection circuit 102 is selected by the timing signal T12, and the input signal to the tag multiplexer selection circuit 104 is selected by the T12 inverted timing signal. Therefore, multiplexer selection circuits 102 and 104 are switched simultaneously but in opposite states, and the central processor index is transmitted by multiplexer selection circuit 102 when the bus adapter tag is transmitted by multiplexer selection circuit 104. Referring to the timing chart of FIG. 12, it can be seen that signal T12 is "high" during the period that signals T1 and T2 are "high", so the pulse time width of signal T12 is 80 nanoseconds.

Therefore multiplexer selection circuits 102 and 1
04 is each individual cache cycle (160 nanoseconds)
It is switched twice between. During the first half of the cache cycle, the A input signal to index multiplexer select circuit 102 (central processor index) is transmitted to cache address latch circuit 114, and during the second half cycle, B
An input signal is transmitted. This B input signal is used by buffer circuit 1 to check the cache (BA priority state while the peripheral processor writes to main memory).
bus adapter address from 06, the same bus adapter address as above (held in buffer circuit 106) for invalid bit writing (after the previous cache check resulted in a tag match condition), or the center (from latch circuit 108). It can be any of the processor's pre-address input signals. The central processor's pre-address inputs are either for memory read operations that result in cache misses, or for central processor memory write operations; in either case, this address is used for cache updates. It should be used as the address for write operations.

During the first cache subcycle, the B input signal to the tag multiplexer selection circuit 104 inputs the tag latch circuit 1 to the tag comparator (FIG. 14).
16, and during the second cache subcycle, the multiplexer select circuit 1
The A input signal to 04 is transmitted to latch circuit 116. The purpose of this timing arrangement will be described later.

The cache address latch circuit 114 is latched by the "Address Clock (L1 LA)" signal, and the tag latch select circuit 116 is latched by the "Tag Clock Inversion (L1 LA)" signal.

For each memory operation in main memory (including cache updates after a cache miss), one address must be selected for application to main memory 16 for the memory operation. For each operation of the central processor, whether a memory operation or other type of operation, the central processor's addresses (MA0-23) are stored in latch circuit 11.
0 through the timing signal T2 (central processor 1
When GT2 is not stopped, the GT2 signal is provided as "high") and the address is applied to main memory address multiplexer 112 and latch circuit 108. If the operation is not a memory operation, or if it is a memory read operation and a cache is present, latch circuit 10
The content of item 8 is never used. If a cache miss exists, signals CP (central processor memory access cycle from Figure 16), T1 and C
1 (cycle 1 from FIG. 15, the first cycle of memory operations that satisfy cache misses) is
Cache data storage 1 for gating addresses through latch circuit 108 to multiplexer 102 and updating writes after completion of memory cycle.
24. The tag part of the address is output as TW0-8 in order to be written into the cache storage section which will be described later.

Since the central processor is halted in response to a cache miss after the interval timing signal T0 of that cycle, before being halted by the cache miss signal (described below), the central processor may preload other addresses for memory reads into the cache ( signal
between TA and T0). This address cannot be lost because it can be stored in the latch circuit 110 and the latch circuit cannot be used for the next T2 after the cache miss signal is cleared.
This is because it cannot be gated until the timing signal is generated. Therefore, during a main memory operation that satisfies a cache miss, latch circuit 110 holds the address for the next memory operation;
8 holds the address exactly at which a cache miss occurs and which reaches main memory for the current action. When a memory operation is complete and data is to be written into the cache, the cache write index is activated by the cache address latch circuit 108.
obtained from. The tag should be written to the cache tag storage unit 120 at the same time as described above.
(Tag write) This is an input of 0-8.

The alternating input signal to main memory address multiplexer 120 is selected by signal BA ("high" or "low") from the priority circuit shown in FIG.
The selected address signal (BMAR3-20, with module selection signals not of interest to the present invention) is the output that addresses main memory 16 (FIG. 19) and memory controller 18 (CMA0-
23). The memory controller uses address signals to maintain a bus transaction log and for other purposes, but this is not of interest to the present invention.

FIG. 14 shows the storage section of the cache. This drawing is a simplified representation and does not show that the cache, which is not involved in the operation of the present invention, is actually divided into even and odd parts. Regarding the effect of the cache storage section, only one of the storage sections is shown. To make the even/odd arrangement of the cache visible, the circuit of FIG. 14 up to flip-flop 130 can be considered to represent either the even or odd part of the cache, with the remaining parts not shown. The output signal of the other similar structure is also the input signal to the 1-bit flip-flop 130 to provide a single cache miss signal. .

The data storage section 124 is a random access memory (RAM) that stores cache entries, the tag storage section 120 stores cooperating 9-bit tags, and the invalid bit storage section 122 stores cooperative invalid bits. do. The aforementioned circuit element 12
4, 122, and 120 are all addressed by a 12-bit index from cache address latch circuit 114 (FIG. 13) and input by "address clock" timing signals (L1, LA) (FIG. 13). The tag portion of the cache entry is read to tag latch circuit 134. The word portion of the cache entry is read out to data latch circuit 126 at the same time as described above.

The tag latch circuit 134 is controlled by the "tag latch enable" signal (timing signal L0+L2, trailing edge of the active pulse) and transfers the stored tag to the tag register 132.
Transmit to. The address tag sections selected in multiplexer 104 and represented as CWA0-8 are used for comparison as "tag clock inversion (inversion L1)".
is the input signal to the tag comparator 132 sent from the latch circuit 116 by the ``LA'' signal. If the tags are equal, the comparator's miss-hit output signal is "low"; if the tags are not equal, the output signal is "high". This output signal is the input signal to a 1-bit flip-flop 130, which is ``misclocked'' for central processor memory read operations only, as controlled by the ``READ'' signal from the circuit of FIG. LA)” signal. Central processor memory write operation or BA
No cache miss or cache miss inversion signal is generated in the address subcycle. Comparator 13 before input to flip-flop 130
The missed bits from 2 are ORed with the stored invalid bits from storage 122. Therefore, for a central processor memory read, either a tag mismatch condition or an invalid bit will cause a cache miss as indicated in the cache miss signal (status signal).

The miss hit signal is an input to the flip-flop 137 shown in FIG.
Extended)” inverted signal (during read operations only).

Data from the data storage section 124 is unlatched from the data latch circuit 126 and sent to the buffer circuit 128 by the "data latch enable" signal (L1 L2). If the tags are equal and indicate that the data entry from buffer circuit 128 is valid, buffer circuit 1
Data from 28 is placed directly on bus 40 to memory address register 1 of central processor 12.
5 (FIG. 3), and the flip-flop 13
The cache miss expansion inversion signal from 7 is sent to the buffer circuit 12 which enables the latch circuit (Fig. 2).
8 is not enabled.

The missed hit bit from tag comparator 132 is also an input signal for setting flip-flop 146. During subsequent cache cycles, the details of which will be described in connection with FIG.
The invalid bit to be written at the time the current address is applied to the memory from 8 is applied to the data input of the cache's invalid state memory 122.

Since the data latch enable signal is "high" only during the first cache operation subcycle, the cache error,
For invalid writes or write cache data operations, data is unlatched and cannot be sent to central processor 12.

Referring to FIG. 11, as previously stated, the cache miss signal causes the central processor to stall with the GT2 response signal inhibiting timing signals T1 and T2. Therefore, the central processor is stopped after the timing pulse signal T0. If the bus adapter is not requesting main memory access, the priority circuit shown in Figure 16 will signal
Generates CP・(inverted BA). Cash misses can be instantly gratified.

To satisfy central processor read requests for cache misses, module select bits (not shown) and address signals BMAR3-20 (first
3) is sent to main memory 16 (FIG. 19) along with the timing and control signals from FIG. 15 to select the addressed doubleword. Three instruction cycles are required to complete the main memory access. The double word is placed on bus 44 through memory controller 18 and then transferred to CP data latch circuit 54 (FIG. 2).
The cache miss extension signal sends the data to the memory data register 56 (first
(Fig. 3).

The cache miss signal is used for memory read operations involving the central processor (LC, LCM24, and
LCP: LCM24 is a latched memory control signal CM24 from the circuit of FIG. 18, which is always "high" for read operations),
When the memory timing circuit shown in the figure determines that the last of the two cycles required for the main memory operation cycle has been reached, signal L0
It is cleared in (Figure 14). Both of these signals mentioned above are called the "clear miss" signal, which is also the input signal to the circuit shown in FIG. 15, which clears the "READ" signal.

In response to a cleared cache miss signal (the cache miss inversion signal goes high),
The STCP (stop central processor) signal is inverted at time L0 (FIG. 15, flip-flop 135). Referring again to FIG. 11, when the cache miss inversion signal goes high, the GT2 signal allows pulses T1 and T2 to be output to the central processor and the central processor operates again in the intermediate cycle. Signal GT1 then allows pulses TA and T0 to be output. The central processor then continues to operate until another cache miss occurs (or a memory write operation occurs, which is not of interest to the present invention).

In more detail with reference to the timing chart of FIG. 23, the STCP inversion signal is normally "high". This STCP inversion signal is used when the central processor (not described here) writes to the main memory or when the flip-flop 1, as shown in FIG.
30 (FIG. 14).
The STCP inversion signal goes "low" at time L1. As can be seen from Figure 11, the STCP inversion signal is
Flip-flop 61 to clear GT1 signal
input, and when the STCP inverted signal goes “low”
The GT1 invert signal is forced low to inhibit output of signals TA and T0 to central processor 12, and then signal GT1 is forced high.

When the cache miss signal is not present (i.e., in the case of a central processor write operation to main memory)
In this case, the GT1 signal is the input to the D terminal of the flip-flop 63 that generates the GT2 signal,
Then on the next L0 pulse, the GT2 inversion signal goes low, inhibiting the next T1 and T2 pulses from being output to the central processor. When the STCP inverted signal goes high again in the L1 pulse (after the write operation is initiated), the GT1 inverted signal goes high in the L2 pulse (timing pulse
TA and T0 are enabled), the GT2 inversion signal goes high on the next L0 pulse (timing pulses T1 and T2 are enabled). Therefore, in the case of a write operation to the main memory, the central processor 12 is stopped at the timing pulse TA and restarted at this pulse.

If the central processor is stopped by the cache miss signal, the cache miss signal will not be generated until the L0 pulse, which is in the middle of the TA pulse, arrives. Therefore, in this case, different stop times (and operational recovery timings) must be provided. For this purpose, the cache miss signal is ANDed with the GT1 signal as the input signal to the D terminal of flip-flop 63 of the GT2 signal, and the cache miss signal is also ANDed with the GT2 inverted output of flip-flop 63. GT2 is therefore gated when the cache miss inversion signal goes "low".
A signal is forced high, inhibiting the output of pulses T1 and T2 and stopping the central processor in the middle of an instruction cycle. The GT1 inversion signal is then followed by the STCP signal (at the L1 pulse)
I am forced to set it to “low”.

During the time TA of the second cache subcycle in the last main memory cycle (as described below), the cache miss signal from flip-flop 130 is cleared after the cache data storage signal is written and the cache update is complete. (14th
figure). The cache miss inversion signal goes high at pulse L0, and the STCP inversion signal goes high at pulse L1.
It becomes "high" at (Figure 15). The GT2 inversion signal changes due to a change in the cache miss signal.
On the L0 pulse, the GT1 inverted signal is forced "low" to allow timing pulses T1 and T2 to be output to the central processor 12, and then on the L2 pulse, the GT1 inverted signal goes "high" and pulses TA and T0 are output. Allow. therefore
When the GT1 signal stops, the central processor command cycle restarts in an intermediate cycle.

The cache data store is updated by cache write operations after a cache miss or during a central processor memory write operation.

Referring to FIG. 20, cache write circuit 1
50 controls writing of the cache contents after a cache miss, and also controls writing of the cache invalid bit after the tags match in BA address comparison. (INVERTED) INVALID BIT (FIG. 14, from flip-flop 146) is an input signal to cache write circuit 150 for writing an invalid bit. Control signal LCM24 and write control signal
WRITE8, WRITE16 or WRITE64 (first
5) are input signals for writing to the cache data store.

As discussed in connection with FIG. 23, cache data store writes occur at different times during main memory write or read operations. All writes occur during time TA, subcycle B of the cache operation cycle. For main memory write operations, a write pulse is present as an output at time TA of memory cycles C1 and C2 (FIG. 15), while for main memory read operations (cache update), a write pulse is present as an output at time TA of memory cycles C1 and C2 (FIG. 15), while for main memory read operations (cache update), memory cycle 3 (LC , last cycle) at time TA. During any main memory cycle, writing of the invalid bit also occurs at time TA.
Because all writes occur during the second subcycle of the cache operation cycle, cache write operations cannot interfere with the central processor's acceptance of memory read requests during the first cache subcycle.

The cache write pulse is sent to the tag storage section 120, the invalid storage section 122, and the data storage section 124 (fourteenth
exists as an appropriate input for Figure).

Providing cache subcycles for specific functions as described above, and more specifically providing a first subcycle solely for accepting central processor memory read requests, is useful for memory read operations. The result is that the address of the central processor for is always accepted once in each cache cycle to compare its tag with the contents of the cache. If the cache is present, the requested data is returned to the central processor during the TA period of the next central processor microinstruction cycle. Therefore, the central processor can proceed without interruption.

If a cache miss exists, the central processor may be stalled and forced to wait several cycles until main memory access is obtained, which only occurs when there is no contention for bus adapter access. . Once the data is available from main memory, it is immediately provided to the central processor during the second subcycle of the cache cycle, and the central processor begins operating again in response to the cache miss flipping high. The central processor then restarts in some manner of operation as if the cache were present. The cache data store is written to during the second cache subcycle after the central processor resumes operation.

The cache is checked for bus adapter tag matches only during the second subcycle of the cache operation cycle. If a tag match condition exists, flip-flop 146 is set and in the next second subcycle (after the central processor has had an opportunity to enter a memory read request) the invalid bit at the matched address is transferred to cache write logic 150. (Figure 20).
causing subsequent attempts by the central processor to read the location in the cache to generate a cache miss signal;
The cache may be updated as described above.

As a result of providing this cache operation subcycle, cache writes (to write an invalid bit, to update a doubleword in response to a cache miss, or to update the cache after writing to the central processor's main memory) either) exists "separately" from the central processor's memory read operations. The central processor is never required to wait while such writes occur. In particular, unlike the circuit layout of many data processing devices that use cache memory,
There are no "dedicated" cache cycles required in conventional data processing systems to update before the central processor can resume operation after a cache miss. Additionally, the central processor can immediately (on the next microinstruction cycle) read the just updated location after a cache miss. Anomalies can occur if the central processor attempts to read a location on which it has just performed a main memory write operation, but this situation is easily avoided by appropriate precautions in the microprogramming of the central processor.

The operation of the data processing apparatus of the present invention will be described below with reference to the timing charts of FIGS. 21, 22, and 23.

Referring first to FIG. 21, this figure illustrates the events of a central processor memory read operation.

The central processor memory read microinstruction begins at time TA and ends at time T2. At the positive edge of the LA inversion signal, the address is set to the memory address register 58 (FIG. 3).
and to the cache 24. While the T12 signal is "low", the A input signal to multiplexer 102 (FIG. 13) is selected to send the central processor index to cache address latch circuit 114. The ``Address Clock'' (L1, LA) signal goes ``high'' on the L1 pulse, transmitting the central processor index from latch circuit 114 to address the cache store (FIG. 14). In response, data is present as an output from data storage 124 and is unlatched from data latch circuit 126 during signals L1 and L2 (80 nanoseconds). This data is stored in the central processor's memory data register 56 at time TA.
(Figure 3). In the case of a cache, the central processor continues without interruption to the next microinstruction cycle.

T12 signal becomes “high” and T12 inversion signal becomes “low”
, A to the tag selection multiplexer 104
The input signal (central processor tag) is selected and transmitted to the tag select latch circuit 116. "Tag clock inversion" (inversion L1, inversion LA)
The signal latches the tag output to comparator 132 (FIG. 14). In response to the input index from the latch circuit 114, the stored tag is present as an output from the tag storage section 120 at the same time as the data is stored, and the "tag latch enable" (L0, L2) is activated.
The tag in which the falling edge of the signal is stored is connected to comparator 1.
32. The miss output signal of comparator 132 is the input signal to flip-flop 130, which is sampled by the LA inverted (miss clock) signal. In the case of a cache miss, the cache miss signal, which is the input signal to flip-flop 135 (FIG. 15), inverts the STCP signal at the L0 inversion signal.

As can be seen in FIG. 21, the cache miss signal is generated only after cache data has been sent to the memory data registers of central processor 12. If there are no cache misses, the central processor continues processing its data. If a cache miss exists, the central processor can be halted after the T0 signal (described below in connection with Figure 23) and the data restored by a main memory read operation before central processor operation resumes. obtain.

Referring to FIG. 22, this figure illustrates cache checking and override operations. These operations are only initiated when the bus adapter (peripheral processor) writes to main memory. For this kind of operation, the bus adapter
The MRBA signal is sent to the circuit shown in FIGS. 6 and 17, which generates the BA priority signal and the BA enable signal. BA enable signal is TA
Goes "high" at the signal. Main memory operation is T0
The first cycle starts from cycle 1 (C1) in the signal.
It is activated by the circuit shown in Figure 5. Memory access control signal BAC1 is latched as mnemonic BBAC1 when a memory operation begins. When the T1 and T2 signals are "high", multiplexer 10
The B input (BA index) signal to the cache address circuit 114 is latched and output to the cache address circuit 114. "Address clock" (L1, LA) signal is BA
Output the index to the cache store (Figure 14). No data is transmitted to the central processor.

When the T1 and T2 inverted signals go high, the B input (BA tag) signal to multiplexer 104 is selected and the selected BA tag signal is transmitted to tag select latch circuit 116. "Tag clock inversion"
The (L1, LA) signal latches the tag output to comparator 132. The stored tag is unlatched from the tag latch circuit 134 and sent to the comparator 134 by the "tag latch enable" (L0, L2) signal. The missed bit is the input to the invalid flip-flop 146 (FIG. 14), which is sampled by the ``invalid clock'' signal at time L2. In tag matching state,
The INV inverted output signal (which is normally ``high'') goes ``low''.

The INV inversion signal is an input to the cache write circuit shown in FIG. 20, and causes a write cache pulse to be output during the TA time. When the write cache pulse is present as an input, the INV output signal of flip-flop 146 is present as a data input to invalid bit store 122 (FIG. 14). The address at the time the INV signal is written is the same as the address at the time the tag match condition was found, because the address is
Buffer circuit 10 through BA main memory write operation
6 (the BA address cannot be entered any further until the memory operation is complete, and may be entered after multiple cache operation cycles). This does not pose a problem since in reality the invalid write operation may be repeated during each individual cache cycle through the main memory operation. It should be noted that during all BA main memory operations, including invalid write operations, central processor operations continue to take the opportunity on each individual cache cycle to read the cache. If a central processor's read operation does not result in a cache miss condition, the central processor
If the BA main memory operation must be stopped after completion and no other BA memory operation is in progress, the central processor can be given priority for the memory operation by the circuit shown in FIG. Main memory reads and cache updates can proceed.

FIG. 23 shows cache misses and updates. Cash miss inversion signal is time
It goes "low" at time L0 (FIG. 14), and the STCP inversion signal goes "low" at time L1 (FIG. 15). Central processor 12 is stopped after time T0. Main memory operations are initiated by cycle 1 (C1) at time T0. Main memory operation is 3
The memory is written to during cycles one and two and read during cycle three. A cache write pulse that updates the cache store after a cache miss is generated during the last cycle (C3) because main memory must be read before the cache store is written to. It is. During the last main memory cycle, the cache miss signal goes high again at time L0 and the STCP signal goes high at time L1. The central processor pulses T
It is restarted at 1.

For central processor memory writes, cache write pulses are used during cycles 1 and 2, time TA.
The central processor is restarted after the start of the memory operation. Central processor 12 can therefore read the cache during each individual subcycle A while write cache operations continue during subcycle B.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram of a data processing device system having a data processing device according to the present invention;
1, FIG. 3 is a diagram showing a portion of the central processor in the data processing device shown in FIG. 1 related to the present invention, and FIGS. FIG. 9 is a diagram illustrating various data and address formats related to the present invention, FIG. 10 is a diagram showing a portion of the control signal storage device shown in FIG. 1 related to the present invention, and FIG. 12 is a diagram showing the basic system timing signals generated by the master clock circuit of FIG. 11, and FIG. 13 is a diagram showing the cache memory address function related to the addressing function of the present invention. 14 shows a portion of the cache related to data storage of the present invention; FIG. 15 shows a portion of the cache related to memory control and other control functions of the present invention; FIG. 16 shows a portion of the cache related to memory control and other control functions of the present invention; 17 is a diagram showing a part of a circuit related to the memory access priority of the present invention, FIG. 17 is a diagram showing a cache circuit that generates a control signal for memory operation of a peripheral device processor,
FIG. 18 is a diagram illustrating cache circuitry related to the use of certain control storage signals in the cache of the present invention; FIG. 19 is a diagram illustrating main memory as an embodiment of the present invention; FIG. A diagram illustrating a cache write logic circuit as an embodiment of the present invention;
FIGS. 21 to 23 are timing charts partially showing the operation of the data processing apparatus of the present invention. Explanation of symbols: 10...Data processing device, 12...Central processor, 14...Control signal storage device, 16...
Main memory, 18... Memory control device, 20... Master clock device, 22... Bus adapter, 24... Cache, 54... Data latch circuit, 56... Memory data register, 58... Memory address register, 60... Timing generation circuit, 62... Decoder and counter.

Claims (1)

[Scope of Claims] 1. A cache memory included in a data processing device including a main memory for storing data and a processor for processing data, wherein the cache memory includes: cache storage means for storing a copy of a portion of the stored data; cache control means for receiving read and write requests from said processor and providing addresses corresponding to certain requests to a memory controller; and said cache control means. cache transfer means for transferring data from the memory controller to the cache storage means in response to activation of the memory controller; controller control means for providing outputs for control operations of the memory; controller transfer means for transferring read data from said main memory to cache storage means and transferring write data from said processor directly to main memory; The controller control means includes timing means for defining a cache memory operation cycle consisting of a first subcycle and a second subcycle, and the cache control means and the controller control means are configured to control the timing means. In response, the first
accepts and processes only processor read requests during the first subcycle and operates to resolve conflicts between all other cache and memory operation requests during the second subcycle; A cache memory characterized by: 2. The cash register as set forth in claim 1.
In the memory, the cache control means provides a corresponding write address to the controller solely in response to a processor data write request received during a first subcycle, thereby causing a subsequent second A cache memory characterized in that during a subcycle, a write operation of processor data from a processor directly to main memory is initiated through the memory controller. 3. The cash register as set forth in claim 1.
In the memory, the cache control means, in response to a processor read request for data not included in the copy in the cache storage means received during the first subcycle, generates a responsive read address. a cache memory controller, thereby initiating a corresponding read operation from the main memory through said memory controller to the cache storage means during a subsequent second subcycle. . 4. The cash register as set forth in claim 3.
a memory, said memory controller transfer means further communicating directly to the processor data provided from said main memory to said cache storage means during said corresponding read operation in response to actuation of said controller control means; A cache memory comprising means for. 5. The cash register as set forth in claim 1.
a memory, wherein the data processing device further includes one or more peripheral processors, and the cache memory is within the cache control means to read and write peripheral processor addresses in response to peripheral read and write addresses. and means for transmitting data between a peripheral processor and a main memory within the controller transfer means, and the controller control means further includes a means for transmitting data between a peripheral processor and a main memory. A cache memory characterized in that it responsively transfers data between a peripheral processor and a main memory. 6. The cash register as set forth in claim 5.
a memory, said cache control means responsive to a peripheral address referencing data contained in a copy residing within said cache storage means;
A cache memory, characterized in that it provides an output to said controller control means for initiating reading of a new copy of data referenced to said cache storage means from said main memory.