JPH0322054A - Cache circuit - Google Patents

Abstract

PURPOSE:To shorten the block update time by starting the access to a main storage device in parallel with the start of access to a cache at the time of data read and holding data read from the main storage device in a load buffer. CONSTITUTION:When a data read request is received from a processor 10, data in data memories 1A and 1B and address tags 2A and 2B are read out by the address from the processor 10. In parallel with this data read, the access to a main storage device 20 is started by the address from the processor 10 and data read out from the main storage device 20 is written in a load buffer 7. Outputs of address tags 2A and 2B are compared with the address from the processor 10 by comparators 3A and 3B to discriminate hit/mishit. Thus, the block update time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache circuit, and particularly to a read-through type cache circuit.

[Conventional technology]

Conventionally, this type of cache circuit has the circuit block structure shown in FIG. 3, and operates as shown in the flowchart shown in FIG. 4.

When there is a data/read request, a cache access is performed and the comparator 3A compares the address of the address tags 2A, 2B with the address input from the processor 10.
3B, and after a mishit is found, data reading from the main storage device 20 is started in order to update the block according to LRU bit 4.

[Problem to be solved by the invention]

The conventional cache circuit described above does not read data from the main storage device 20 after a cache miss is detected.
Since the structure is such that block updating is started, there is a drawback that the block updating time is long.

An object of the present invention is to provide a cache circuit that can shorten block update time.

[Means to solve the problem]

The cache circuit of the present invention includes a data memory that stores a part of data in a main memory and reads data from an address designated by a processor, and a data memory that stores part of data in the main memory and reads data from an address specified by a processor. an address tag that holds an address and a valid bit indicating the validity of data; a comparator that compares the output of the address tag with an address from the processor to determine cache hit/miss; an LRU bit that indicates a book to be rewritten in the event of a hit; a selector that selects and outputs the hit data from the data memory; and a selector that temporarily holds the data read from the address of the main memory specified by the processor It has a load buffer for writing into memory, and a control section that stops access to the main storage device after the data from the selector is transmitted to the processor, and controls the operation of each section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, data memories IA and IB which store part of the data in the main memory 20 and read data from addresses designated by the processor IO, and data memories LA and le which store part of the data, are used. Main storage device 2
Address tag 2A, '2B that holds an address on 0 and a valid bit indicating the validity of the data, and this address tag 2A, 2! ! Comparators 3A and 3B compare the output from the processor 10 with the address from the processor 10 to determine cache hit/miss, the LRU bit indicating the block to be rewritten in the event of a cache miss, and the hit data memory (2A. 2B). ), an input/output controller 6 that transmits the data from the selector 5 to the processor 10, and a data read from the address of the main storage device 20 specified by the processor 10, which temporarily outputs the data Holding data memory IA, 1. Load buffer 7 to be written to is selected by selector 5,
It has a structure including a control section 8 that stops access to the main storage device 20 through which data from the input/output controller 6 is transmitted to the processor, and controls the operation of each section.

Next, the operation of this embodiment will be explained.

FIG. 2 is a flow chart for explaining the operation of this embodiment.

When a data read request is received from the processor 10, data memories IA, IB and address tags 2A, 2 . data is read.

In parallel with this, access to the main memory device 20 is also started using the address from the processor IO side.

Data read from the main storage device 20 is written to the load buffer 7.

Address tag 2A, 2. The output is compared with the address from the processor IO side by comparators 3A and 3B to determine whether it is a hit or a miss. If there is a hit, data memo! Among the outputs of JIA, In, the data output on the hit side is selected by the selector 5, and the data is sent to the input/output controller 6. The input/output controller 6 sends the read data to the processor 10 side, and at the same time stops the access to the main storage device 20 that has been started.

In the case of a mishit, access to the main memory 20 is continued, and the first buffer 7 is accessed according to the output of LRU bit 4.
Update the block via

The data is then sent to the processor 10 side, and the cache access is completed.

〔Effect of the invention〕

As explained above, the present invention starts accessing the main storage device in parallel with starting access to the cache when reading data, and stores the data read from the main storage device in the load buffer. This has the effect of shortening the block update time when a cache miss occurs, and prevents an increase in cache access time by stopping the access to the main memory that has started when a cache hit occurs. There is an effect that it can be done.

Restag, 3A, 3B... Comparator, 4...
...LRU bit, 5.5A...Selector, 6
, 6A... Input/output controller, 7...
・Load buffer, 8, 8A...Control unit, 10
. . . Processor, 20 . . . Main storage device.

Claims (1)

[Claims] A data memory stores part of the data in the main memory and reads the data from an address specified by the processor, and the validity of the address and data on the main memory of the data stored in the data memory is read out from the address specified by the processor. an address tag that holds a valid bit indicated by the address tag; a comparator that compares the output of the address tag with the address from the processor to determine cache hit/miss; and L indicating a block to be rewritten in the event of a cache miss.
RU bit, a selector that selects and outputs hit data from the data memory, a load buffer that temporarily holds data read from the address of the main storage device designated by the processor and writes it to the data memory; A cache circuit comprising: a control section that stops access to the main storage device after data from a selector is transmitted to the processor, and controls operations of each section.