JPH03220650A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To continuously use all the addresses of a memory cell array by executing the write / read of data for confirmation to a diffused memory cell part provided near the memory cell array and confirming the effectivity of the data to be held by a backup power source. CONSTITUTION:Before switching to the backup power source, the data for confirmation stored in a non-volatile memory part 1 is written into a diffused memory cell part 2. Next, after switching to the backup power source, the data stored in the diffused memory cell part 2 is read out and compared with the data for confirmation from the non-volatile memory part 1. As a result, when the data are coincident, since the diffused memory cell part 2 is formed near a memory array 11 and the memory cells forming them are equipped with the almost same characteristics, it is judged that the data stored in the memory cell array 11 is effective. Thus, without making the address of the memory cell array 11 discontinuous or limiting the use, all the addresses can be used for normal data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a function of confirming the validity of data in a memory cell array backed up by a battery or the like.

[Conventional technology]

Conventionally, this type of semiconductor memory, as shown in FIG.
When the main power supply is cut off, the memory cell array 11 that retains stored data is powered by a backup power source such as a battery, and the data D
T's writing.

Row decoder 12 for reading. The storage unit includes an input/output circuit 13 and a column decoder 14].

In this semiconductor memory, when the main power is cut off and switched to a backup power source such as a battery, data stored in the memory cell array 11 is stored before switching to the backup power source in order to confirm the validity of the data. Confirmation data is written in the confirmation memory cell section 11X using a part of the memory cell array 11, and after switching to the backup power supply, the data is read out, and if it matches the confirmation data, the memory cell array It was determined that the data in 11 had been correctly backed up.

[Problem to be solved by the invention]

The conventional semiconductor memory described above has a memory cell array 11.
Since the configuration is such that the validity of the data in the memory cell array 11 after switching to the backup power supply is confirmed by the confirmation memory cell section 11X using a part of the memory cell section]
, I
In addition, in a system that uses a large number of semiconductor memories, it is necessary to sequentially write and read confirmation data to and from each semiconductor memory and confirm whether the data matches or does not match, which takes a long time to confirm. It has the disadvantage of becoming.

An object of the present invention is to provide a semiconductor memory in which all addresses of a memory cell array can be used for normal data, and the validity of data in the memory cell array can be confirmed in a short time when using a backup power supply. It is about providing.

[Means to solve the problem]

The semiconductor memory of the present invention includes a memory cell array that retains stored data using a backup power source when the main power source is cut off, a decoder that specifies an address of the memory cell array using an address signal, and a memory cell array that is specified by the decoder. a memory section including an input/output circuit that writes and reads normal data to and from addresses in the cell array; a nonvolatile memory section that stores confirmation data; and a main power source provided adjacent to the memory cell array. an extended memory cell section that retains data stored by the backup power supply when the first
The confirmation data stored in the non-volatile memory section is written to the extended memory cell section at the timing of the second
an expansion input/output circuit that reads data stored in the expansion memory cell section at a timing of , and compares data from the expansion input/output circuit with confirmation data stored in the nonvolatile memory section. It has a comparison circuit that outputs a determination signal as to whether or not there is a match, and an extended memory control section that performs writing, reading control, and comparison control of the confirmation data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment includes a memory cell array 1 which retains stored data by a backup power supply when the main power supply is cut off, and a row decoder which specifies the address of the memory cell array 11 using address signals A, DR, and ADc. 12 and a column decoder 14, and a memory cell array 1 specified by the row decoder 12 and column decoder 14.
1. A storage section 10 for normal data DT, which includes an input/output circuit 13 that writes and reads normal data DT to and from addresses of , a nonvolatile memory section 1 that stores confirmation data DTC, and a memory cell array. an extended memory cell section 2 which is provided in close proximity to the main power source 11 and retains stored data using a backup power supply when the main power supply is cut off; Confirmation data DTC stored in
an expansion input/output circuit 3 that writes the data stored in the expansion memory cell section 2 at a second timing, and an expansion input/output circuit 3 that writes the data stored in the expansion memory cell section 2 at a second timing; The structure includes a comparison circuit 4 that compares the data DTC with the data DTC and outputs a judgment signal JE indicating whether or not they match, and an expansion memory control section 5 that performs write/read control and comparison control of the confirmation data DTC. There is.

Next, the operation of this embodiment will be explained.

Memory cell array 11 after switching to backup power supply
When confirming the validity of the data, first, before switching to the backup power supply, the confirmation data DTC stored in the non-volatile memory section is written to the extended memory cell section 2.

Next, after switching to the backup power supply, the data stored in the extended memory cell section 2 is read out, and this data is compared with the confirmation data DTC from the nonvolatile memory section 1. As a result of the comparison, a judgment signal JE is output to determine whether or not they match.

If this judgment signal JE indicates "match", the extended memory cell section 2 is formed in close proximity to the memory cell array 11, and the memory cells forming these have almost the same characteristics. The data stored in cell array 11 is determined to be valid.

In this way, it is not necessary to provide the memory cell section X for confirmation in the memory cell array 11 in the conventional example, and this section can also be used for normal data, so that the addresses of the memory cell array 11 may become discontinuous All addresses can be used for normal data without any usage restrictions. In addition, even in systems that use a large number of semiconductor memories, the validity of data can be checked for each semiconductor memory individually, and these can be done simultaneously, reducing the time required for confirmation. can.

FIG. 2 is a block diagram showing a second embodiment of the invention.

The difference between this embodiment and the first embodiment is that the memory cell array 11 is divided into two memory cell parts 11A and 11B, and the memory cell arrays 11A and 11B are expanded to adjacent outside portions and between the memory cell arrays 11A and 11B. Memory cell sections 2A to 2c are provided to enable more accurate confirmation of the validity of data in memory cell arrays 11A and 11B using a backup power source.

〔Effect of the invention〕

As explained above, the present invention provides an extended memory cell section in proximity to the memory cell array, separate from the memory cell array that stores normal data, and writes and reads confirmation data to and from the extended memory cell section. By implementing a configuration in which the validity of the data held by the backup power supply is confirmed, all addresses in the memory cell array can be used continuously and without restrictions, and systems that use a large number of semiconductor memories can Also, the validity of the data held by the backup power source can be confirmed in each semiconductor memory, and the confirmation time can be reduced.

[Brief explanation of drawings]

↑ and FIG. 2 are block diagrams showing the first and second embodiments of the present invention, respectively, and FIG. 3 is a block diagram showing an example of a conventional semiconductor memory. DESCRIPTION OF SYMBOLS 1... Non-volatile memory, 2, 2A-2c... Expansion memory cell section, 3... Extension input/output circuit, 4... Comparison circuit, 5, 5A... Extension memory control section, 6. ...Extension decoder, 10.1OA...Storage section, 11, 11A. 11B...Memory cell array, 11X...Memory cell section for confirmation, 12...Row decoder, 13...I/O circuit, 14...Column decoder.

Claims (1)

[Claims] A memory cell array that retains stored data by a backup power supply when the main power supply is cut off, a decoder that specifies the address of the memory cell array using an address signal, and a normal a storage section including an input/output circuit for writing and reading data; a nonvolatile memory section for storing confirmation data; and a backup section provided in close proximity to the memory cell array to be used as a backup when the main power supply is cut off. An extended memory cell section that holds data stored in the non-volatile memory section is written to the extended memory cell section at a first timing, and the verification data stored in the non-volatile memory section is written at a second timing. An expansion input/output circuit that reads data stored in the expansion memory cell section compares the data from this expansion input/output circuit with the confirmation data stored in the nonvolatile memory section and determines whether or not they match. 1. A semiconductor memory comprising: a comparison circuit that outputs the determination signal; and an extended memory control section that performs writing, readout, and comparison control of the verification data.