JPH03220653A - Malfunction prevention control system - Google Patents

Abstract

PURPOSE:To prevent malfunction by converting received signals to parallel in all periods at timing allocated by a serial / parallel conversion circuit corresponding to slave units, transferring the signal to a master unit and deciding whether the signals are positive response signals from the accessed slave units or not. CONSTITUTION:At timing allocated to slave units 2-1 - 2-n, a signal transmission circuit 7 sends out the positive response signals from the slave units 2-1 - 2-n to an ACK signal line 4. Therefore, even when there is the slave unit causing the malfunction, the affirmative response signals are serially transmitted to the ACK signal line 4 and even when there are the affirmative response signals from the slave units 2-1 - 2-n, the signals are converted in parallel and transferred to a master unit 1 by a serial / parallel conversion circuit 6. Thus, when the plural affirmative response signals are included, the malfunction can be prevented by executing retry, etc.

Description

[Detailed Description of the Invention] [Summary] Regarding a malfunction prevention control method in a system in which a master unit and a plurality of slave units are connected via a bus, malfunctions are prevented by determining whether or not an acknowledgment signal is correct. A master unit and a plurality of slave units are connected via a bus, and the slave unit accessed by the master unit sends an acknowledgment signal to the master unit via an ACK signal line. In the system, a serial/parallel conversion circuit is provided between the master unit and the bus, and a clock signal from the master unit is supplied between the slave unit and the bus via a clock signal line. a signal sending circuit that sends out the acknowledgment signal from the slave unit to the ACK signal line at a predetermined timing according to the above, and within the entire period of timing assigned to the slave unit by the serial/parallel conversion circuit. The received signal is converted into parallel signals and transferred to the master unit, and the master unit determines whether or not it is an acknowledgment signal from the accessed slave unit.

[Industrial application field]

The present invention relates to a malfunction prevention control method in a system in which a master unit and a plurality of slave units are connected via a bus.

In a system such as a data transmission system in which a master unit each equipped with a processor and a plurality of slave units are connected via a common bus, each slave unit controls, for example, a line, and the master unit manages and controls the entire system. When the master unit accesses the slave unit, the slave unit sends an acknowledgment signal to the master unit through a common ACK signal line.

However, if there is a slave unit that sends an erroneous acknowledgment signal due to erroneous recognition of an access address, the master unit may not recognize the acknowledgment signal from the slave unit that has actually been accessed. It is desired to prevent such malfunctions.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, which includes a master unit 41 each equipped with a processor, and a plurality of slave units, in this case two slave units 42-1.42.
-2 through a bus 43 to configure a data transmission device, exchange device, etc., and each slave unit 42-1.42
-2 each control a line, and a distributed control system is configured in which a master unit 41 manages the entire system. The bus 43 is composed of a data bus, an address bus, a control bus, etc., and 44 is an ACK signal line for transmitting an acknowledgment (ACK) signal.

When a desired slave unit is accessed from the master unit 41 by specifying an address, the specified slave unit sends an acknowledgment signal to the master unit 41 via the ACK signal line 44. The master unit 41 is
By receiving this acknowledgment signal, the slave unit determines that it is operating normally and reads data.

[Problem that the invention seeks to solve]

In the configuration shown in FIG. 4 described above, the master unit 41
For example, an address specifying the slave unit 42-1 and a command signal indicating reading or writing of data are sent from the slave unit 42-1 to Φ) in FIG. 5 as shown in (a) of FIG. The acknowledgment signal shown is A.
When the signal is sent to the CK signal line 44, the master unit 41 assumes that the designated slave unit 42-2 is operating normally and performs operations such as reading or writing data.

However, even though the slave unit 42-1 was designated, the slave unit 42-2 malfunctioned and sent the acknowledgment signal shown in (d) as an ACK signal in response to the command signal shown in (C) in FIG. When sent on line 44, master unit 41 transmits this acknowledgment signal to slave unit 42.
It is determined that this is from -1 and moves on to the next operation. Even if an acknowledgment signal from the regular slave unit 42-1 is sent to the ACK signal line 44 as shown by the dotted line, the master unit 41 ignores it. Alternatively, due to malfunction, acknowledgment signals from multiple slave units may be transmitted overlappingly on the ACK signal line 44.

In order to improve this drawback, it is conceivable to provide ACK signal lines between the master unit 41 and each slave unit 42-1, 42-2, but as the number of slave units increases, the ACK signal The disadvantage is that the number of lines increases, resulting in an uneconomical configuration. Therefore, bus 43
In order not to increase the number of signal lines, the ACK signal line 44 is provided commonly to each slave unit.

The present invention aims to prevent malfunctions by determining whether or not an acknowledgment signal is correct.

[Means to solve the problem]

The malfunction prevention control method of the present invention predetermines the timing at which the acknowledgment signal from each slave unit is sent to the ACK signal line, and determines that the acknowledgment signal is correct when it is a predetermined timing acknowledgment signal. , will be explained with reference to FIG.

Master unit 1 and multiple slave units 21 to 2-
In a system in which slave units 2-1 to 2-n accessed by master unit 1 send an acknowledgment signal to master unit 1 via ACK signal line 4, slave units 2-1 to 2-n are connected to , master unit 1 and bus 3
A serial/parallel conversion circuit 6 is provided between the slave units 2-1 to 2-n and the bus 3, and a predetermined clock signal is provided between the slave units 2-1 to 2-n and the bus 3 according to the clock signal from the master unit 1 supplied via the clock signal line 5. A signal sending circuit 7 is provided to send an acknowledgment signal from the slave unit to the ACK signal line 4 at the specified timing, and the serial/parallel conversion circuit 6
The received signals within the entire timing period assigned to the slave units 21 to 2-n are converted into parallel signals and transferred to the master unit 1, and the master unit 1 receives the acknowledgment signal from the designated slave unit. Determine whether it exists or not.

[Effect]

The signal sending circuit 7 transmits signals to the slave units 2-1 to 2-n at timings assigned to the slave units 2-1 to 2-n.
The acknowledgment signal from 2-n is sent to the ACK signal line 4, and even if there is a malfunctioning slave unit on the ACK signal line 4, the acknowledgment signal will be transmitted in series. Even if there is an acknowledgment signal from each slave unit 2-1 to 2-n, the master unit 1 converts it into parallel and transfers it by the serial/parallel conversion circuit 6, so that multiple acknowledgment signals are not included. If so, it means that a malfunctioning slave unit is included.
Alternatively, if the acknowledgment signal has a timing different from the assigned timing of the designated slave unit, it can be determined that the slave unit is malfunctioning. Therefore, by performing a retry or the like in such a case, malfunctions can be prevented.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a master unit, 12-1 to 12-3 are slave units, 13 is a bus, 14 is an ACK signal line, 15 is a clock signal line, and 16 is a series a parallel conversion circuit; 17 is a signal transmission circuit;
18. 19 is a processor (CPU), 20 is a register,
21 is a comparison circuit.

The slave units 12-1 to 12-3 each include a processor 19 to control data transmission and reception, and the master unit 11 also includes a processor 18 to manage each slave unit 121 to 12-3. The data transmission device and exchange device are at the bottom of the tank, and it is of course possible to provide a larger number of slave units.

Further, the signal sending circuit 17 is connected to the slave units 121 to 12.
-3 is assigned to slave unit 1.
ACK signal line 1 for acknowledgment signals from 2-1 to 12-3.
4 and has a circuit configuration based on timing control, so it can be realized with a relatively simple circuit. For example, the bottom of the tank is set by a counter and a gate circuit, etc.
The clock signal sent from the master unit 11 via the clock signal line 15 is counted by a counter,
ACKs the acknowledgment signal from the slave unit by opening the gate circuit at the assigned timing.
It can also be sent to the signal line 14.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, in which (a) is a clock signal sent to the clock signal line 15, (b) is a command signal, and (C) is a slave unit sent to the ACK signal line 14. 12-1 to 12-3 affirmative 0 indicates the allocation timing of response signals A, B, and C. Therefore,
When a command signal specifying slave unit 12-2 is sent from master unit 11, slave unit l
-12-2 is to add an acknowledgment signal to the signal sending circuit 17, and from the signal sending circuit 17 B in (C) of FIG.
It is sent to the ACK signal line 14 at the timing of .

Other slave units that are not specified, such as 12-
3 has been accessed and an acknowledgment signal C is applied to the signal sending circuit 17, the acknowledgment signal C is sent to the ACK signal line 14 at the timing C in FIG. 3(C). In this case, A
= “0°°, B = “1”, and C = “1”.

The serial/parallel conversion circuit 16 on the master unit 11 side receives the ACK signals transmitted serially via the ACK signal line 14 within the entire tying period T assigned to each slave unit 12-1 to 12-3. The response signals are converted into parallel signals and transferred to the master unit 11. In the master unit 11,
Bit b corresponding to the specified slave unit 12-2 is set in register 1 20, and the comparison circuit 21 compares the contents of the register 20 with the parallel signal (“010”) converted by the serial/parallel conversion circuit 16. do.

In the above case, if only the acknowledgment signal B is "l",
Since it matches the set contents of the register 20 ("010"), it is assumed that the acknowledgment signal is normal and the process moves on to the next step.However, if the acknowledgment signal C is also 1'', an unmatched bit occurs. Therefore, it is determined that a malfunction has occurred in the slave unit, and the slave unit 12-2 is accessed again under the control of the processor 18.

As in the case of normal control, if a normal acknowledgment signal is not obtained after a predetermined number of attempts, a system alarm will be sent.

In the embodiment described above, the register 20 and the comparison circuit 21
Although it is determined whether or not the acknowledgment signal is normal by the hardware of the processor 18, it is also possible to determine by the software of the processor 18. Furthermore, the signal sending circuit 17 can of course be provided in the slave units 12-1 to 12-3, and similarly, the serial-to-parallel conversion circuit 16 can be realized by the conversion function in the master unit 11. It is also possible to do so.

〔Effect of the invention〕

As explained above, the present invention provides the slave unit 2-
The signal sending circuit 7 sends out an acknowledgment signal to the ACK signal line 4 at the timing assigned to each of 1 to 2-n, and the acknowledgment signal is serially transmitted to the ACK signal line 4 by the serial/parallel conversion circuit 6. is converted into a parallel signal and transferred to the master unit 1, and the master unit 1 determines whether or not it is an acknowledgment signal from a specified slave unit. There is an advantage that the acknowledgment signals from the units do not interfere, and therefore false acknowledgment signals from the slave units can be reliably detected and malfunctions can be prevented.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram explaining the operation of the third embodiment of the present invention, and FIG. FIG. 5 is an explanatory diagram of the operation of the conventional example. 1 is a master unit, 2-1 to 2-n are slave units, 3 is a bus, 4 is an ACK signal line, 5 is a clock signal line, 6 is a serial/parallel conversion circuit, and 7 is a signal sending circuit.

Claims (1)

[Claims] A master unit (1) and a plurality of slave units (2-
1 to 2-n) via a bus (3), and the slave units (2-1 to 2-n) accessed by the master unit (1) send an acknowledgment signal to the ACK signal line ( 4), in which a serial-to-parallel conversion circuit (6) is provided between the master unit (1) and the bus (3), and the slave unit ( 2-1 to 2-n) and the bus (3) at a predetermined timing according to a clock signal from the master unit (1) that is supplied via a clock signal line (5). Slave unit (2-1 to 2-n)
a signal sending circuit (7) for sending the acknowledgment signal from the ACK signal line (4) to the ACK signal line (4); The received signals within the entire period of the allocated timing are converted into parallel and sent to the master unit (
1), and the master unit (1) determines whether or not it is an acknowledgment signal from the accessed slave unit.