JPH0322069A - Information processor - Google Patents

Abstract

PURPOSE:To process the same software at a high speed by providing plural memory modules each of which has two ports artificially by combination of a selector and a one-port memory. CONSTITUTION:Once a tristate buffer 31 is accessed from an address bus 37, a circuit 30 keeps this buffer 31 in the driving state till the access from an opposite address bus 40. A tristate buffer 32 is kept in the driving state till the access from the address bus after being accessed from the address bus 40. Thus, only the address input of a memory 3 corresponding to the tristate buffer 31 or 32 is sent at the time of access from the address bus on the same side, and therefore, the access time is not extended.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to the structure of its memory system.

[Conventional technology]

Conventionally, there have been configurations of information processing apparatuses having two memory access buses, a data access bus and an instruction access bus, as shown in FIGS. 4 and 5. In the device shown in FIG. 4, a processor (CPU) 1 having two memory access ports is connected to a data access bus 6 and an instruction read bus 7, and a cache memory 8 is connected to each of the data access bus 6 and the instruction read bus 7. .9 is connected, and only when there is no hit in these cache memories 8.9, the selector 15 is switched and the memories 3' and 4' are accessed via the memory bus 16.

In the device shown in FIG. 5, dedicated memories 20 to 25 are connected to a data access bus 17 and an instruction read bus 18, respectively.

[Problem to be solved by the invention]

In FIG. 4 described above, if the cache memories 8 and 9 are not hit, access to either bus must go through the memory bus 16, which has the disadvantage that the processing speed decreases. Furthermore, in FIG. 5, the memories 20 to 22 connected to the data access bus 6 and the memories 23 to 25 connected to the instruction reading bus 7 are separated, so the same memory is used for data and instructions. The disadvantage is that it cannot run the same programs as conventional computers using .

An object of the present invention is to eliminate such drawbacks and to provide a selector and a single
An object of the present invention is to provide an information processing device that can process the same software at high speed by having a plurality of memory modules using pseudo two-port memories using RAM of a boat.

[Means to solve the problem]

The structure of the present invention includes a plurality of memory modules, two buses connected to and accessed by these memory modules for data access and instruction reading, and a first bus connected to these two buses. In an information processing device that has a cache memory and a processor connected to these buses, or a processor that connects these two buses to one bus via a second cache memory, the accessed bus is Each memory module has a control circuit that outputs a selection signal to select, and outputs a selection signal that selects one bus and allows access to the other bus when accessed from both buses at the same time. , a memory, and a selector that connects one of the buses and the memory according to the selection signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention. In this embodiment, the CPUI has two memory access ports, one for data and one for reading instructions, and these are connected to a data access bus 6 and an instruction reading bus 7, respectively. A memory module 10.11 connected to these buses 6.7 is composed of a selector 2.4 and a memory 3.5. Selectors 2 and 4 connect either the data access bus 6 or the instruction read bus 7 to the memory 3.5. Cache memories 8.9 are connected to data access bus 6 and instruction read bus 7, respectively.

FIG. 2 is a block diagram showing the memory module of FIG. 1 in more detail. address bus 37 and data bus 38
corresponds to the data access bus 6 in FIG. 1, and the address bus 40 and data bus 41 correspond to the instruction read bus 7. Data path 38 is tri-state buffer 33
．． 34, the data bus 37 is connected to the memory 3 through tri-state buffers 35 and 36, the address bus 37 is connected to the tri-state buffer 31, and the address bus 40 is connected to the tri-state buffer 32.
Connected to memory 3.

A control circuit 30 outputs control signals for these tristate buffers 31 to 36. This control circuit 30 receives an address bus 37 and an address bus 40 as inputs, and outputs a ready signal 39 and a ready signal 42. ready signal 37
is input to the CPUI via the data access bus 6, and the ready signal 42 is similarly input to the instruction read bus 7.
is input to the CPUI via.

In this embodiment, the memory module 10.11 is a large address unit. For example, each megabyte is allocated.

Next, the operation when the CPU 1 accesses the memory module 10 via the data access bus 6 will be described.

When the CPUI attempts to access the memory module 10 via the data access bus 6, the control circuit 30
This information is learned from the address bus 37, and the tri-state buffer 31 is driven. Also, when accessing to read from memory, the tri-state buffer 3
4, the tri-state buffers 33 are respectively driven in the write access.

Once accessed from the address bus 37, the control circuit 30 keeps the tri-state buffer 31 in a driven state until it is accessed from the address bus 40 on the opposite side.

Further, the tri-state buffer 32 is also connected to the address bus 4.
It is in the driving state after being accessed from 0 until being accessed by the address bus 37. This allows memory 3 to be accessed from the address bus on the same side.
Since the address input is delayed only by the amount of the tristate buffer 31 or tristate 32, the access time does not become long.

FIG. 3 is a block diagram showing the system configuration of a second embodiment of the present invention. C P TJ 1 ' has only one port for accessing memory, and it is
4 to an instruction cache memory 12 and a data cache memory 13. The instruction cache 12 is connected to the data access bus 6, and the data cache memory 13 is connected to the instruction read bus 7.

In this embodiment, the CPUI' has one port, but the cache memory 12.13 is divided into instructions and data.
Each has an instruction read bus 7 and a data access bus 6.
connected to. Cache memory 12.13 is CPU
Even when the memory is not accessed from 1', the memory is accessed by operations such as read ahead and write back, so the data access bus 6 and the instruction read bus 7 are used at the same time, which has the advantage of improving computer performance.

〔Effect of the invention〕

As explained above, the present invention provides an information processing device that can execute the same software at high speed as before by having a plurality of memory modules having two pseudo ports by combining a selector and one board of memory. This has the advantage that it can be configured as follows.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of the memory module of FIG. 1, FIG. 3 is a block diagram of a second embodiment of the present invention, FIG. FIG. 5 is a block diagram showing the structure of a conventional information processing apparatus having two buses. 1.1'...CPU, 2,4.15...Selector,
3.3', 5.5', 20-25...memory, 6
...Data access bus, 7...Instruction read bus,
8, 9...Cache memory, 10.11...Memory module, 12.13...Cache memory for instructions, 14,43.44...Wiring, 16...Memory bus, 30... Control circuit, 31-36... Tri-state buffer, 37.40... Address bus, 38.
41...Data path, 39.42...Ready signal line.

Claims (1)

[Claims] A plurality of memory modules, two buses for data access and instruction reading that are connected to and accessed by these memory modules, and a first cache memory connected to these two buses, and these buses. In an information processing device having connected processors or a processor connected to these two bus systems and one bus system via a second cache memory, outputting a selection signal for selecting the accessed bus. , a control circuit that outputs a selection signal that selects one bus and allows access to the other bus when accessed from both buses simultaneously, and each memory module has a memory and a control circuit that outputs a selection signal that allows access to the other bus. An information processing device comprising: a selector that connects one of the buses and the memory.