JPH03220731A - Gaas fet - Google Patents
Gaas fetInfo
- Publication number
- JPH03220731A JPH03220731A JP1555790A JP1555790A JPH03220731A JP H03220731 A JPH03220731 A JP H03220731A JP 1555790 A JP1555790 A JP 1555790A JP 1555790 A JP1555790 A JP 1555790A JP H03220731 A JPH03220731 A JP H03220731A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- undoped
- algaas
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 54
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 16
- 230000007547 defect Effects 0.000 abstract description 9
- 239000013078 crystal Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract 1
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010581 sealed tube method Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明はＧａＡｓＦＥＴに係り、特にドレイン電流の
漏れが少なく、高ゲインで低雑音特性を得ることのでき
るＧａＡｓＦＥＴに関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a GaAsFET, and particularly to a GaAsFET that has little drain current leakage, high gain, and low noise characteristics.
（従来の技術）
第７図の素子断面模式図に示すようにｎ型ＧａＡｓ能動
層１０１とＧａＡｓバッファ層１０２との間に、ＧａＡ
ｓよりバンドギャップエネルギの大きいＡｊ！ＧａＡｓ
をバッファ層１０３として形成して、ＧａＡｓとＡＩＬ
ＧａＡｓ間のへテロ接合のエネルギ障壁によってドレイ
ン電流の漏れを少なくする技術は知られている。ＡＪ２
ＧａＡｓバッファ層１０３としてはアンドープまたはＰ
型が用いられており、Ｐ型ＡｌＧａＡｓの方がドレイン
電流漏れに対する障壁効果は大きい。(Prior Art) As shown in the schematic cross-sectional view of the device in FIG.
Aj with larger bandgap energy than s! GaAs
is formed as a buffer layer 103, and GaAs and AIL are formed as a buffer layer 103.
Techniques for reducing drain current leakage by creating an energy barrier in a heterojunction between GaAs are known. AJ2
The GaAs buffer layer 103 is undoped or P.
P-type AlGaAs has a greater barrier effect against drain current leakage.
（発明が解決しようとする課題）
しかし、ＧａＡｓ能動層１０１とＡｌＧａＡｓバッファ
層１０３とは異種（ヘテロ〉接合となるため、接合界面
に結晶欠陥が発生する。まｋ、このような接合構造は一
般にＭＯＣＶＤ法（有機金属気相エピタキシャル成長性
）やＭＢＥ法（分子線エピタキー）で形成されるが、Ｐ
型ＡｌＧａＡｓをバッファ層として用いる場合、Ｐ型不
純物が充分に活性化されずに格子間に位置し深い準位を
作このようにヘテロ接合界面およびＡｕＧａＡｓ層に欠
陥が存在すると、この欠陥を介してキャリアの発生・再
結合がおこり、ＦＥＴとしてはノイズ（特に低周波域で
の４／ｆノイズ）の増加につながるという問題がある。(Problem to be Solved by the Invention) However, since the GaAs active layer 101 and the AlGaAs buffer layer 103 form a heterojunction, crystal defects occur at the junction interface. It is formed by MOCVD (metal organic vapor phase epitaxy) or MBE (molecular beam epitaxy), but P
When AlGaAs type AlGaAs is used as a buffer layer, if there are defects at the heterojunction interface and the AuGaAs layer, the P-type impurity is not activated sufficiently and is located in the interstitial space, creating a deep level. There is a problem in that carriers are generated and recombined, leading to an increase in noise (particularly 4/f noise in the low frequency range) in the FET.
この発明はこのような課題を解決するためなされたもの
て、その目的はトレイン電流の漏れが少なく、かつ、ヘ
テロ接合界面やＡｆｌＧａＡｓ中の結晶欠陥の影響を低
減したＧａＡｓＦＥＴを提供することにある。The present invention has been made to solve these problems, and its purpose is to provide a GaAsFET with less leakage of train current and with reduced effects of crystal defects at the heterojunction interface and in AflGaAs.
（課題を解決するための手段）
前記課題を解決するためこの発明に係るＧａＡｓＦＥＴ
は、ＧａＡｓ能動層とＡｕＧａＡｓバッファ層との間に
、アンドープＧａＡｓ層、もしくは、アンドープＧａＡ
ｓ層とアンドープＡｌＧａＡｓ層を設けたことを特徴と
する。(Means for Solving the Problems) In order to solve the above problems, a GaAsFET according to the present invention is provided.
is an undoped GaAs layer or an undoped GaAs layer between the GaAs active layer and the AuGaAs buffer layer.
It is characterized by providing an s layer and an undoped AlGaAs layer.
（作用）
前記構造ではＧａＡｓ能動層とアンドープＧａＡｓ層は
同種（ホモ）接合となり、従来構造て問題であった異種
（ヘテロ）接合界面の結晶欠陥を低減てきる。さらに、
ＧａＡｓ能動層とアン）・−プＧａＡｓ間のエネルギ障
壁によりＡｕＧａＡｓ層へのトレイン電流の漏れが低減
され、／ｍＱＧａＡｓ内の結晶欠陥の影響もＧａＡ ｓ
層により低減できる。(Function) In the above structure, the GaAs active layer and the undoped GaAs layer form a homojunction, which reduces crystal defects at the heterojunction interface, which has been a problem in conventional structures. moreover,
The energy barrier between the GaAs active layer and the amplified GaAs reduces the leakage of train current into the AuGaAs layer, and the effect of crystal defects in the GaAs is also reduced.
It can be reduced by layering.
なお、不純物欠陥の多いＰ型ＡＪ２ＧａＡｓをバッファ
層として用いる場合には、Ｎ型ＧａＡｓ能動層の下に絶
縁性ＧａＡｓ層、絶縁性ＡｌｌＧａＡｓ層、Ｐ型Ａｆｌ
ＧａＡｓバッファ層を設りる構造とすることにより、Ｐ
型ＡｕＧａＡｓ層の結晶欠陥による影響をさらに低減す
ることかできる。Note that when P-type AJ2GaAs with many impurity defects is used as a buffer layer, an insulating GaAs layer, an insulating AllGaAs layer, a P-type Afl
By providing a structure with a GaAs buffer layer, P
The influence of crystal defects in the AuGaAs layer can be further reduced.
（実施例）
以下、この発明の実施例を添付図面に基づいて説明する
。(Example) Hereinafter, an example of the present invention will be described based on the accompanying drawings.
第１図は請求項１に係るＧａＡｓＦＥＴの構造を示す断
面模式図である。FIG. 1 is a schematic cross-sectional view showing the structure of a GaAsFET according to a first aspect.
ＧａＡｓＦＥＴ１は、半絶縁性（１０７Ω’ｃｍ以上）
のＧａＡｓ基板１１の上にアンドープＧａＡｓバッファ
層１２を厚さ約０．５μｍ、アンドープＡＪＩＬＧａＡ
ｓ （Ａｆｌ比０．２）バッファ層１３を厚さ約１．５
μｍ、アンドープＧａＡｓ層１４を厚さ約０．３ μｍ
、 Ｎ型ＧａＡｓ （Ｎｄ＝１．５ ｘｌ ０ ”７ｃ
ｍ３）能動層１５を約０．３ μｍ、 Ｎ生型ＧａＡｓ
（Ｎｄ＝１ｘｌ ０１１ｔ／Ｃｍ３ ）コンタク）・
層１６を厚さ約０．２ μｍ、ＭＯＣＶＤ法で成長させ
た後に、ゲート電極１７のコンタクト部のＮ＋型ＧａＡ
ｓコンタクト層１６をりん酸系（リン酸３・過水１・水
５０）またはクエン酸系（クエン酸１００：過水８・水
１０）のエツチング液で除去し、次に、ソース電極１８
およびドレイン電極１９のオーくツク電、１ｉ（ＡｕＧ
ｅＮｉ）、ならびにショットキ型のゲート電極１７を形
成して、ＭＥＳ型のＦＥＴを構成する。GaAsFET1 is semi-insulating (107Ω'cm or more)
An undoped GaAs buffer layer 12 with a thickness of about 0.5 μm is formed on a GaAs substrate 11 of undoped AJILGaA.
s (Afl ratio 0.2) The buffer layer 13 has a thickness of about 1.5
μm, and the thickness of the undoped GaAs layer 14 is approximately 0.3 μm.
, N-type GaAs (Nd=1.5 xl 0 ”7c
m3) The active layer 15 is approximately 0.3 μm thick and made of N-type GaAs.
(Nd=1xl 011t/Cm3) contact)・
After growing the layer 16 to a thickness of approximately 0.2 μm using the MOCVD method, an N+ type GaA layer at the contact portion of the gate electrode 17 is
The s-contact layer 16 is removed with a phosphoric acid-based (3 phosphoric acid, 1 part hydrogen peroxide, 50 parts water) or citric acid-based (100 citric acid: 8 parts hydrogen peroxide, 10 parts water) etching solution, and then the source electrode 18 is removed.
and the conductor of the drain electrode 19, 1i (AuG
eNi) and a Schottky-type gate electrode 17 to configure an MES-type FET.
第２図は請求項１に係るＧａＡｓＦＥＴのエネルギ構造
図である。FIG. 2 is an energy structure diagram of the GaAsFET according to the first aspect.
第１図に示した構造のＧａＡｓＦＥＴ１ては、ドレイン
電流の半絶縁性ＧａＡｓ基板１１側への漏れは、アンド
ープＧａＡｓ層１４およびアンドープＡｌＧａＡｓバッ
ファ層１３で阻止される。In the GaAsFET 1 having the structure shown in FIG. 1, leakage of drain current toward the semi-insulating GaAs substrate 11 is prevented by the undoped GaAs layer 14 and the undoped AlGaAs buffer layer 13.
第３図はＦＥＴの電圧−電流特性を示すグラフである。FIG. 3 is a graph showing the voltage-current characteristics of the FET.
同図（ａ）は、第１図に示したＧａＡｓＦＥＴＩのドレ
イン−ソース間電圧（ＶＤＳ）に対するドレイン電流（
ＩＤＳ）特性をゲート電圧（ＶＧＳ）をパラメータにし
て示したものであり、同図（ｂ）は第７図に示す従来構
造のＦＥＴの同様な特性である。第３図の電圧−電流特
性に示されるように、請求項１に係るＧａＡｓＦＥＴ１
はトレイン電流（ＩＤＳ）のリークが少ない。Figure (a) shows the drain current (
(IDS) characteristics are shown using the gate voltage (VGS) as a parameter, and FIG. 7(b) shows similar characteristics of the FET of the conventional structure shown in FIG. As shown in the voltage-current characteristics of FIG. 3, the GaAsFET 1 according to claim 1
has less leakage of train current (IDS).
第４図はＦＥＴの雑音特性を示すグラフである。第４図
において、縦軸は入力等価電圧を、横軸は周波数を表わ
している。同図中の実線は請求項１に係るＧａＡｓＦＥ
Ｔ１の雑音特性を、点線は第７図に示す従来構造のＦＥ
Ｔの雑音特性を示す。ＧａＡｓＦＥＴ１は入力等価雑音
電圧が低減している。FIG. 4 is a graph showing the noise characteristics of the FET. In FIG. 4, the vertical axis represents the input equivalent voltage, and the horizontal axis represents the frequency. The solid line in the figure represents the GaAsFE according to claim 1.
The dotted line indicates the noise characteristics of T1, and the dotted line indicates that of the conventional structure of FE shown in Fig. 7.
The noise characteristics of T are shown. GaAsFET1 has a reduced input equivalent noise voltage.
第５図は請求項２に係るＧａＡｓＦＥＴの構造を示す断
面模式図である。FIG. 5 is a schematic cross-sectional view showing the structure of a GaAsFET according to the second aspect.
請求項２に係るＧａＡｓＦＥＴ２は、半絶縁性（１０７
Ω・ｃｍ以上）のＧａＡｓ基板２１の上に、Ｐ型ＧａＡ
ｓ （Ｎａ＝２ｘ １０１７／ｃｍ３）バッファ層２２
を厚さ約０．５ μｍ、Ｐ型ＡｌＧａＡｓ （Ａｎ比０
．２．Ｎ ａ ＝ ２ ｘ １０１７／ｃｍ３）バッフ
ァ層２３を厚さ約１．５μｍ、アンドープＡｌＧａＡｓ
（ＡＪ２比０．２）層２４を厚さ約１．０μｍ、アン
ドープＧａＡｓ層２５を厚さ約０．３ μｍ、 Ｎ型Ｇ
ａＡｓ （Ｎｄ＝１．５ ｘ １０１７／ｃｍ３）能動
層２６を厚さ約０．３ μｍ、 Ｎ生型ＧａＡｓ （Ｎ
ｄ＝１ ｘ １０１８／ｃｍ３）コンタクト層２７を厚
さ約０．２μｍ、ＭＯＣＶＤ法で成長させた後に、ゲー
ト電極２８のコンタクト部のＮ生型ＧａＡｓコンタクト
層２７をリン酸系またはクエン酸系のエツチング液で除
去し、次に、ソース電極２９およびドレイン電極３０の
オーミック電極（ＡｕＧｅＮｉ）ならびに、ショットキ
型のゲート電極２８を形成して、ＭＥＳ型のＦＥＴを構
成する。The GaAsFET 2 according to claim 2 is semi-insulating (107
P-type GaA
s (Na=2x 1017/cm3) buffer layer 22
about 0.5 μm thick, P-type AlGaAs (An ratio 0
．． 2. Na = 2 x 1017/cm3) The buffer layer 23 is made of undoped AlGaAs with a thickness of about 1.5 μm.
(AJ2 ratio 0.2) Layer 24 is approximately 1.0 μm thick, undoped GaAs layer 25 is approximately 0.3 μm thick, N-type G
The aAs (Nd=1.5 x 1017/cm3) active layer 26 has a thickness of approximately 0.3 μm, and is made of N-baked GaAs (N
d=1 x 1018/cm3) After growing the contact layer 27 to a thickness of approximately 0.2 μm using the MOCVD method, the N-type GaAs contact layer 27 in the contact portion of the gate electrode 28 is grown using a phosphoric acid-based or citric acid-based After removal with an etching solution, ohmic electrodes (AuGeNi) for the source electrode 29 and drain electrode 30 and a Schottky gate electrode 28 are formed to form an MES type FET.
第６図は請求項２に係るＧａＡｓＦＥＴのエネルギ構造
図である。FIG. 6 is an energy structure diagram of the GaAsFET according to the second aspect.
第５図に示した構造のＧａＡｓＦＥＴ２では、ドレイン
電流の半絶縁性ＧａＡｓ基板２１側への漏れは、アンド
ープＧａＡｓ層２５、アンドープＡｆ！、ＧａＡｓバッ
ファ層２４、および、Ｐ型ＡＪ２ＧａＡｓバッファ層２
３で阻止される。In the GaAsFET 2 having the structure shown in FIG. 5, leakage of drain current to the semi-insulating GaAs substrate 21 occurs through the undoped GaAs layer 25 and the undoped Af! , GaAs buffer layer 24, and P-type AJ2GaAs buffer layer 2
Blocked by 3.
なお、各実施例ともショットキゲートを形成したＭＥＳ
ＦＥＴについて説明したが、接合形ＦＥＴ （Ｊ−ＦＥ
Ｔ）についても同様の構造で同じ効果が得られる。In addition, in each example, an MES with a Schottky gate formed was used.
Although we have explained about FET, junction type FET (J-FE
The same effect can be obtained for T) with a similar structure.
接合形ＦＥＴの製作工程の１例を以下に説明する。An example of the manufacturing process of a junction type FET will be described below.
ＭＯＣＶＤ法による結晶成長後に、５ｉ３Ｎ４Ｈ＠を厚
さ１５００オングストローム形成し、ゲート部にドライ
エツチングで窓あけを行なう。次にＺｎＡｓを拡散源と
して封管法でＺｎ拡散（５５０ｔ Ｘ １００分）を行
ないＰ形ＧａＡｓゲートを形成し、ゲート金属（ＡｕＢ
ｅ）を形成する。次に、ソースおよびドレイン部にＳｉ
３Ｎ４膜の窓あけを行なった後にオーよツク電極（Ａｕ
ＧｅＮｉ）を形成して接合形ＦＥＴを構成する。After crystal growth by MOCVD, 5i3N4H@ is formed to a thickness of 1500 angstroms, and a window is formed in the gate portion by dry etching. Next, Zn was diffused (550t x 100 minutes) using ZnAs as a diffusion source using a sealed tube method to form a P-type GaAs gate, and the gate metal (AuB
form e). Next, Si is placed in the source and drain parts.
After opening the 3N4 film, an open electrode (Au
GeNi) to form a junction FET.
（発明の効果）
以上説明したように本発明に係るＧａＡｓＦＥＴは、Ｇ
ａＡｓ能動層とＡｌ１ＧａＡｓバッファ層との間にアン
ドープＧａＡｓ層、もしくは、アンドープＧａＡｓ層と
アンドープＡ立ＧａＡｓ層を設けたので、ドレイン電流
のＧａＡｓ基板へのリークが低減できる。また、ＧａＡ
ｓ能動層とアンドープＧａＡｓ層とは同種（ホモ）接合
となり、この接合界面での結晶欠陥を低減できるので、
ＦＥＴ内部で発生するノイズ（特に低周波域での１７ｆ
ノイズ）を小さくすることができる。(Effect of the invention) As explained above, the GaAsFET according to the present invention has a G
Since an undoped GaAs layer or an undoped GaAs layer and an undoped A-vertical GaAs layer are provided between the aAs active layer and the Al1GaAs buffer layer, leakage of drain current to the GaAs substrate can be reduced. Also, GaA
The s-active layer and the undoped GaAs layer form a homojunction, and crystal defects at this junction interface can be reduced.
Noise generated inside the FET (especially 17f in the low frequency range)
noise) can be reduced.
第１図は請求項１に係るＧａＡｓＦＥＴの構造を示す断
面模式図、第２図は同ＧａＡｓＦＥＴのエネルギ構造図
、第３図はＦＥＴの電圧−電流特性を示すグラフで同図
（ａ）は請求項１に係るＧａＡｓＦＥＴ、同図（ｂ）は
ＧａＡｓＦＥＴのＶＤＳ−ＩＤＳ特性を示すグラフ、第
４図はＦＥＴの雑音特性を示すグラフ、第５図は請求項
２に係るＧａＡｓＦＥＴの構造を示す断面模式図、第６
図は同ＧａＡｓＦＥＴのエネルギ構造図、第７図は従来
のＧａＡｓＦＥＴの構造を示す断面模式図である。
１．２−ＧａＡｓＦＥＴ、１１．２１・・・半絶縁性Ｇ
ａＡｓ基板、１３．２３−ＡＩｔＧａＡｓバッファ層、
１４．２５・・・アンドープＧａＡｓ層、２４・・・ア
ンドープＡｊ！ＧａＡｓ層。
特 許 出 願 人 日本ビクター株式会社ＶＧＳ
： ０．５Ｖステツプ
ドレイン−ソース間電圧
■ＤＳ（■）
（ａ）第１図のＦＥＴ
電圧−
夕６
ＶＧＳ ： ０．５Ｖステツプ
ドレイジーソース間電圧
ｖｏｓ （ｖ）
（ｂ）従来のＦＥＴ
・電流特性
図FIG. 1 is a cross-sectional schematic diagram showing the structure of the GaAsFET according to claim 1, FIG. 2 is an energy structure diagram of the GaAsFET, and FIG. 3 is a graph showing the voltage-current characteristics of the FET. GaAsFET according to claim 1, FIG. 4 is a graph showing the VDS-IDS characteristics of the GaAsFET, FIG. 4 is a graph showing the noise characteristics of the FET, and FIG. 5 is a cross-sectional schematic diagram showing the structure of the GaAsFET according to claim 2. Figure, 6th
The figure is an energy structure diagram of the same GaAsFET, and FIG. 7 is a schematic cross-sectional diagram showing the structure of a conventional GaAsFET. 1.2-GaAsFET, 11.21...Semi-insulating G
aAs substrate, 13.23-AItGaAs buffer layer,
14.25...Undoped GaAs layer, 24...Undoped Aj! GaAs layer. Patent applicant: Victor Japan Co., Ltd. VGS
: 0.5V step drain-source voltage ■DS(■) (a) FET voltage in Figure 1 VGS: 0.5V step drain-source voltage vos (v) (b) Conventional FET current Characteristic diagram
Claims (2)
ｌＧａＡｓバッファ層を有するＧａＡｓＦＥＴにおいて
、前記ＧａＡｓ能動層と前記ＡｌＧａＡｓバッファ層と
の間にアンドープＧａＡｓ層を設けたことを特徴とする
ＧａＡｓＦＥＴ。(1) A between the GaAs active layer and the GaAs buffer layer
A GaAsFET having an IGaAs buffer layer, characterized in that an undoped GaAs layer is provided between the GaAs active layer and the AlGaAs buffer layer.
ｌＧａＡｓバッファ層を有するＧａＡｓＦＥＴにおいて
、前記ＧａＡｓ能動層と前記ＡｌＧａＡｓバッファ層と
の間にアンドープＧａＡｓ層およびアンドープＡｌＧａ
Ａｓ層を設けたことを特徴とするＧａＡｓＦＥＴ。(2) A between the GaAs active layer and the GaAs buffer layer
In a GaAsFET having an IGaAs buffer layer, an undoped GaAs layer and an undoped AlGaAs layer are provided between the GaAs active layer and the AlGaAs buffer layer.
A GaAsFET characterized by being provided with an As layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1555790A JPH03220731A (en) | 1990-01-25 | 1990-01-25 | Gaas fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1555790A JPH03220731A (en) | 1990-01-25 | 1990-01-25 | Gaas fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03220731A true JPH03220731A (en) | 1991-09-27 |
Family
ID=11892072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1555790A Pending JPH03220731A (en) | 1990-01-25 | 1990-01-25 | Gaas fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03220731A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594262A (en) * | 1994-06-06 | 1997-01-14 | The United States Of America As Represented By The Secretary Of The Air Force | Elevated temperature gallium arsenide field effect transistor with aluminum arsenide to aluminum gallium arsenide mole fractioned buffer layer |
-
1990
- 1990-01-25 JP JP1555790A patent/JPH03220731A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594262A (en) * | 1994-06-06 | 1997-01-14 | The United States Of America As Represented By The Secretary Of The Air Force | Elevated temperature gallium arsenide field effect transistor with aluminum arsenide to aluminum gallium arsenide mole fractioned buffer layer |
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