JPH03220750A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the time for redesigning a chip and the manufacturing costs of diffusion masks by providing unused matrix arrays of transistors in a portion of outer regions of the chip where input/output buffer circuits are arranged. CONSTITUTION:A semiconductor chip 7 includes inner cell array 4 in its inner region. Input/output buffer circuits 5 are arranged in outer regions in the periphery of the inner region. Cell arrays 1-3 for use of redesigning are formed between the input/output buffer circuits, to which pad electrodes are connected for external connection. When the chip is redesigned to change or add logic functions, it is modified without a change of transistor processes by using the cell arrays 1-3 and additional wiring. Therefore, it is possible to reduce the time for redesigning and the manufacturing costs of diffusion masks.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having functional blocks arranged in a standard cell layout.

[Conventional technology]

Conventional semiconductor integrated circuits have an internal area on a semiconductor chip where internal logic blocks are placed, and an external area where an input/output buffer circuit is placed that converts high-y energy signals from external circuits and low-energy signals from the internal area. It is sectioned.

FIG. 3 is a layout diagram showing an example of a conventional semiconductor integrated circuit.

As shown in FIG. 3, the external area provided at the periphery of the semiconductor chip is formed surrounding the internal area, and the input/output buffer circuits 15 provided in the external area have the same shape to facilitate automatic placement and wiring. The pad electrode 16 is connected to a pad electrode 16 for external circuit connection. A semiconductor integrated circuit having a desired logic function is constructed by arranging logic blocks in a polycell-shaped cell array 14 provided in an internal region and performing automatic wiring together with special function blocks 12.

Here, each of the logic function block and special function block is designed in advance to be optimal in terms of transistor size and arrangement within the block.

By automatically arranging the blocks on a chip and automatically wiring the terminals of the blocks, it is possible to design a semiconductor integrated circuit having a desired logical function in a short period of time.

At this time, in order to reduce the chip unit cost, automatic placement and wiring is performed on the condition that the chip size is minimized.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit described above is tested to see if a desired logic function can be obtained from a circuit mounted on a semiconductor substrate.

At this time, if the desired logic function cannot be obtained, or if it becomes necessary to change or add a logic function, automatic placement and wiring must be performed again. This will lengthen the design period and increase development costs due to re-creation of the diffusion mask.
Furthermore, there was a drawback that the chip size increased.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has a cell array having transistors of the same size provided in a part of the external area where the input/output buffer is located, and when chip redesign is required, the cell array can be used to change only the wiring process. Change or add desired logical functions using

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram showing a first embodiment of the present invention.

As shown in FIG. 1, an internal cell array 4 is provided in the internal region of the semiconductor chip 7, and input/output buffer circuits 5 are arranged and provided in the external region of the semiconductor chip 7 on the outer periphery of the internal region, and each input/output buffer Cell arrays 1 to 3 for redesign are arranged between circuits 5, and input/output buffer circuits 5 are connected to pad electrodes for external circuit connection.

FIG. 2 is a layout diagram showing a second embodiment of the present invention.

As shown in FIG. 2, the area of the cell array 1 is the same as that of two human output buffer circuits 5, and the cell array 2 is arranged using a part of the butt electrode forming area. It has the same configuration as the embodiment.

〔Effect of the invention〕

As explained above, the present invention allows changing the desired logic function by pre-arranging transistors arranged in rows and columns as an unused cell array in a part of the external area where the input/output buffer circuit is provided. If it becomes necessary to redesign the chip for additions or the like, the cell array can be used to change or add desired logic functions by changing only the wiring process, without changing the design of the transistor formation process. Therefore, chip redesign is shortened.

This has the effect of reducing the manufacturing cost of the diffusion mask.

[Brief explanation of drawings]

1 and 2 are layout diagrams showing first and second embodiments of the present invention, and FIG. 3 is a layout diagram showing a conventional semiconductor integrated circuit. 1.2.3... Cell array, 4, 14... Internal cell array, 5.15... Input/output buffer circuit, 6°6.
...Pad electrode, 7゜7...Semiconductor chip, 12...Special function block.

Claims (1)

[Claims] In a semiconductor integrated circuit in which a desired logic circuit is obtained by arranging a plurality of circuit blocks on a semiconductor chip and interconnecting these circuit blocks, an input/output buffer circuit provided at the periphery of the semiconductor chip is arranged. A semiconductor integrated circuit comprising cells equivalent to cells of an internal logic cell array provided in a part of an external region.