JPH03220764A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable reduction of chip size by using polycrystalline silicon film for the lower electrode of a capacitor and by forming bonding pads via an insulating film over a capacitor spread with a polycrystalline silicon film of the lower electrode and with a dielectric film. CONSTITUTION:An oxide film 5 on a polycrystalline silicon film 4 is etched except a part 6 to serve as the dielectric film of a capacitor to form the lower electrode of a capacitor. The next stop is to spread the whole surface with the first metal film, which is etched to form the first metallized layer and a metal electrode 8a as the upper electrode on the dielectric film used for a capacitor and to form a metal (Al) electrode 8 as the lower electrode at the extraction part of a polycrystalline silicon film under the dielectric file used as a capacitor. The other step is to spread the whole surface with the second metal film, which is etched to form the second metallized layer and bonding pads 11 via an interlayer insulating file 10 over a dielectric film not used for a capacitor. This process can reduce the chip size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a capacitor.

[Conventional technology]

As shown in the cross-sectional view shown in FIG. 3, this type of conventional technology involves forming an N-type diffusion layer 13 on an N-type epitaxial layer 1, and then depositing a layer with a thickness of 300 mm on the N-type diffusion layer 13. An oxide film 14 is formed, and a silicon nitride film 3 with a thickness of 1000 nm is formed on this oxide film 14, and this oxide film 14 and silicon nitride Il! 3 is a dielectric film, and an N-type diffusion layer 13. N+ type scattering layer 1 for contact formed in N type diffusion layer 13
4. Polycrystalline silicon film on top of 5N+ type diffusion layer 15. and the aluminum electrode 8 connected via the polycrystalline silicon film 4 to the N+ type scattering layer 15 as the lower electrode, and the polycrystalline silicon film 4 formed on the dielectric film and the polycrystalline silicon on the dielectric film. Aluminum electrode 8a formed on film 4
and was used as the upper electrode to form a capacitor.

On the other hand, the aluminum film of the bonding pad 11 for assembly was formed on the silicon nitride film 9, which is an insulating film between the eyebrows. In addition, the bonding pad 11 is designed so that the semiconductor characteristics will not be affected even if the lower part is strained during bonding.
No device was formed directly beneath it, but it was formed on an element isolation region consisting of a P-type diffusion layer 12 provided in an N-type epitaxial layer 1, a field oxide film 2 provided thereon, and the like.

[Problem to be solved by the invention]

The semiconductor device equipped with the conventional capacitor described above uses a thin oxide film and a silicon nitride film as the dielectric film, and even if the aluminum film of the electrode is removed, there is still a polycrystalline silicon film, so a bonding pad is placed on top of the polycrystalline silicon film. If cracks occur in the dielectric film due to strain caused in the bonding process or the like, the polycrystalline silicon film and the N-type diffusion layer, which is the other electrode, are likely to be short-circuited.

In particular, even when changing the number and position of bonding pads during the wiring process, such as with master slice products, bonding pads cannot be formed on top of unnecessary capacitors, so bonding pads must be formed on the outer periphery of the semiconductor chip. However, the disadvantage is that the chip size increases accordingly.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of depositing a polycrystalline silicon film on an insulating film, a step of forming an insulating film on the polycrystalline silicon film, and annealing after introducing impurities into the polycrystalline silicon film by ion implantation. Step: Etching the insulating film on the polycrystalline silicon film leaving the part that will become the dielectric film of the capacitor; Etching the polycrystalline silicon film and leaving the polycrystalline silicon film under the dielectric film and on the lead-out part. Step of forming the lower electrode of the capacitor, step of forming the first metal film on the entire surface, and etching of the first metal film to form the upper electrode on the first layer of metal wiring and the dielectric film used as the capacitor. A step of forming a metal electrode as a lower electrode on the extended portion of the polycrystalline silicon film under the dielectric film used as a capacitor, and a step of forming an interlayer insulating film on the entire surface and forming a through hole. , a step of forming a second metal film on the entire surface, and etching the second metal film to form a bonding pad on the second layer metal wiring and at least one dielectric film not used as a capacitor through an insulating film between the eyebrows. and a step of forming.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are process-order sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

First, as shown in FIG. 1 (a), a field oxide film 2 is formed on an N-type epitaxial layer l, and after growing, for example, 1000 silicon nitride films 3 on the field oxide film 2, a polycrystalline film 3 is grown on the entire surface. For example, 1,500 silicon films 4 are grown.

Next, as shown in FIG. 1(b), a polycrystalline silicon film 4
An oxide film 5 is formed on the top at 950'C for 5 minutes with steam.
After growing to 00 people, for example, arsenic is accelerated with energy E=7
It is implanted at 0 keV with a dose of Φ-1〆10'' cm-2 and annealed for 60 minutes in N2 at 950°C.At this time, emitter vines of NPNI to Lancistor may be formed at the same time. After growing a silicon nitride film 6 on the oxide film 5 to a thickness of, say, 500 nm, the silicon nitride film 6 is left only on the portion of the oxide film 5 where the dielectric film of the capacitor will be formed using photolithography. Remove the others.

Next, as shown in FIG. 1(C), the photoresist film 7
Using a method, the polycrystalline silicon film 4 and oxide film 5 forming the lower electrode of the capacitor and its lead-out portion are left, and the other portions of the polycrystalline silicon film 4 and oxide film 5 are removed.

After that, the photoresist film 7 is removed, and the oxide film 5 remaining and exposed on the polycrystalline silicon film 4 is removed using hydrofluoric acid or the like.
An extended portion of the lower electrode is formed using polycrystalline silicon film 4.

Next, as shown in FIG. 1(d), after forming a first aluminum film on the entire surface, the first aluminum film is etched by photolithography to form a capacitor in the area where the co-temp is to be formed. An aluminum electrode 8a, which becomes a partial electrode, and an aluminum electrode 8, which serves as a lower electrode and connects to an extended portion of the polycrystalline silicon film 4, are formed at the same time. At this time, in the case of a master slice product or the like, a first aluminum wiring layer (not shown) may be formed at the same time.

Next, as shown in FIG. 1(e), the interlayer insulation M 10
For example, a plasma silicon nitride film is grown to a thickness of 1 μm. Note that for planarization, a silica glass film or the like may be further formed to form an interlayer insulating film made of a multilayer film.

Next, the interlayer insulating film 1 is formed using photolithography technology.
A through hole (not shown) is formed at a predetermined position of 0.

Next, after forming a second aluminum film on the entire surface, the second aluminum film is etched using photolithography technology, and bonding pads are formed on the interlayer insulating film 10 on the polycrystalline silicon film 4 that does not form a co-temperature. 11, a second aluminum wiring layer (not shown) can be formed at the same time in the case of a master slice product or the like.

2(a) to 2(c) are step-by-step cross-sectional views for explaining the second embodiment of the present invention.6 First, as shown in FIG. 2(a), an N-type epitaxial layer] A field oxide film 2 is formed thereon, a silicon nitride film 3 of, for example, 1,000 layers is grown on the field oxide film 2, and then a polycrystalline silicon film 4 of, for example, 1,500 layers is grown on the entire surface.

Subsequently, after growing a thin oxide film 5 on the polycrystalline silicon film 4, for example, arsenic is heated to an acceleration energy of E70 k e V.
, implanted at a dose of Φ-I x 1016 cm-2, and annealed for 60 minutes in N2 at 950°C. At this time, the emitter of the NPN transistor may be formed at the same time.

Next, by using a first lithography technique, only the portion of the oxide film 5 that will form the dielectric film of the capacitor is left, and the other portions are removed.

Subsequently, using a photoresist film 7, the polycrystalline silicon film 4 that forms the lower electrode of the capacitor and its extension portion is left, and the other portions of the polycrystalline silicon film 4 are removed.

Next, as shown in FIG. 2(b), after removing Photosis 1 to film 7 and forming a first aluminum film on the entire surface, the first aluminum film is etched using photolithography technology. In the part that forms the capacitor,
Aluminum electrode 8a serving as a two-part electrode for the balance wheel
and an aluminum electrode 8 which is connected to the extended portion of the polycrystalline silicon film 4 serving as the lower electrode are formed at the same time.

At this time, in the case of a master slice product or the like, a first aluminum wiring layer (not shown) may be formed at the same time.

Next, as shown in FIG. 2(c), for example, a plasma silicon nitride film is grown to a thickness of 1 μm as the interlayer insulating film 10. In addition, for flattening, a silica glass film etc. is further formed.
The interlayer insulating film 10 may be formed of a multilayer film. Subsequently, through holes (not shown) are formed at predetermined positions in the interlayer insulating film 10 by photolithography.

Next, after forming a second aluminum film on the entire surface, the second aluminum film is etched using photolithography technology, and the interlayer insulating film 10 on the polycrystalline silicon film 4 on which no capacitor is formed is etched. A bonding pad 11 is formed on. At this time, in the case of a master slice product or the like, a second layer of aluminum 9m wiring layer (not shown) can be formed at the same time.

In this embodiment, since the dielectric film of the capacitor is only the thin oxide film 5, there is an advantage that the capacitance per unit area can be increased, and even if the capacitor size is unified to the bonding pad size, it is sufficient. capacity.

〔Effect of the invention〕

As explained above, the present invention uses polycrystalline silicon for the lower electrode of a capacitor, thereby forming a capacitor on which a metal electrode is not formed as an upper electrode, but a polycrystalline silicon film and a dielectric film are formed as a lower electrode. , it becomes possible to form a bonding pad through the glabella insulating film.

This means that a bonding pad is formed on this capacitor, and even if cracks occur in the dielectric film of the capacitor due to strain caused during the bonding process, there is a target that will short-circuit with the polycrystalline silicon film that is the lower electrode. This is to prevent it from happening.

In addition, since the bonding pad can be formed on the capacitor mentioned above, there is no need to form the bonding pad on the periphery of the semiconductor chip. It becomes possible to form a capacitor. From this,
This has the effect of increasing the degree of integration and reducing the chip size.

[Brief explanation of drawings]

1(a) to (e) are step-by-step sectional views of the first embodiment of the present invention, and FIG. 2(a)-(c) are step-by-step sectional views of the second embodiment of the present invention. FIG. 3 is a sectional view of an example of a conventional semiconductor device.

Claims (1)

[Claims] 1. A step of depositing a polycrystalline silicon film on an insulating film, a step of forming an insulating film on the polycrystalline silicon film, and introducing an impurity into the polycrystalline silicon film by ion implantation. a step of etching the insulating film on the polycrystalline silicon film leaving a portion to be used as a dielectric film of the capacitor; and a step of etching the polycrystalline silicon film to form a portion under the dielectric film of the capacitor. a step of forming an electrode of the capacitor by leaving the polycrystalline silicon film on the lead-out portion; a step of forming a first metal film on the entire surface; and a step of etching the first metal film to form the capacitor used as a capacitor. forming a metal electrode as an upper electrode on the dielectric film of the capacitor, and forming a metal electrode as a lower electrode on the extended portion of the polycrystalline silicon film under the dielectric film of the capacitor used as the capacitor. A step of forming an interlayer insulating film on the entire surface and forming a through hole, a step of forming a second metal film on the entire surface, and etching the second metal film to form at least one capacitor that is not used as a capacitor. A method for manufacturing a semiconductor device, comprising the step of forming a bonding pad on a dielectric film via the interlayer insulating film. 2. In a master slice product having a capacitor and two metal wiring layers, a first metal wiring layer is formed by etching the first metal film, and a first metal wiring layer is formed by etching the second metal film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a second metal wiring layer.