JPH03220770A - Image sensing device - Google Patents

Abstract

PURPOSE: To enable an image-sensing device to be lessened in size with high resolution and pixel density. CONSTITUTION: An image-sensing device is equipped with a planar array of photo sites 2, an address decoder 10 which receives address input data, a series of resistive gate CCD charge transfer channels 8, so coupled as to receive charges transferred from a columnar arrangement related to the photo sites 2 in the planar array, a transfer channel 8 driven by and coupled to a scanner circuit 28 where a traveling wave drive circuit 40 is used, and a charge-storage well 14 for storing charges transferred to the related transfer channel 8 out of the transfer channels 8. A traveling wave drive circuit 30 is equipped with a pair of inverters between an RC network 36 and a delay line 32, keeping an interval between them and tap points selected by a large current drive device 38 connected to a resistive gate 26. In this case, charge is received from the storage well 14 and read out as image signals. By this setup, an image sensor which is high in resolution and pixel density and small in size can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a novel high performance charge-coupled device CCD image sensor for use in optical imaging devices. More particularly, the present invention relates to a novel device design and architecture with improved sensitivity and charge carrier control, while simultaneously having greater pixel density and smaller sensor dimensions.

[Conventional technology and problems]

A key problem with all solid-state image sensors is the need for efficient detection of the image signal and the conversion of the image into pixels of charge representing the image signal, as well as the need to transfer the image signal to the sensor output terminal. Calling and carrying out at high speed and in a predetermined order. The CCD method is most commonly used for this purpose. This is because it is inherently easy to manipulate and transport charge within silicon chips. However, the drawback of the CCD method is that a wide charge transfer channel is required, which uses up a lot of valuable image sensing area, and the sensitivity to collecting stray charges is also an issue. This causes blurring of the image. There is always a need for image sensors with high resolution, high pixel density, and small dimensions, and therefore there are several ways to improve CCD image sensors to overcome these limitations in sensor characteristics. technology has been developed.

One technique to improve performance in this way is to combine line-to-line transfer IT architecture commonly used in CCD image sensors with charge sweep techniques.

(Ultra-compact TV camera using K. Takasbima's rcsD device,” Image Technology and Information Display, Vol. 20, No. 9,
(pp. 47-51, May 1988) This technique significantly reduces the dimensions of the vertical charge transfer channels placed between the columns of the photosite sensing element, thus significantly increasing the quantum efficiency of the CCD. Improved. However, the time required to carry charge away from the sensing elements in the array is relatively long, and the problem of undesirable smearing has not been completely solved.

The present invention discloses a novel image sensor and method thereof that solves the problems of conventional CCD image sensors and has high resolution, high pixel density, small size, and significantly improved characteristics. do. A novel sensor architecture using charge superswept (C3S) technology is presented to overcome the problems of conventional COD such as blue-5ing and image smearing. The present invention also provides an image sensor using electronic focal plane shutter technology with inherent exposure control with a single or variable scan rate.

Charge supersweep technology rapidly transfers multiple lines of data from photosites located anywhere in the pixel array to a buffer storage region located at the bottom edge of the sensor's image sensing area. be able to.

This transfer is performed during every horizontal blanking interval, or, if transfer of an entire frame of data is required, only during vertical blanking intervals.

For image sensors with frame transfer capability, one or more on-chip analog field storage devices are incorporated, similar to conventional frame transfer CCD sensors. This sensor is also used in still image photography applications.

Charge superswept C3S technology utilizes all narrow vertical channels placed between photosites, similar to line-to-line transfer IT devices. However, the characteristics of C3S technology are
The charge from the photosites is stored in the channel for only a short time and is transported out using a resistive gate traveling wave technique. The narrow channel minimizes loss of photosensitivity, and traveling wave sweeping maximizes charge transfer efficiency within the narrow channel by using field-enhanced charge carrier transfer effects.

[Purpose and summary of the invention]

The main objective of the present invention is to provide a novel CCD/C3S image sensor and its manufacturing method using traveling wave charge supersweep technology.

Another object of the present invention is to provide an architecture for a novel CCD/C3S image sensor.

Yet another object of the present invention is to provide a novel photosite device for a CCD image sensor and to provide process steps for integrating a novel COD photosite device and a CMO3 structure on the same chip. be.

Yet another object of the present invention is to provide a novel sense amplifier circuit for a CCD image sensor.

Yet another object of the present invention is to provide a novel scanner circuit for use with CCD/C3S image sensors.

With said object in mind, the present invention provides a planar array of photosites, an address decoder receiving address input data and coupled to said photosites, and an associated columnar array of photosites in said array. a series of resistive data 1-CCD charge transfer channels coupled to receive charge transferred from the scanner circuit; a series of said transfer channels coupled to and driven by said scanner circuit; a series of charge storage wells for storing said charge transferred to associated transfer channels of said storage wells; and a plurality of charge storage wells for receiving charge from associated one of said storage wells and reading out said charge as an image signal. This is accomplished by registers.

Yet another embodiment of the invention provides a connection between an associated one of the storage wells and the register such that the charge in the register is read out into a number of selected output channels. It has a series of multiplexers that combine.

Yet another embodiment of the invention has multiple field stores coupling said registers and said multiplexer for storing and processing entire frames of data.

〔Example〕

Figures 1a to 1c are CCD images according to the prior art.
FIG. 2 is a schematic diagram of a sensor. A planar array of photosites 2, shown as diodes, is created in a semiconductor substrate (not shown). Each of the photosites is coupled to an associated charge transfer gate 6 by a charge transfer device 4, for example a transistor. Charge transfer gates 6 form a vertical columnar array on an insulator layer 7 disposed above vertical charge transfer channels 8 in the substrate. The address decoder 10 receives an input control signal and thereby controls the charge transfer device 4 of a selected row to transfer the charge stored in the photosites 2 to the associated vertical charge transfer channel 8. A scanner 12 is coupled to every transfer gate 6, thereby sequentially sweeping the transfer channel 8 as a distinct horizontal row of charge representing a line of signal to the associated charge storage well 14 of a row. Charge can be carried out into the . When voltage pulse φ3 is applied, storage well 1
A charge is held in 4. This continues until the next voltage pulse φt9 applied to the associated charge transfer gate 16 transfers a row of charge to the series of horizontal registers 18. This charge is then transferred to the applied voltage pulse φs
Under the control of rl + φsr2 + . . . , it is read out from the horizontal register as a line of image signals. FIG. 1c shows a charge storage potential well 22 and a horizontal register potential well (24) along the vertical charge transfer channel.
) shows the potential distribution of the charge row 20 when it is carried out.

Thin vertical charge transfer channels with smaller potential well capacitance due to the ability to call out distinct lines of charge 8
can be manufactured. This is because the charge stored on an individual photosite can span several vertical stages within the COD. However, due to the narrow width of the vertical charge transfer channels 8, the charge transfer efficiency is compromised and one line of charge or signal can be transferred from the top of the array to the bottom during a single horizontal blanking interval. 0 Cannot be transferred. This complicates the timing of the image sensor and also results in long charge accumulation in the vertical charge transfer channels. In this case, additional stray charges from other photosites within the CCD can accumulate, resulting in smearing of the image. There is also the problem of clock signal feedthrough from storage register 14 to horizontal register 18. This is because these registers must be active during the readout period as a result of the inability to completely transport charge from the vertical transfer channel 8 within the blanking period.

A vertical clocking frequency on the order of 100 MHz is used to transfer a line of charge across the entire height of the image sensor during the few microseconds available within the horizontal blanking period of the imager of the present invention. required for 3 vertical COD photosites. Such a locking frequency is difficult to achieve considering the relatively large loading capacitance of the vertical charge transfer gate 6. During this time, the number of points of illumination is further doubled due to the requirement for a thin vertical charge transfer channel as described above.

An attempted solution to the fast charge transfer problem is to use a segmented array of charge transfer gates 6 in R,
Zimmermann's "RC;'S Image Sensor for Black and White Cameras", Electronics, Vol. 32, No. 12
No. 93-92, June 1983, and R.E.
"R GHzGaAs CCDs: Promises, Problems, and Progress," by Corbes et al., Proceedings on
5PIE, Volume 1071, Pages 108-114, 198
The solution is to replace it with a series of continuous columnar resistive gates, as proposed in January 2009. The advantage of using a resistive gate is that there is a large lateral electric field along the direction in which charge is transported. This greatly enhances the transport rate of charge carriers according to the following equation:

■ Electric field, ■ is the voltage applied between the charge transfer gates, L is the length of the charge transfer gates (carrier movement length),
Also, L,=τμEt. where τ is the average travel time of charge carriers, μ
is the charge mobility.

However, a significant drawback of resistive gate approaches is the high power consumption of any device using this technology.

Conventional multiphase CODs can turn on tens or potentially hundreds of parallel-connected charge transfer gates with each clock pulse for large arrays. The resistive loading of all parallel-connected charge transfer gates is then very low, and it is not possible to incorporate suitable drive circuitry on the same chip with the imaging array.

This is because it requires a very large amount of power.

A novel super-sweep (COD/C35) scheme that overcomes the above-mentioned limitations is shown in Figures 2a-2c. Figures 2a-2c are similar structures to Figures 1a-1c, except that the segmented vertical charge transfer gate 6 is replaced by a continuous vertical resistive gate 26, and As shown in Figure 2a, a novel scanner 28 using a traveling wave drive circuit 30 is used to sweep the charge using a resistive gate 26 below the vertical charge transfer channel 8. Traveling wave drive circuit 3
0 is created as a linear delay line 32. The formation of this linear delay line is shown as one example, and is not meant to be limiting. The traveling wave drive circuit 30 includes an inverter 34 arranged at a distance between the distributed RC circuit wAa6 and the delay line 32.
and has a tap point at a selected point by a high current driver 38 coupled to resistive gate 26. FIG. 2b shows the potential distribution of one column of charges or lines 40 of the signal as the charges are carried away along the vertical charge transfer channel 8 to the charge storage well 14.

When this new CCD/C3S image sensor is used, the power consumption is significantly lower than that of conventional COD image sensors. That is, if the 0M03 circuit is used to configure this drive,
This is because at any selected time, current will flow in only a small number of driver stages 38 that are transitioning from a high level to a low level or from a low level to a high level.

Therefore, the on-chip load for a CCD/CS S image sensor corresponds to a single row of charge from a single row of photosensors connected in parallel, which requires a drive current that can be easily managed by the present invention. shall be.

The charge in the vertical charge transfer channel 8 of a CCD/C3S image sensor is carried away over the entire height of the image sensor by a traveling wave electric field in about 1 microsecond or less. This complete and fast delivery of the charge transfer channels allows for the sequential transfer of multiple lines of data within the horizontal blanking period, allowing for the selection of five photosites to facilitate exposure control. Another advantage of using these channels is to remove stray charges from the charge transfer channels due to unnecessary charge transport and blooming overflow of charge during the charge integration time within the photosites.

This fast charge transfer is also beneficial in reducing sensor bleed.

The two basic imaging system architectures using CCD/C3S image sensors described above allow imaging devices with significantly improved performance over the prior art. The first such architecture is shown in FIG. Basic CCD/C3 shown in Figure 2b
In addition to the S image sensor, clearing gate 4
6 and a drain 44 are located near the bottom of each vertical charge transfer channel 8 so that the clearing gate 6 can be passed to the storage register 14 or through the charge clearing gate 46 to the drain 44. . A series of multiplexed charge storage gates 48 are connected to the two multiplexers so that the correct timing pulses φ1llXI+ from these multiplexers
With φmx2 and the correct timing pulse φt9 from the register transfer gate 16, charge can be transferred into a series of horizontal storage registers 18 for multi-channel readout of the image signal to an associated series of amplifiers. . A second vertical clearing drain 50 is located at the bottom of the horizontal register 18, thereby
During the read time interval, unnecessary charge can be carried away from the register. This first system architecture is similar to prior art line transfer devices (LTD). However, the LTD charge side-swept TD/C architecture allows any row or pair of rows of photosites to represent a line or line pair of image signals on the photosite array within a single horizontal blanking time interval. The benefits of calling and reading can be changed. Moreover, during the same time interval this function can be performed and 7 carry out unnecessary charges from the photosites 2, the vertical charge transfer channels 8, the storage registers 14 and the horizontal registers 18. be able to. By comparison, conventional CCD imaging systems are unable to completely clear a single line of signal throughout the height of the imaging play during the horizontal blanking time interval.

A second imaging system architecture using a novel CCD/C3S image sensor is shown in FIG. This architecture is similar to that in Figure 3, except that this embodiment has a single charge storage register 14 at the bottom of the imaging array and reads out the entire frame of the signal. There are two field stores 52 disposed between the multiplexer gate 48 and the horizontal register 18 so that the data can be stored therein. Traditional frame-to-line transfer (FI
T) Architecture to frame store, in parallel,
Required transfer of all lines of signal across the sensor. This new C3S scheme allows the transfer of individual lines of signals to the frame store. If desired, a charge clearing sweep of the vertical charge transfer channels can be performed between such individual transfers.

Therefore, this new FIT/C3S imager provides unique exposure control and anti-bluing control that was previously unparalleled. LTD/C3 in Figure 3
The S architecture is primarily used for movie cameras or still image cameras with mechanical shutters, while the field storage of the second architecture is used for still video cameras.
It can be used with cameras and has variable speed electronic focal plane shutter performance.

In the timing diagrams of FIGS. 5 and 3, the TD/C
A more detailed description of the 3S imaging system architecture is given.

The operating cycle begins as follows. That is, during the horizontal blanking time interval, a binary address 9 is input into the address decoder 10 and a charge transfer pulse is applied to the transfer gate 4 of the selected photosite 2. This carries unwanted charge away from photosite 2 and determines the starting point of the charge integration period. After this cycle is completed, if the device is designed for dual line readout, it also clears the charges on the photosites 2 of another line.

Here, the charge resides in the vertical charge transfer channel 8 and can be carried away to the buffer storage area represented by the horizontal register 18. To remove unnecessary charge and to control blueprinting, charge clearing gate 46 can be used to remove vertical charge transfer channels 8 as needed at any time during the operating cycle of the device. Charge can proceed from the charge storage well 14 to either the charge storage well 14 or the drain 48 . To prevent residual reverse charge flow into photosite 2, vertical charge transfer channel 8 is always used before charge transfer from photosite 2.
can also be cleaned. It is in practice preferable to perform a charge clear sweep before transferring correct 0 data into storage well 14.

Blooming protection can be incorporated into the LTD/C3S sensor device by using a vertical overflow drain within each photosite 2, as is commonly done in conventional CCD imagers. However, this unnecessarily complicates the manufacturing process and is not used in newer LTD/C3S imagers. The vertical overflow drain also reduces sensor light sensitivity in the long visible H@ wavelength portion of the spectrum and in the near infrared region. This is an undesirable drawback if the imaging device is to compete in surveillance and security applications. therefore,
Blooming control of the LTD/C3S imager is performed as described above by transporting photosite overflow charge from the vertical charge transfer channel before each transfer in each horizontal blanking interval.

1 Traveling wave drive circuit 30 cooperates with the resistive gate 26 of the novel CCD/C3S image sensor to enable such rapid charge transport and subsequent blue-gong control.

After the vertical charge transfer channel 8 is cleared of unnecessary charges, it is ready to receive charge from the selected photosites 2 representing one line of the image signal.

the decoder binary code input to the address decoder 10 is changed to the appropriate address and the charge in the corresponding photosite 2 is transferred to the vertical charge transfer channel;
Then, it is carried out into the storage well 14. In this process step, the address is changed by a reduction corresponding to the number of lines representing the width of the focal plane shutter. A second line of signals can immediately follow this step, or a clearing sweep can be inserted between the lines of signals to erase stray charges. Since the maximum charge sweep time is on the order of milliseconds, the degree of bleeding is very small. Even if the vertical charge transfer channel (8) is not completely protected by a light shield, the smear signal is small due to the fast sweep time provided by the new image sensor. The smear signal is approximately determined by the ratio of charge sweep time to charge accumulation time at the photosite. For example, a test pattern that covers one-tenth of the image height is 982
For a CCD/C3S with lines, this ratio is 0
．． Only 61%. If a standard aluminum light shield is used in the image sensor, this value can easily be improved by at least two orders of magnitude.

The buffer storage area of the novel image sensor device can be configured to hold several lines of data in the storage well 14, as shown in FIG. 3, or as shown in FIG. It can be expanded to hold data from all sensors in field storage 52, as shown in FIG. In the latter case, the device also has variable speed electronic focal plane shutter capability.

A line of photosites 2 can be cleared in rapid sequential sweeps 3 and the entire image sensing area can be reset within 1 millisecond. The signal can then be integrated into the photosites 2 within the next time interval and rapidly transferred into the buffer storage area again. Other combinations of tying are also possible. In this case, the scanning speed is the maximum speed mentioned above and 1 second
The standard TV speed is chosen to be somewhere between 730 and 730.

This feature is most useful in still image cameras where it resembles the action of a mechanical focal plane shutter with both variable slit width and variable speed.

Once the signal is transferred to the storage buffer area, it is easy to multiplex it into any number of formats and transfer it to the horizontal register 18 for reading. 1 selected for the new CCD/C3S image sensor
The example format allows the signals in the four photosites 2 to be read out through the four serial registers 18. The second and fourth registers have the signals from the odd and even photosites 2 of the even lines of signals, and the third and fourth registers have the signals of the odd and even pixels of the odd lines of signals. have Since line addressing is done through decoder 10, the order of line addressing is not fixed and can change from field to field if interlaced dual line readout is required. This selected multi-channel output allows high speed data readout from the sensor using a moderate clock frequency of 12.8 MHz. This is an important advantage for output amplifier designs that must have high gain and low noise.

Important to the development of the new CCD/C3S image sensor is a new scanner 28 that incorporates a new traveling wave drive circuit 30 necessary to create the charge sweep time in the vertical charge transfer channel 8. Traveling wave drive circuit 3
A circuit 5 diagram of one embodiment of 0 is shown in FIG. This new CCD/C3S
For the actual operation of the image sensor, identical C0Ms arranged in two rows are placed on either side of the photosite array to minimize the propagation delay to the center of the array.
Five large current drive devices 38 are arranged. Driver 38 receives a signal from delay line circuit 32 . Delay line circuit 32
consists of a chain of CMO3 inverters 54 interconnected by an RC distribution circuit 34, as shown in FIG. The parameters of the circuit are chosen such that the delay of the signal through the circuit is slightly greater than the propagation velocity of the electrons in the vertical charge transfer channel. This ensures maximum transfer speed and good transfer efficiency.

For efficient design of CCD/C3S image sensors, the above equations defining electric field strength and carrier travel length do not necessarily require having one driver 38 for each row of photocells 2. Show that. In order to meet design rules for sensor manufacturing, a few rows can be skipped and still save space for the six transfer gate address buses. However, it is still necessary to place a dummy metal line between the scanner and the photosite array to preserve optical symmetry and uniformity of the optical response of the photosites.

Important for good low noise characteristics of COD image sensors is the charge sense amplifier. Typical charge conversion sensitivities of conventionally used sensors are about 4.0 to 10.
It is on the order of 0 microvolts/electron. This characteristic is insufficient for image sensors having dense photosite arrays where the charge stored in each photosite is only a few electrons. FIG. 7 is a diagram illustrating a charge sensing node and a charge sensing amplifier according to the prior art. Stray diffused charge storage region 55 is located on semiconductor substrate 58
is created in a buried channel region 56 of the channel.

Stray diffused charge storage region 55 is typically created in direct contact with an output gate 60, which is typically metal, connected to a conventional dual stage source follower output circuit 62. This is the case. The charge conversion sensitivity of such a typical detection node is reduced. That is because of the noise arising from some parasitic capacitances present in the detection node and the amplifier circuit, as shown in the figure.

This circuit also has large kTC noise. At this time,
The capacitance of the sensing node is the sum of parasitic capacitances. That is, cd=Cdb+C09+Cr, 9+C9d+Cg5, which severely limits the low noise characteristics.

FIG. 8a is a diagram of a novel charge sensing node structure and charge sensing amplifier circuit that minimizes the kTC noise and parasitic capacitance that limit the low noise performance of current CCD sensors. . This novel amplifier circuit is created using CMO3 technology, which allows a high performance feedback amplifier to be designed on the same chip as the CCD sensor array. In the novel charge sensing node of FIG.
8 is not in direct contact with it, is separate from it, and is capacitively coupled to it by an insulator layer 64. In yet another embodiment of the novel detection node, the stray diffuse charge detection region 55 can be eliminated altogether and replaced with, for example, an N-type well.

A novel high performance feedback amplifier circuit 66 is connected between the charge detection node and the dual stage source follower circuit 68. Ql, Q2. Q3. Q4. Q
5 and Q6 are transistors. Positive feedback allows nearly infinite open loop gain to be converted into a single stage, which is important for high speed circuit performance. At the same time, negative feedback to node D through node C minimizes the detection parasitic capacitance that reduces charge conversion sensitivity. For the new capacitively coupled charge sensing node, the node capacitance is given by Cd=Cdb+Cag.

Because of the negative feedback provided through capacitor Ct between nodes C and D, amplifier 966 must be reset periodically, but to a bias reference level that is different from the voltage at the charge sense node. This reset consists of parallel connected transistors Q13 and Ql4 connected across capacitor C7 and applying true and complementary reset pulses φars + φ3. to their respective input gates. ．． This is done by amplifier reset switch 70, which receives s. Taking into account the difference in bias voltage reference levels, the charge detection node is coupled to the amplifier circuit input through a capacitor Cin.

The technical advantage of this novel charge sensing node structure is that it requires a large area area by eliminating the DC connection between the output gate 60 and the stray diffused charge collection region 55, as seen in the prior art. It is possible to eliminate the contact structure. This new feedback amplifier 66
The dual stage source follower circuit 68 coupled to is of conventional design and has adequate drive capability for off-chip loads. P channel・
N-channel transistors Q7.0 with transistors QB, Q11, and Q12. The combination of Q9, and Q10 is such that the difference in dark value voltage of these stages is compensated for and the output signal V. U.

is selected to provide a positive dc bias level for.

One example of the operation of this novel charge sense amplifier with a capacitively coupled charge sense node having a stray diffused charge storage region 54 can be seen with reference to Figure 9a. Initially, the voltage bias level of stray diffuse charge detection region 55 is reset by a short pulse.

At the same time, the amplifier circuit 66 resets the reset switch 70
However, it is reset with a longer pulse to cancel the kTC noise generated at the detection node. After this amplifier reset pulse is released, the charge held by the CCD register is transferred to the detection node.

The time interval between reset release and charge transfer is utilized by the clamp pulse to cancel the kTC noise generated in the amplifier feedback capacitor Cf. After the amplifier's response to the received charge has settled to a stable level, its output can be sampled. This sampling and clamping is performed in off-chip signal processing circuitry.

FIG. 8b is a drawing of yet another embodiment of the novel charge detection mode/charge amplification circuit. In this example, the N-type stray diffusion region is replaced by an N-type well. The potential distribution for this node is shown in dotted lines above the node structure. Due to the absence of N+ spreading region 55, no kTC noise occurs within the detection node itself. This is because the charge transfer from the detection well replacing the diffusion region is complete. In this case, the amplifier kT
It is only necessary to remove the C noise.

It is also possible to reset the amplifier only once per charge transfer of a row of photosites rather than for all photosites which completely cancels the kTC noise.

FIG. 9b is a timing diagram for the embodiment of FIG. 8b showing the operating pulse sequence for this embodiment. Note that the amplifier reset pulse and reset gate pulse can coincide. φc12
．． 4 and φ. , 1.3 indicates that there is only one such pulse per line during the dark reference pixel.

The process for assembling the CCD/C3S image sensor is a double poly single level metal P-well CMO3 process. The design rules are relatively traditional, with most array dimensions being 1.6 microns and contact hole dimensions being 1.2 microns. The P-type well area in the peripheral circuit area is the same as the P-type well area for the CCD register.

This greatly simplifies a complex process. The CCD structure incorporated in this process is a two-phase double polyN
It is a shaped embedded channel COD.

Figures 10a-10c illustrate the basic steps of this simplified manufacturing sequence. The first major processing cycle is the ion implantation and diffusion of a P-type well 72 into an N-type semiconductor region 74 created in an N-type semiconductor substrate 78. A thick field oxide 80 is then grown. This field oxide 80 surrounds the active area of each transistor and the CCD array. This thick field region is also implanted with a suitable channel stop implant (not shown) prior to oxidation to prevent the formation of parasitic conduction channels. Thereafter, a first gate oxidation, implantation of a buried channel region 82, and first polycrystalline silicon deposition are performed. After this first polycrystalline silicon is deposited, it is preferably doped with a slight boron impurity to create resistive gate 84. This polycrystalline silicon is capped by depositing silicon dioxide 86, and then resistive gate (CCD/C3S)
Patterned to define areas of charge transfer channels. The exposed polycrystalline silicon is then again doped with boron to increase its conductivity.

The CCD channel stop region is defined by implanting 4 boron through the first polycrystalline silicon. The important feature to note here is the vertical CC
The patterned lid oxide 86 deposited over the D channel serves to self-align the CCD channel stop region 90 and the resistive gate. The first polycrystalline level 84 is then etched using the combination of photoresist and cap oxide 86 as a mask. After this step, the thin gate oxide 86 is etched away, a second gate oxide (not shown) is grown, and the interlevel isolation for the second level polysilicon 94 is replaced. This is followed by a COD barrier implant and a blanket implant of dark value shift adjustment for the peripheral circuitry. The subsequent steps include forming a second polycrystalline silicon gate.
Level 92 deposition, doping, and patterning stages. The last important step in this process sequence is
This is the stage of creating a photosite gate. The selected photosite structure is based on the practical state concept, and the practical gate 94 is created by a shallow boron implant. The remaining process steps are 0MO3
) implantation steps of N+ source regions 96 and N+ drain regions 98 and P+ source regions 100 and P+ drain regions 102 for transistors, interlevel oxide deposition steps and contact holes for metal interconnects; opening, depositing and shaping a metal bus interconnect, depositing a protective oxide coating, and finally depositing and shaping a light shield for the image sensor. This is the stage of determining the The process is completed by etching away the oxide from the bond pads.

11 and 12 are drawings showing the design configuration of the most important areas of the device. Figure 11 is photo site 2
It shows the arrangement of. The important features to note here are:
The metal bus 104 is placed in contact with the resistive gate 84.

A contact hole for the first polysilicon level is created above the 6 channel stop region 90, but not above the active CCD/C3S channel.

This eliminates parasitic potential wells that would otherwise occur in the CCD channel due to changes in the polysilicon gate work function due to alloying of polysilicon and aluminum. Therefore, the drive signal for the resistive gate 84 is applied to the P doped region 9 extending from the contact hole.
0, fed laterally. The photosite 2 itself is actually a combination of a well and a clocked barrier structure, as shown in FIG. The practical gate concept has the advantage of complete charge transfer from the photosites 2, which prevents image delay.

Another important feature in the architecture of this new device is the interface between the CCD/C3S vertical charge transfer channels 8, the storage wells 14, and the multiple horizontal shift resists 18. These are shown in FIG. As shown in FIG. 12, superswept charges are accumulated 7 in two rows of accumulation wells 14. This charge can also be passed through gate 42 towards charge clearing drain 44 . Here, two rows of acquisition wells are used, so that the storage for the transfer of two lines of data is changed within one horizontal blanking period. A multiplexing gate 48 is connected to the charge storage region to redistribute charge from the horizontal photosite pairs to the vertical sequence. The charge from these regions is then transferred to transfer gate 1
into multiple horizontal registers 18, separated by 6. The transfer gate of the outermost register interfaces this register with a charge clearing drain 50. Charge transfer among all regions shown in FIG. 12 can be easily understood in this figure as charge flows from well to well in response to the bias applied to the corresponding gate.

Regarding the above description, the following sections are further disclosed.

(1) a planar array of photosites disposed within a semiconductor substrate and accumulating charge carriers in proportion to incident light; a series of elongated columnar charge transfer channels coupled to receive the accumulated charge carriers from the rows; and a plurality of components each disposed over an associated charge transfer channel in the charge transfer channel. a scanner coupled to provide control pulses to the plurality of elongated components to control movement of the stored charge carriers within the charge transfer channel; an image sensor device comprising: a device for storing a stored charge;

(2) The imaging device of paragraph 1, further comprising an address decoder for addressing a selected row of photosites for transferring the accumulated charge carriers to the charge transfer channel.

9(3) The imaging device of paragraph 1, wherein the elongate component is a resistive gate.

(4) The imaging apparatus of paragraph 1, wherein the scanner has a traveling wave drive circuit coupled to send traveling wave pulses to the elongate component.

(5) In clause 4, the traveling wave drive circuit has a delay line, and the delay line is coupled between the elongated component and the delay line at a selected point along the delay line. An imaging device having multiple high current drivers.

(6) a planar array of photoarrays that store charge carriers in response to incident light; and a series of elongated charge transfer channels coupled to receive the stored charge carriers from selected rows of the photosites. , an address decoder for transferring the accumulated charge carriers in the selected row of the photosites into the charge transfer channel; and an address decoder for transferring the accumulated charge carriers in the selected row of the photosites into the charge transfer channel; a scanner coupled to the charge transfer channel for controlling motion; a storage device for storing the accumulated charge carriers of a plurality of discrete rows of the photosites; a readout device for selectively reading out the accumulated charge carriers as a multi-channel output signal.

(7) In clause 6, said elongate charge carriers are connected to said elongate charge carriers by a series of associated elongate components coupled to transmit pulses from said scanner to control movement of said accumulated charge carriers within said charge transfer channel. An architecture in which a transfer channel is coupled to said scanner.

(8) The architecture of clause 7, wherein the elongated components are resistive gates overlying respective charge transfer channels.

1 (9) The architecture of claim 7, wherein the scanner has a traveling wave drive circuit coupled to provide traveling wave pulses to the elongate component.

00) In paragraph 1, the accumulated charge carriers in the charge transfer channel are cleared by a number of clearing channels.
The architecture further comprises a series of clearing gates coupled between the storage device and the series of charge transfer channels for selectively advancing to a drain.

(10) The architecture of claim 1, wherein the readout device includes a pair of multiplexers coupled between the storage device and a multichannel output of the imaging device.

[theta]f Clause 9, wherein the traveling wave drive circuit has a delay line, and the delay line is coupled between the elongated component and the delay line at a selected point along the delay line. architecture with multiple high current drivers.

(6) a planar array of odosites (accumulating charge carriers in response to incident light); and a series of elongated charge transfer channels coupled to receive the accumulated charge carriers from selected columns of the photosites. , an address decoder for transferring the accumulated charge carriers in a selected row of the photosites to the charge transfer channel, and controlling the movement of the accumulated charge carriers within the charge transfer channel. a scanner coupled to the charge transfer channel for storing the total of the accumulated charge carriers of the entire planar array; and a multichannel output of the accumulated charge carriers of the entire array. An architecture for an imaging device comprising: a readout device for selectively reading out signals;

041 In clause 13, said elongated charge carriers are connected to said elongated charge carriers by a series of associated elongated parts coupled to transmit pulses from said scanner to control the movement of said accumulated charge carriers within said charge transfer channel. An architecture in which a transfer channel is coupled to said scanner.

05) The architecture of clause 13, wherein the elongate components are resistive gates overlying respective charge transfer channels.

06) The architecture of clause 13, wherein the scanner has a traveling wave drive circuit coupled to provide traveling wave pulses to the elongate component.

071 In clause 13, between the storage device and the series of charge transfer channels such that the accumulated charge carriers in the charge transfer channels can be selectively advanced to a plurality of clearing drains. further comprising a series of clearing gates coupled to the
architecture.

0IID Clause 13, wherein the readout device comprises a pair of multiplexers coupled between the storage device and a multi-channel output of the imaging device.
architecture.

409) Clause 13, wherein the traveling wave drive circuit has a delay line, and the delay line comprises a coupling between the elongated component and the delay line at a selected point along the delay line. architecture with multiple high current drivers.

detecting the image on an array of photosites each accumulating a charge in response to light transmitted by the C2G+ image; selecting one row of the photosites for processing; transferring the charge accumulated by the row of photosites representing a first line of the imager to an associated series of charge transfer channels; transporting to a storage buffer adjacent to an array; the detecting, selecting, forwarding, and transporting steps for at least a second line of signal within the single horizontal blanking interval; 5. reading the first line and the second line of signals from the storage buffer as multi-channel output signals from the imager. processing method.

21. The method of claim 20, further comprising performing a first charge clearing sweep of the charge transfer channel before selecting the row of photosites.

22. The method of claim 20, further comprising a second charge clearing sweep of a selected portion of the storage buffer before conveying the first or second line of signals into the storage buffer. Method.

(23) of paragraph 20, further comprising directing excess charge in the charge transfer channel into a clearing drain during the transport of the first or second line of signals to the storage buffer. , said method.

(24) detecting an image on an array of photosites each accumulating a charge in response to light transmitted by the image; and selecting I rows of the photosites for processing. and transferring charge accumulated by said row of photosites representing one line of signal to an associated series of charge transfer channels adjacent to said array during one horizontal blanking interval of said imaging device. transporting the line of signal to a storage buffer stored in the array; and detecting for all the lines of signal of the array.
Charge-coupling comprising: repeating the selecting, transferring, and exporting steps; and reading the line of signal in the storage buffer as a multi-channel output signal from the imaging device. A method of processing images for a device COD image device.

7 (25) The method of claim 24, further comprising performing a first charge clearing sweep of the charge transfer channel prior to selecting the row of photosites.

26. The method of claim 24, further comprising a second charge clearing sweep of a selected portion of the storage buffer before carrying each of the lines of signals into the storage buffer.

27. The method of claim 24, further comprising directing excess charge in the charge transfer channel into a clearing drain during the delivery of each of the lines of signals to the storage buffer.

28. The method of claim 24, wherein the accumulation buffer comprises two independently addressable frame stores.

(29) an output gate for a charge transfer circuit overlying a region of accumulated charge carriers in a semiconductor structure and separated from said charge carrier accumulation region by a planar insulator region; a first transistor having a first gate coupled to a first terminal of a capacitor, a first drain coupled to a second terminal of the capacitor, and a first source coupled to a first node; a second transistor having a second gate coupled to an output gate and a first terminal of a capacitor, a second drain coupled to a second terminal of the capacitor, and a second source coupled to a second node; , a third gate coupled to the second terminal of the capacitor;
a third transistor having a third drain coupled to a first voltage source and a third source coupled to the first node; a fourth gate coupled to a second terminal of the capacitor;
a fourth transistor having a fourth drain coupled to a voltage source and a fourth source coupled to the second node; a fifth gate coupled to the first voltage source; a fifth drain coupled to the second drain;
a fifth transistor having a fifth source connected to a voltage source; a sixth gate coupled to the voltage source; a sixth drain coupled to the second node; and a fifth transistor coupled to the first voltage source. a reset switch connected across the capacitor; and a sixth transistor coupled to detect a voltage at a second terminal of the capacitor and provide an output signal for the sensing circuit. an amplifier for use in an integrated circuit for detecting charge carriers accumulated in a region of a semiconductor structure having an output circuit coupled to transmit;

30. The amplifier circuit of claim 29, wherein the region of accumulated charge carriers is a diffusion region within the semiconductor structure.

31. The amplifier of claim 29, wherein the region of stored charge carriers is an N-type well in the semiconductor structure.

(32) The amplifier circuit of clause 29, wherein each of the amplifier circuits is fabricated as the charge transfer circuit on the same semiconductor structure.

(33) The amplifier circuit according to item 29, wherein all of the transistors are 0MO3) transistors.

(34) In paragraph 29, the output circuit is a dual
An amplifier circuit that is a stage source follower circuit.

(35) creating an N-type epitaxial semiconductor substrate; creating an N-type semiconductor layer on the substrate; creating a series of P-type semiconductor wells in the N-type layer; growing a first insulator layer over a substrate; creating an N-type semiconductor buried channel region in selected wells of the P-type semiconductor well; and forming a region adjacent to the buried channel region. creating a first series of channel stop regions in the insulator layer; a first created in a pattern connecting said buried channel region on top;
depositing a polycrystalline silicon layer; depositing a patterned insulator over the first polycrystalline silicon layer over the buried channel region to define a series of charge carrier transport channels; creating a second series of channel stop regions adjacent each of the charge carrier transport channels; and creating a second insulator layer over the patterned first polysilicon layer. step and depositing a patterned second polysilicon layer connecting the buried regions over the second insulator layer to define interconnects for peripheral circuitry to the image sensor. creating a series of practical wells in the buried channel region adjacent the interconnection of conductive paths and charge carrier transport channels; and forming a series of practical wells in the buried channel region adjacent the N-type semiconductor layer. forming a single layer metal interconnect array over the second polycrystalline silicon layer for connection of the practical well to the peripheral circuitry; A method for manufacturing an image sensor comprising:

(36) The manufacturing method according to item 35, wherein the first signal conductive path and the second signal conductive path each have different amounts of impurity added.

(37) In paragraph 35, the step of creating the second series of channel stop regions comprises covering the patterned insulator of the first polycrystalline silicon over the buried channel region. A manufacturing method that includes the step of injecting boron into the areas where it is not present.

38. The method of claim 35, wherein the step of creating the actual well comprises implanting boron.

(39) a semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type formed on the substrate; and a first semiconductor layer of the first conductivity type formed in the semiconductor layer and configured to generate charge carriers in response to incident light. an array of accumulating photosites; and a plurality of interconnected first and second portions created above the array of photosites and forming charge carrier transport and charge carrier sweep gates, respectively. a second semiconductor layer formed in a pattern; a semiconductor insulator layer formed on the second semiconductor layer formed in a pattern; and a semiconductor insulator layer formed on the insulator layer and formed in the fourth layer. - a patterned third semiconductor layer having a plurality of elongated interconnected portions coupling sites to selected peripheral circuitry; an array of elongated metal connections coupling the semiconductor layer to a charge sweep scanner circuit.

(40) In paragraph 39, the photosites include a buried channel region of a first semiconductor type created in the first semiconductor layer and a buried channel region of a second semiconductor type created in the buried channel region. A semiconductor structure having a gate region.

(41) The semiconductor structure according to item 39, wherein the first portion and the second portion of the second semiconductor layer formed in a pattern have different doping amounts of impurities.

(42) The semiconductor structure of clause 39, wherein the first semiconductor material is N-type and the second semiconductor material is P-type.

5 (43) The semiconductor structure according to item 39, wherein the second semiconductor layer and the third semiconductor layer formed in a pattern are polycrystalline silicon.

(44) A novel high-performance CCD image sensor technology has been disclosed that can be used in a versatile image sensor family with sensors having high resolution and high pixel density. The disclosed sensor architecture is based on a novel charge supersweep concept developed to solve common problems such as blooming and image smearing. Charge supersweep occurs in very narrow vertical channels placed between photosites, similar to line-to-line transfer COD devices. The difference in this case is that the charge is never accumulated in these regions for any reasonably long time (and is carried away using a novel resistive gate traveling wave sweep technique. The sweep method also allows fast charge transfer of multiple lines of data from a photosite located anywhere in the array to the storage buffer during a single horizontal blanking interval. be.

[Brief explanation of drawings]

1a to 1c are front and side schematic diagrams of a prior art CCD image sensor using segmented charge transfer channels and schematic diagrams of the charge potential distribution in the vertical charge transfer channels. , Figures 2a to 2c are top and side schematic views of a novel CCD/C3S image sensor using a continuous resistive gate charge transfer channel coupled to a novel scanner circuit and vertical resistive Schematic diagram of the charge potential distribution in the gate charge transfer channel; Figure 3 is a schematic diagram of a CCD/C3S image sensor with a similar architecture to line-to-line transfer C3S with multichannel readout; Figure 4 is a diagram of the multichannel CCD with similar architecture for frame-to-line transfer with readout
A schematic diagram of the CCD/C3S image sensor, FIG. 5, and a timing diagram of the CCD/C3S image sensor created by Akira Himi, FIG. 6, showing the pulse sequence of operations that occur during the horizontal blanking interval. FIG. 7 is a circuit diagram of a traveling wave drive circuit used in a scanner for a novel CCD/C3S image sensor, showing the CMO3 inverter stage and distributed RC circuit used to construct the circuit. ,
FIG. 8a is a cross-sectional view of a prior art stray-diffusion charge sensing node structure for use with a CCD image sensor and associated source follower amplification circuit; FIG. A cross-sectional view of the charge sensing node structure and a novel CMOS feedback amplifier circuit diagram for canceling kTC noise and parasitic capacitance, Figure 8b, is compared to Figure 8a, where stray diffusion is replaced with an N-type potential well. FIG. 9a is a tying diagram showing the operating pulse order for the detection node/amplifier circuit of FIG. 8a; FIG. 9b is a tying diagram showing the operating pulse order for the detection node/amplifier circuit of FIG. 8b; Timing diagrams showing the operating pulse sequence for the node/amplifier circuit, 8. Figures 10a to 10c illustrate the CCD/C3 of the present invention.
FIG. 11 is a cross-sectional view of selected stages of fabrication of an N-type buried channel CCD integrated on the same chip as a P-type CMO3 structure to create an S-image sensor. Image for sensor
A top view of the sensor cell, cross-sectional view along lines AA and A'A', FIG. 12, shows a charge collection well, a multiplexer, a serial register with a transfer gate;
FIG. 2 is a schematic diagram of important areas of the novel CCD/C3S image sensor of the present invention, showing the charge clearing drain. [Explanation of symbols] 2 Photo site 8 Charge transfer channel 28 Scanner

Claims (2)

[Claims] (1) a planar array of photosites disposed within a semiconductor substrate and accumulating charge carriers in proportion to incident light; and a planar array of photosites disposed within said substrate and selected rows of said photosites; a series of elongate columnar charge transfer channels coupled to receive the stored charge from the charge transfer channel; a plurality of elongate elements each disposed over an associated charge transfer channel in the charge transfer channel; , a scanner coupled to provide control pulses to a plurality of the elongated components to control movement of the stored charge carriers within the charge transfer channel; An image sensing device comprising: a device for storing charge; and an image sensing device. (2) detecting the image on an array of photosites each accumulating a charge in response to light transmitted by the image; and selecting one row of the photosites for processing. , transferring the charge accumulated by said row of photosites representing a first line of signals to an associated series of charge transfer channels; and transferring said first line of signals during a single horizontal blanking interval of the imaging device. to a storage buffer adjacent to the array; the detecting, selecting, and forwarding steps for at least a second line of signals during the single horizontal blanking interval; and reading the first line and the second line of signals from the storage buffer as multi-channel output signals from the imaging device.
Image processing method for CCD) imaging devices.