JPH03220779A - Semiconductor protecting element - Google Patents

Abstract

PURPOSE:To decrease a resistance without enlarging the area of an element region by providing a low-resistivity metal layer in a diffused layer in the inside of a P-N junction formed in a recess part in one semiconductor region constituting a diode. CONSTITUTION:An N<+>-type embedded region 2 is provided in the surface of a P-type silicon substrate 1. An N-type epitaxial layer 4 is grown on the surface including the region 2. An annular N<+>-type diffused region 3 reaching the N<+>-type embedded region 2 is provided from the surface. A silicon oxide film 7 which is provided on the entire surface and the N-type epitaxial layer 4 are sequentially etched by anisotropic dry etching. Thus a recess part is provided. Then, with the silicon oxide film 7 as a mask, P-type impurities are diffused into the inner surface of the recess part, and a P<+>-type diffused region 5 is formed. A metal layer 6 having the low resistivity is deposited by a vapor growth method, and the inside of the recess part is filled. Then, the entire surface is etched back, and the metal layer 6 is embedded only in the inside of the recess part. A hole is selectively formed on the silicon oxide film 7. An electrode 9 which is connected to a positive-electrode power supply and an electrode 8 on the metal layer 6 are formed. Thus the resistance can be decreased without widening the area of the element region.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor protection device.

[Conventional technology]

As shown in FIG. 3, a conventional semiconductor protection element includes an N+ type buried region 2 selectively provided on a P type silicon substrate;
An N-type epitaxial layer 4 provided on the surface including the N"-type buried region 2, and an annular N++ diffusion region 3 provided so as to reach the N'-type buried region 2 from the surface of the N-type epitaxial layer 4.
and an N-type epitaxial layer 4 inside the N++ diffusion region 3.
A P+ type diffusion region 5 is selectively provided on the surface of the electrode 8, which is connected to the P″ type diffusion region 5 by opening a hole in the silicon oxide [7], and an electrode 8 is connected to the N++ diffusion region 3. The electrode 9 is connected to a positive power source, and the electrode 8 is connected to an input terminal and an internal circuit element.

[Problem to be solved by the invention]

In the conventional semiconductor protection device described above, it is necessary to reduce the resistance of the diode of the protection device to increase the protection effect against electrostatic discharge damage, but the resistance of the opposite conductivity type epitaxial layer that constitutes one side of the diode is large, In order to reduce the resistance of the device, it is necessary to increase the area of the PN junction between the epitaxial layer and the diffusion region of one conductivity type provided in the epitaxial layer of opposite conductivity type, but in order to do so, the area of the element region must be increased. However, there is a problem in that it hinders high integration.

An object of the present invention is to provide a semiconductor protection element with low resistance without increasing the area of the element region.

[Means to solve the problem]

A first semiconductor protection element of the present invention includes a buried region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, an epitaxial layer of a reverse conductivity type provided on a surface including the buried region, and an epitaxial layer of the opposite conductivity type provided on a surface including the buried region. an annular reverse conductivity type diffusion region provided on the surface of the epitaxial layer and reaching the buried region; a recess provided on the surface of the epitaxial layer within the reverse conductivity type diffusion region; and a one conductivity type diffusion region provided on the inner surface of the recess. , and a low resistivity metal layer filled in the recess.

A second semiconductor protection element of the present invention includes a one conductivity type buried region provided on a one conductivity type semiconductor substrate, an opposite conductivity type epitaxial layer provided on a surface including the one conductivity type buried region, and the a diffusion region of one conductivity type provided on the surface of the epitaxial layer and reaching the buried region; a recess provided on the surface of the one conductivity type diffusion region; and a diffusion region of the opposite conductivity type provided on the inner surface of the recess; and a low resistivity metal layer provided to fill the inside of the recess.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
An N+ type buried region 2 is selectively provided on the surface of the substrate, and an N type epitaxial layer 4 is grown on the surface including the N+ type buried region 2. Next, after providing an annular N++ diffusion region 3 extending from the surface of the N-type epitaxial layer 4 to the N+-type buried region 2,
The silicon oxide film 7 and the N-type epitaxial layer 4 provided on the entire surface are sequentially selectively etched by anisotropic dry etching to form recesses. Next, using the silicon oxide film 7 as a mask, a P type impurity is diffused into the inner surface of the recess to form a P+ type diffusion region 5. Next, a low resistivity metal layer 6 such as aluminum is deposited by vapor phase growth to fill the recess.

Next, as shown in FIG. 1(b), the entire surface is etched back by anisotropic dry etching, and the metal layer 6 is buried only in the recesses. Next, holes are selectively opened in the silicon oxide film 7 on the N+ type nuclear diffusion region 3, and an electrode 9 connected to the positive electrode power supply is formed.
An electrode 8 is formed on the metal layer 6' and the metal layer 6'.

FIG. 2 is a sectional view of a second embodiment of the invention.

As shown in FIG. 2, P+
A type buried region 10 is provided, and an N type epitaxial layer 4 is provided on the surface including the P type buried region]0. Next, a P type diffusion region 11 and a P + type diffusion region 12 reaching the P + type buried region 10 are provided in the N type epitaxial layer 4 . Next, the silicon oxide film 7 and the P-type diffusion region 11 provided on the entire surface are selectively and sequentially anisotropically etched to form a recess, and using the silicon oxide film 7 as a mask, an N-type impurity is diffused into the inner surface of the recess. Then, an N+ type diffusion region ↓3 is formed. Next, in the same manner as in the first embodiment, a low resistivity metal layer 6 is buried in the recess, and then a hole is formed in the silicon oxide film 7 on the P+ type region 12, and a G
An electrode 8 is formed on the metal layer 6 and the electrode 14 connected to the ND power source.

In this embodiment, a protective PN diode is connected to an external terminal,
This is an example in which connection is made between the GND electrode and the GND electrode.

〔Effect of the invention〕

As explained above, the present invention provides a recess in one of the semiconductor regions constituting the tie-out of the protection element, and provides a low resistivity metal layer in the diffusion layer inside the PN junction formed in the recess. In the case of the first embodiment, P+ type diffusion region 5
The thickness of the N-type epitaxial layer 4 immediately below is thinned, making it possible to reduce the resistance without increasing the area of the element region, and further reducing the resistance by providing a low resistivity metal layer in the recess. effective.

In the case of the second embodiment, the resistance can be reduced by similarly reducing the thickness of the P-type diffusion region 1 immediately below the N-type diffusion region 13.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are cross-sectional views of a semiconductor depth shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention, and FIG. The cross-sectional view, FIG. 3, is a cross-sectional view of a conventional semiconductor protection element. ]...P-type silicon substrate, 2...N+ type buried region 3
...N++ diffusion region, 4...N type epitaxial layer, 5...P+ type diffusion region, 6...metal layer, 7...
Silicon oxide film, 8, 9...electrode, 1-0...P+ type buried region, 11...P type diffusion region, ]2...P+ type diffusion region, 13...N++ diffusion region, 14...electrode.

Claims (1)

[Claims] 1. A buried region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on a surface including the buried region, and an epitaxial layer of an opposite conductivity type provided on a surface of the epitaxial layer. Provided,
an annular reverse conductivity type diffusion region reaching the buried region; a recess provided on the surface of the epitaxial layer within the reverse conductivity type diffusion region; a one conductivity type diffusion region provided on the inner surface of the recess; 1. A semiconductor protection element comprising a low resistivity metal layer provided by filling a recess. 2. A buried region of one conductivity type provided on a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on a surface including the buried region of one conductivity type, and an epitaxial layer provided on a surface of the epitaxial layer and said buried region. a diffusion region of one conductivity type reaching the containing region, a recess provided on the surface of the one conductivity type diffusion region, a diffusion region of the opposite conductivity type provided on the inner surface of the recess, and a diffusion region filled in the recess. A semiconductor protection element characterized by having a metal layer having a low specific resistance.