JPH03220818A - logic circuit - Google Patents

Abstract

PURPOSE:To form a high speed circuit with less dispersion in the delay time by applying a prescribed voltage to a pre-stage of load element so as to reduce the dispersion in the current flowing to pre-stage logic and a current flowing to a load drive section. CONSTITUTION:Logic circuits 100, 200 are operated by a positive power supply 151 and a negative power supply 153 and a prescribed level Vg is applied to a gate of a logic load element (FET 603). The FET 603 is made up of a normally-on FET. A current flowing to the FET 603 is a value proportional to (Ygs-Vth)<2>, where Vgs is a gate-source voltage and Vth is a threshold voltage. Since the Vth is negative in the normally-on FET, the value of Vgs-Vth is increased, Thus, a dispersion Vth of the Vth takes place, the effect is relatively decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and more particularly to an ultra-high speed and low power consumption GaAs logic circuit.

[Conventional technology]

As a prior art, for example, Japanese Patent Application Publication No. 2002-2912
There is a high speed logic circuit shown in Figure 3.

FIG. 14 is an example of the high-speed circuit shown in the above publication. This circuit consists of a high potential power supply 151 (VDD) and a low potential power supply 151 (VDD).
! (for example 0V) has 153 and 101.102.10
It is composed of normally-off type FETs consisting of 4.105, 106.191°603.

The operation of this logic circuit is such that when a H1gh level (for example, 0.6V) is applied to either the input terminal 155 or 156, the output terminal 121 is applied to a Low level (for example,
This is NOR logic in which OV) appears. Logic operation is mainly determined by FET10I, upper 02, and load element 6035. For example, when the input terminal 155 is at a high level, current flows through FET10I, and as a result, the gate voltage of FET105 whose input is the potential of 155 increases, the potential of the output node 121 becomes Lo, which is close to the ground potential.
It becomes W level. On the other hand, when low level is applied to all input terminals, the current from the load element is FE
The potential of the flow connection 120 flows through T191.
The H i g h level is clamped by JLr (approximately 0.6
V) appears.

FETs 104, 105, and 106 are provided to increase the load driving ability of the circuit, and FETs 104 and 105 quickly discharge the load capacitance connected to the output note 121.
106 functions to charge at high speed.

Further, the FET 191 has a high potential at the input terminal 155.
When falling from gh level to Low level, the gate voltage changes from Low level to High level, so the off state changes to the on state.

As the potential of the terminal 121 rises, the FET 191 turns on and shifts to clamp operation.

On the other hand, the potential of the input terminal 155 changes from Low level to Hi.
When rising to the gh level, the gate voltage of the FET 191 moves in the opposite direction from the High level to the Low level, and as the potential of the terminal 121 decreases, it shifts to cut-off operation.

[Problem that the invention seeks to solve]

Problems with the prior art shown in FIG. 14 include the following.

First of all, the gate voltage of the FET 603 is supplied from the terminal 151 through the resistance element, and the current ILL flowing through the load element 603 is easily affected by voltage fluctuations at the terminal 151.

Second, the potential of the terminal 151 is normally set to a value of about 2V, and the gate of FET6C)3 is formed by a Schottky junction, so the voltage between the gate and source is 0. When the voltage exceeds .6V, current begins to flow from the gate to the source. This current flows from terminal 151 to resistive element 604, FET10I, 102 and FET1
Flows through 91, /I! This will lead to an increase in the cost of electricity.

Furthermore, the resistance element 604 also becomes a factor that inhibits the transient response of the gate voltage that changes following the change in the source voltage of the FET 603, and there is still room for improvement in terms of high speed.

Thirdly, due to variations in the threshold voltage of the FET 603, the load current ILL supplied from the FET 603 changes, and furthermore, the current IL flowing through the FET 106 changes.
2 also causes variations in delay time and load driving ability, resulting in a lack of stable operation. Fourth, although the gate of FETI 91 is configured to be directly connected to output node 121, it is not possible to adjust the time for FETI 91 to transition from an off state to an on state, and it is difficult to adjust the time for the FETI 91 to transition from an off state to an on state, It is not possible to take the optimal value for

Figure 15 shows how the current ILL flowing through the front-stage logic in Figure 14 and the current IL2 flowing through the load drive section vary due to the variation in threshold voltage of the FET, which is the third problem above. It is. As can be seen from this figure, the Vth variation of normally-off type FET is 0.22Vf.
0. With respect to IV4m, the average currents of ILL and IL2 each vary by about ±40%. In addition, as shown in FIG. 13, in response to the variations in ILL and IL2, the delay time of the circuit also increases by about +60% and - as shown in FIG.
There is a variation of 20 to 30%, and stable operation and high-speed operation cannot be expected. In addition, in FIG. 16, CL
=O means that when the load capacitance such as wiring capacitance is 0, CL=0.
25 pF means that this value is 0.25 pF.

[Means for solving problems]

In the present invention, the load element FET603.

This is an attempt to solve the above problem by applying a predetermined potential Vg and reducing variations in ILL and IL2.

[Effect]

The predetermined potential Vg applied to the gate of the load element (FET 603) of the logic section has the function of stabilizing the current ILL of the FET 603 and the current IL2 flowing through the FET 106 against variations in element characteristics. in particular,
IL
This is an attempt to stabilize L and IL2 and realize a high-speed circuit with less variation in delay time.

〔Example〕

Embodiments of the present invention will be described below using the following drawings. 1st
The circuit in the figure is positive side 1! J151 and a negative side power supply 153, and a predetermined potential Vg is applied to the gate of the logic section load element (FET603). FET603 is
It is composed of normally-on type FET, but FET60
The current flowing through 3 increases the voltage between the gate and source by Vgs,
Letting the threshold voltage be vth, (V g s - V t
h)", and since the value of Vth is negative in a normally-on type FET, V g s - V
This is because the value of th can be increased, and even if variation Δvth in vth occurs, its influence can be relatively small.

FIG. 2 is an example of a circuit for generating the above-mentioned Vg. 2701, 2702, 2703, and 2704 are normally-on type Fs designed to have the same threshold voltage vth.
In ET, 2706° and 2707 are Schottky diodes designed with equal junction area. Here, resistance 2
The current Ird flowing through 705 is a normally on type FET.
Since it does not flow into the gate of 2702, it all flows into Schottky diodes 2706 and 2707. Connection 27
08 and the negative side of the source terminal 153, this current Ird is connected to these Schottky diodes 270.
6. Assuming the respective forward drop voltages Vf (2706) and Vf (2707) that occur when flowing to 2707,
Vf (2706) becomes 10 Vf (2707). At this time.

Vg is the gate-source voltage of normally-on type FET2701゜2702, Vgs (FET2701), V
gs (FET2702), the following equation is obtained.

Vg=Vgs (FET2701) 10Vgs (FE
T2702)+Vf (2706)+Vf (270?
) 10V (153) ---(2). In addition, V
(153) is the potential of the negative power supply terminal 153. By the way, the FET has a voltage Vgs between the gate and source of the FET.
It has a voltage-current characteristic that is a function of the square of the difference between the threshold voltage and the threshold voltage.

The current flowing through the FET is proportional to the gate width. here,
The current Ifl of FET2701 is applied to FET2703.
Since the current If2 of FET2702 flows into ET2704, FET2701゜2702.2703.270
4 gate width is W2701. W2702. W2703-
When W2704 is assumed, the following relationship holds true.

Ifl”-W2701・(Vgs (FET2701)
Vth)"W2703・(-Vth)"
・・・・・・(3) If2ccW27
02 ・(Vgs (FET2702)-Vth) 2
ceW2704- (-Vth) 2
-=・(4) (3), rearranging equations (4), Vgs(FET2701)=(1-W2703 W2
01) Vth... (5) Vgs (FET2702) = (1-W2 0 W
/ )Vth...(6) Here, by substituting equations (5) and (6) into equation (2), Vg becomes as follows.

Vg=(1-W2 03 W2 1) ・Vth+
(1-W2704/W2702) ・Vth+vf (
2706)+vf (27o7)+v(153)---
---(7) In other words, according to this circuit, FET270
1 and FET2703, further FET2702 and FET2
By changing the gate width ratio of 704, a potential Vg having arbitrary threshold voltage vth dependence can be generated.

Now, the current flowing through FET 603 in Fig. 1 is defined as IL(
F E T 603), the potential of the connection vA120 v(12
0).

ILI(FET603)=K(Vg-V(120)-V
th)” −...(8), where K is FET
603 is the mutual conductance coefficient. Now, W 2701 in equation (7).

W2702, W2703, W2704 1-W27
03/W2701=0.51-
' = 0.5, then in equation (8), ILL (FET603) = K (Vf (2706) +
Vf(2707) 10V(153)-V(120))”
・-=(9) becomes an expression unrelated to Vth,
ILLCFET603) is a normally-on type FET.
It is possible to avoid being affected by h variations.

In addition, in actual operation, V(120
) is affected by the vth variations of the FETs 191, 101, and 102, so the influence of the Vth variations on the IL (FET 603) cannot be completely eliminated, but the stability is significantly improved compared to the conventional method.

Therefore, by applying Vg generated in this circuit to the logic circuit shown in FIG. 1, the influence of manufacturing variations in the threshold voltage vth of the normally-on FET can be reduced. Note that in this configuration example, normally-on type FE
Connect the Vg terminal of the source floor circuit consisting of T1
Although two circuits 11 are cascade-connected to 12708, the same effect as in this example can be obtained even if a plurality of circuits are cascade-connected. Therefore, it is possible to secure operating margin and stabilize circuit characteristics such as delay time. Further, in FIG. 2, a resistive element may be used in place of the diodes 2706 and 2707. Also, due to fluctuations in the positive power supply voltage, V
The potential of g has little fluctuation, and the current of the load FET 603 of the logic circuit shown in FIG. 1 also has little change, making stable operation possible.

FIG. 3 shows another configuration of the Vg generation circuit of the embodiment shown in FIG. 2, and in this case as well, the same effects as explained in FIG. 2 can be obtained.

FIG. 4 shows the variations in the average currents of ILL and IL2 with respect to the variations in vth when the circuits in FIGS. 1 and 3 are combined and Vg is applied.

In Figure 4, the vth variation of EFET is 0.2
2V+0. IV, DFET (7) variation.

-0.8V+0. It is called IV. As can be seen from this figure, ILL
is +20% and -30%, and IL2 is +10 to 20%, which is a significant improvement compared to the conventional case.

FIG. 5 shows how the delay time variation changes in response to the above-mentioned ILL and IL2 variation. With respect to the design center, CL=O, CL=0.25 p
In both cases, it can be seen that an improvement of as much as 20% is possible on the slow side compared to the conventional case of -15% and +40%.

FIG. 6 shows the specific difference in delay time between the conventional circuit and the circuit of the present invention. When vth becomes shallower, 1.
It is possible to increase the speed by 5 to 1.8 times.

Further, the power consumption at this time is 1/1.8 of that of the conventional circuit, which is a significant improvement in terms of lower power consumption.

FIG. 7 is an attempt to explain the principle by which variations in ILL and IL2 are reduced by the circuit of the present invention from the vth dependence of the potential of the connection wA120.

In the conventional example, the potential V (120) of the connection 120 is vth
Because it is constant against variations.

The gate-source voltage vgs of FET603.106 is also constant. The current Ids flowing through the FET is (Vgs −
Vth)'' is proportional to 2, so Ids is affected by variations in Vth(7) and varies greatly. On the other hand, in the present invention, as vth becomes shallower, Vg increases.

Along with this, the potential of V(120) also increases. Due to this operation, the Vgs of FET603.106 also increases,
(Vgs - Vth)" to be constant,
ILL and IL2 are stabilized. Conversely, when Vth becomes deeper, Vg decreases, and in this case as well, ILL, IL
2 is the direction of stabilization.

In the embodiment shown in FIG. 1, the FET 603 is a DFE.
Although T is used, an EFET may also be used. In this case, a predetermined Vg can be generated by replacing the DFET in FIGS. 2 and 3 with an EFET.

FIG. 8 shows a delay element 2201 between the gate terminal 2202 of the FET 191 and the output terminal 121 of the embodiment shown in FIG.
Fig. 2 shows an embodiment of the pond of the present invention in which the pond is inserted. This embodiment also operates in the same way as the embodiment shown in FIG. 1 in terms of direct current. On the other hand, in the case of AC, the potential of the output terminal 121 is
The signal is transmitted to the gate terminal 2202 of the device 191 with a delay of one hour T (T is the delay time of the delay element 2201). Now, considering the time when the potential of the output terminal 121 rises from a low level to a high level, the FET 191
Since the potential of the delay element 2201 is initially approximately equal to the potential of the negative side chamber source, the off state is maintained during the delay time T of the delay element 2201. therefore.

During this time, the current I (FET6
03) are all used to charge the gate capacitance of the FET 106, and the potential of the output terminal 121 rises rapidly. On the other hand, the potential of the output terminal 121 is High
When falling from the level to the Low level, even if the potential of the output terminal 121 becomes the Low level, the FE remains for a time T.
Since T191 continues to be on, this FET
Due to the current 191, the potential of the wire 20 falls rapidly. As a result, FET106 turns off quickly and FET1
04, the potential of the output terminal 121 also falls quickly.6 Therefore, according to this embodiment, high-speed operation is possible even when the load capacitance is particularly large.

FIG. 9(a) shows the delay element 2201 in FIG.
01 and a capacitor 2302 according to an embodiment of the present invention. In the delay element with this configuration, the output terminal 121
The potential is transmitted to the terminal 2202 with a delay of a time proportional to the time constant of the resistor 2301 and the capacitor 2302.

Furthermore, FIG. 9(b) shows the resistance element 23 of FIG. 9(a).
This is an embodiment of the present invention in which a normally-on type FET 2303 is used instead of the FET 01.

Even in this configuration, the delay time is the same as in Fig. 9(a).
The value is proportional to the impedance of the capacitor 2303 and the time constant of the capacitor 2302.

FIG. 10 has almost the same configuration as the embodiment shown in FIG.

A high impedance resistance element 2401 is inserted between the gate of the load element 603 in the drawing and Vg, and a capacitor ff124 is inserted.
This figure shows an example in which the transistor 02 is provided between the gate and the source. Also in this embodiment, since no current flows through the gate of the FET 603, it operates in the same manner as in FIG. 1 in terms of direct current, and the effects of the present invention can be obtained. On the other hand, in terms of alternating current, it operates as follows. In this embodiment, as in the embodiment shown in FIG. 1, the potential of the input terminal 155 changes from Low level to High level.
When it rises to h level, FETl0I turns on and connection 1
The potential at 20 decreases. At this time, in the embodiment shown in FIG.
Since the gate of FET603 is fixed at Vg,
As the potential of the connection 120 decreases, the gate-source voltage of the FET 603 increases, the current of this FET 603 increases, and this prevents the potential of the connection 11Al2O from falling.

Also, the potential of the input terminal 155 changes from High level to Low level.
When it falls to w level, FET10I turns off and F E
T 603 Niyotte, M @ 120 (7) '1st place stands up. At this time, in the embodiment shown in FIG. 1, as the potential of the connection 120 increases, the layer pressure between the gate and source of the FET 603 decreases, so the current of the FET 603 decreases and the rise of the potential of the connection 1!120 becomes slower. On the other hand, in the embodiment shown in FIG.
Since the gate and source of 3 are connected by capacitor 2402, the result is ! The change in the potential of the wire 120 is transmitted to the gate of the FET 603, and the FET 603 operates in such a direction that the potential difference between the wire 120 and the wire 2403 does not change. Therefore, in this example,
Even if 1l120 changes, the gate-source voltage of FET 603 does not change, and the current of FET 603 remains constant, so it operates faster than the embodiment shown in FIG.

FIG. 11(a) shows the resistance element 2401 in FIG.
501 shows an embodiment of the present invention configured with 501.

FIG. 11(b) shows an embodiment of the present invention in which the resistive element 2401 of FIG. 6 is constructed of a normally-on type FET 2502 whose gate and source are connected. moreover,
FIG. 11(C) shows the resistance element 2401 of FIG. 6 as a normally-on type FET with a fixed pressure applied to the gate.
2503 shows an embodiment of the present invention configured with 2503.

FIG. 12 shows an embodiment of the present invention in which a load element 2001 is provided between the train and source of the FET 106 of the embodiment of FIG. In this embodiment, the output terminal 121
When the potential of FET191.20 is High level,
The currents of both FET 106 and load element 2001 flow into the parallel gate-source Schottky diode of 1.204. At this time, the High level of the output terminal 12↓ is the sum of the currents Ih of the FET 106 and the load element 2001.
(=Iout+Ir) and FET191°201.20
It is determined by the voltage-current characteristics of the parallel gate-source Schottky diode of 4.

Therefore, by setting M and tEIr of the load element 2001 sufficiently large, the current Iout of the FET 106 can be reduced without reducing the high level of the output terminal. Since the current Iout of the FET 106 is determined by the potential difference between the connection 120 and the output terminal 121, it can be made extremely small by lowering the potential of the connection 120.

On the other hand, in terms of AC, the output terminal 1 is similar to the embodiment shown in FIG.
When the potential of the output terminal 121 rises from a low level to a high level, the FET l 91 is cut off until the potential of the output terminal 121 becomes high level.
The potential of connection 120 rises to near the positive power supply voltage. Therefore, the FET 106 is always off in terms of direct current, operates only when the potential at the output terminal rises, and charges the load capacitance at high speed. In other words, according to this embodiment, the direct current Iout of the FET 106 can be made extremely small without increasing the rise time of the output.

FIG. 13(a) shows the load element 200 of the embodiment shown in FIG.
The circuit is constructed with a normally-on type FET2101. Further, FIG. 13(b) shows a configuration in which the load element 2001 of the embodiment shown in FIG. 12 is configured with a resistor 2102.

Among the embodiments described above, at least one of the embodiments shown in FIGS. 8, 10, and 12 may be used in combination.

[Brief explanation of drawings]

The construction drawings to FIG. 3 and FIGS. 8 to 13 are. 1A and 1B are circuit diagrams each showing an embodiment of the present invention. FIGS. 4 to 7 are circuit diagrams for explaining the present invention in detail. FIGS. 14 to 16 are circuit diagrams for explaining the conventional example, respectively. [Explanation of symbols] 100.200...Logic circuit, 101,102゜10
4.105,106,191,201゜204.703
,709,711,713゜714.2701,270
2,2703゜2704.2301,2502,250
3゜2303.2101...FET, 103,240
1゜2501.2502.2503・i cargo fi child, 70
1.704,706,707,708°710.210
2,2001,2501゜2401.2301.270
5...Resistance, 715°716.2706.2707.
...Diode element, 2201...Delay circuit. 2302゜2302...Content 1. 121...Output terminal, 154゜155...Input terminal, Vg...Load element 200 pieces

Claims (1)

[Claims] 1. Provided between a first terminal connected to a first power source and a second terminal connected to a second power source, the first load element and at least one field effect The first transistor
a group of transistors, the input signal is received at the gate of the field effect transistor constituting the first transistor group, and a predetermined potential reflecting variations in device characteristics is applied to the gate of the first load element. a logic section that obtains a desired logic signal according to an input signal from a connection point between the first load element and the first transistor group; and a drain connected to a third terminal connected to a third power supply. a first field effect transistor connected to the gate, receiving the output of the logic section at its gate and obtaining an output signal from its source; and a fourth field effect transistor connected to the source of the first field effect transistor and a fourth power supply.
and a pull-down means provided between the second terminal and the gate of the first field effect transistor, the pull-down means being provided between the second terminal and the gate of the first field effect transistor, and discharging the load capacitance when the output signal falls; A logic circuit comprising: clamping means controlled by an output signal. 2. The clamping means is configured by a second field effect transistor having a gate connected to the source of the first field effect transistor, a drain connected to the gate of the first field effect transistor, and a source connected to a second terminal. 2. The logic circuit according to claim 1, wherein the logic circuit is configured as follows. 3. The logic circuit according to claim 2, wherein the threshold value of the second field effect transistor is substantially equal to the threshold value of the first field effect transistor. 4. The logic circuit according to claim 1, further comprising a second load element connected between the drain and source of the first field effect transistor. 5. The logic circuit according to claim 4, wherein the second load element is constituted by a resistance element. 6. The logic circuit according to claim 4, wherein the first load element is constituted by a normally-on type FET whose gate and source are connected. 7. The logic circuit according to claim 1, wherein a delay circuit is inserted between the gate of the second field effect transistor and the source of the first field effect transistor. . 8. The logic circuit according to claim 7, wherein the delay circuit includes a resistive element and a capacitive element. 9. The logic circuit according to claim 8, wherein the delay circuit is composed of a field effect transistor and a capacitor whose gate and source or gate and drain are connected. 10. Any one of claims 1 to 9, wherein a capacitive element is provided between the gate and source of the first load element, and a resistive element is inserted between the gate and a predetermined potential. Logic circuit described in . 11. Claim 10, characterized in that the resistance element inserted between the gate of the first load element and a predetermined potential is constituted by a field effect transistor in which the gate and source or the gate and drain are connected. The logic circuit described. 12. The resistance element inserted between the gate of the first load element and a predetermined potential is constituted by a field effect transistor whose gate is connected to a constant potential. logic circuit. 13. The pull-down means comprises at least one field effect transistor to which the input signal of each of the first transistor group is applied to the gate, and whose sources are connected to each other and connected to the fourth terminal, 13. The logic circuit according to claim 1, comprising a second group of transistors whose respective drains are connected to each other and connected to the source of the first field effect transistor. 14. The logic circuit according to claim 1, wherein the first load element is composed of a normally-on field effect transistor. 15. A first transistor group consisting of at least one field transistor, to which each input signal is applied to the gate of each transistor, which is connected to a negative power supply, and whose drains are connected to each other; a first load element connected between the common drain of the first transistor group and the positive power supply and having a predetermined potential applied to its gate that reflects variations in element characteristics; Input signals are applied to the gates of a first field effect transistor whose gates are connected to a connection point between the common drain and the first load element, and corresponding to respective inputs of the first transistor group. It consists of at least one field effect transistor, the sources of each transistor are connected to each other and connected to the negative side power supply, and the drains of each transistor are connected to each other and connected to the source of the first field effect transistor. a second group of transistors,
The clamping means is provided between the negative power supply and the gate of the first field effect transistor, and is controlled by an output signal obtained from the source of the first field effect transistor. Claims 2 to 1
2. The logic circuit according to any one of 2 and 14.