JPH03220886A - High definition television display device - Google Patents

Abstract

PURPOSE:To display a noninterlace signal of a standard television receiver and a high definition television signal with a same deflection circuit by providing a changeover circuit receiving an output of a frame synchronization circuit and an output of a 1 frame memory and selecting an output signal with an output signal of a frame signal output control circuit and a scanning conversion circuit converting the digital standard television interlace signal being an output of the changeover circuit into a noninterlace signal. CONSTITUTION:A frame synchronization circuit 4 receives an input digital standard television interlace signal a2 and outputs a26, a27 of a synchronization phase difference detection circuit 3 and outputs a standard television signal a3 in matching with the phase of the high definition television signal. An output signal a5 of the changeover circuit 6 is inputted to a scanning conversion circuit 7 and outputted as a standard television noninterlace signal a6. An output signal a6 of the scanning conversion circuit 7 is converted into an analog signal by a D/A converter 8 and a signal a8 is outputted. The output signal a8 of the D/A converter 8 is inputted to a changeover circuit 9 together with the analog high definition television signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides the same polarization for standard television non-interlaced signals and high definition television (11252:1) signals. The present invention relates to a high-definition television display device that enables display using a circuit.

2. Description of the Related Art With the MUSE television system proposed and developed by the Japan Broadcasting Corporation in recent years, the emergence of a high-definition television system as a next-generation television is taking shape. Among these, there have been proposals for displaying conventional standard television signals on high-definition television displays. As shown in Japanese Patent Application Laid-Open No. 62-263783, such a television display device uses a high-definition television signal, a standard television signal, and an external signal as input signals, and converts the standard television signal into When outputting to a quality television display device, an external signal may be output to a portion where the signal is missing due to the aspect ratio.

Problems to be Solved by the Invention However, with the above-mentioned configuration, there is a difference between the vertical scanning frequency of 60 Hz for the high-definition television signal currently proposed by Japan and the vertical scanning frequency of 59.94 Hz for the standard television signal. Since standard television signals cannot be directly output to high-definition television display devices, it is necessary to change or switch part of the deflection system depending on the type of display signal.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a high-definition television display device that can display a high-definition television 3/ signal and a standard television non-increment signal using the same deflection circuit. .

Means for Solving the Problems To achieve this object, the high-definition television display device of the present invention detects the phase difference between the synchronization signals of the high-definition television signal and the standard television interlaced signal to achieve synchronization. A synchronization phase difference detection circuit outputs a control signal for synchronization, a frame synchronization circuit synchronizes a high-definition television signal and a standard television interlaced signal using a control signal from a synchronization matching circuit, and a frame synchronization circuit synchronizes a high-definition television signal with a standard television interlaced signal. A frame motion detection circuit that changes at least two types of thresholds for determining whether a standard television signal is a still image over a certain period of time and outputs a signal that matches the threshold; A frame synchronization control signal output circuit that outputs a control signal that outputs a 1-frame signal only once twice, an l-frame memory that outputs the same 1-frame signal, and a 1-frame signal that is the same as the normal signal as input. It is equipped with a switching circuit that switches output signals according to a frame synchronization control signal, and a scan conversion circuit that converts a standard television interlaced signal into a non-interlaced signal.

Effect This configuration allows you to change the deflection system of a standard television non-interlaced signal to a high-definition television output device.
Display can be performed at the vertical scanning frequency of 60 Hz without switching.

Embodiment Hereinafter, a high-definition television display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a high-definition television display device in one embodiment of the present invention. In FIG. 1, 1 is a motion detection circuit, 2 is a frame signal output control circuit, 3 is a synchronization phase difference detection circuit, 4 is a frame synchronization circuit, 5 is an l frame memory, 6 is a switching circuit, 7 is a scan conversion circuit, 8 is D/A
A converter, 9 a switching circuit, and 10 a display element.

The operation of the high-definition television display device configured as described above will be described below.

The synchronization phase difference detection circuit 3 receives a high-definition television horizontal synchronization signal a21, a vertical synchronization signal a21, which is sent independently from the video signal or obtained by being separated from the television signal, and a standard television signal. horizontal synchronization signal a23,
It inputs the vertical synchronizing signal a24 and outputs a signal a27 representing the horizontal phase difference and a signal a26 representing the vertical phase difference. The frame synchronization circuit 14 receives the input digital standard television interlaced signal a2 and the output a26 . A27 is input, and a standard television signal a3 whose phase is matched with the high-definition television signal is output. The one frame memory 5 receives the output a3 of the frame synchronization circuit 4 and outputs a signal a4 delayed by one frame. The output signal a3 of the frame synchronization circuit 4 and the output signal a4 of the one frame memory 5 are input to a switching circuit 6, which outputs the signal a5 selected by the output a31 of the frame signal output control circuit 2.

Digital standard television (interlaced) as above
The signal a2 is input to the frame motion detection circuit 1, and as shown in FIGS. 2 and 3, the total number of video pixels in one frame is a certain number (TI, T2°T3), If it is less than THI, TI2゜TI3), it will be a still image, or a certain number (THI).

TI2. TI3) In the above cases, it is determined that it is a moving image and a motion detection signal a30 is output. In this embodiment, "0" is output when the image is determined to be a moving image, and "1" is output when the image is determined to be a still image.

The frame signal output control circuit 2 is the output a3 of the motion detection circuit.
0 is input, and if a still image frame exists during a certain period T, the output signal a5 of the switching circuit 6, which normally outputs the output signal a3 of the frame synchronization circuit 4, will be output for one frame only once for one frame. A control signal a32 is outputted so as to become a memory output a4.

The output signal a5 of the switching circuit 6 is input to the scan conversion circuit 7 and output as a standard television non-interlaced signal a7. The output signal a7 of the scan conversion circuit 7 is a D/A
The converter 10 converts it into an analog signal and outputs it as an output a8.

The output signal a8 of the D/A converter 10 is input to the switching circuit 9 together with the analog high-definition television signal a1. The output a9 of the switching circuit 9 is selected by the external control signal a33 and input to and displayed on the high quality television display element 10.

Effects of the Invention According to the present invention, high-definition television signals and standard television non-interlaced signals with different vertical scanning frequencies can be displayed without changing the deflection circuit.
Its practical effects are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a high-definition television display device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram illustrating the output signal of the motion detection circuit, and FIG. 3 is a diagram showing the characteristics of the frame signal output control circuit. FIG. 3 is a waveform diagram showing the relationship between an output signal and a motion detection circuit output signal. DESCRIPTION OF SYMBOLS 1...Motion detection circuit, 2...Frame signal output control circuit, 3...Synchronization phase difference detection circuit, 4...Frame synchronization circuit, 5. ...1
Frame memory, 6, 9...Switching circuit, 7...
...Scan conversion circuit, 8...D/A converter.

Claims (1)

[Claims] a synchronization phase difference detection circuit that detects a phase difference between a horizontal synchronization signal and a vertical synchronization signal of an input standard television signal and a horizontal synchronization signal and a vertical synchronization signal of an input high-definition television signal;
A frame synchronization circuit that is controlled by the output signal of the synchronization phase difference detection circuit and controls the frame synchronization of the input television signal so that the frames of the selectively inputted high-definition television signal and standard television signal are aligned. and a frame memory which takes as input the digitized standard television interlaced signal which is the output of this frame synchronization circuit and delays it by one frame, and detects the number of moving pixels relative to the total number of pixels in one frame of the input television signal. and has at least two types of motion pixel count thresholds for determining whether the frame is a still image or a video,
a frame motion detection circuit that changes a motion pixel count threshold for a certain period of time; and a frame signal that outputs a control signal for outputting the same frame signal of a standard television signal twice once during the certain period of time. an output control circuit, a switching circuit that receives the frame synchronization circuit output and one frame memory output as input and selects an output signal according to the frame signal output control circuit output signal; and a switching circuit that selects an output signal according to the frame signal output control circuit output signal; A high-definition television display device comprising: a scan conversion circuit for converting into signals.