JPH0322090B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The present invention is a signal processing circuit that obtains a signal delayed by a predetermined time with respect to an input signal, and is configured using an ultrasonic delay line or a shift register, so that it can be used on a large scale. In order to solve the problem of conventional circuits that become obsolete, we have developed a constant value generation circuit that generates a constant value from a delay amount and a timing signal whose timing corresponds to the cycle of the input signal when it has this delay amount; By providing an adder/subtracter circuit that performs addition/subtraction between a signal and a fixed value, and a circuit that corrects the output amplitude of the adder/subtracter circuit at a fixed cycle to obtain a delayed signal with respect to the input signal, it is no longer possible to use the large-scale configuration of conventional circuits. This is to obtain a delayed signal without needing it.

[Industrial application field]

The present invention relates to a signal processing circuit, and particularly to a signal processing circuit that obtains a signal delayed by a predetermined time with respect to an input signal, and is applied to a portion of circuits such as digital filters and analog filters.

[Conventional technology]

As conventional circuits for obtaining delayed signals, there are known analog signal processing circuits using, for example, ultrasonic delay lines, and digital signal processing circuits using shift registers using flip-flops.

[Problem that the invention seeks to solve]

Conventional circuits using the above-mentioned ultrasonic delay line have a problem that they are large in size and cannot be configured compactly.

On the other hand, in the conventional circuit using _the shift register _described above, as shown in _FIG . Then, the input signal Vi
For example, in order to obtain the signal V ₀₅ with the delay amount (t ₅ - _{t 0} ), it is necessary to use five stages of flip-flops, which increases the circuit scale and has the problem that it cannot be configured compactly. Ta.

[Means for solving problems]

FIG. 1 shows a basic block diagram of the circuit according to the invention.
In the figure, 4 is a constant value generation circuit that generates a constant value αi from a delay amount di and a timing signal SC() whose timing corresponds to the cycle of the input signal when it has this delay amount di, and 2 is an input Signal Vi(t)
6 is an addition/subtraction circuit 2 that subtracts a constant value αi from the period input signal Vi(t) according to the timing of the timing signal and adds the constant value αi to the input signal Vi(t) every 1/2 cycle of the timing signal. the output of the input signal
This is an amplitude correction circuit that performs period amplitude correction according to the delay amount di every 1/2 cycle of Vi(t) to obtain an output signal V ₀ (t) having an amplitude corresponding to the amplitude of the input signal Vi(t).

[Effect]

By adding or subtracting a constant value αi to the input signal Vi(t) every 1/2 cycle and correcting the amplitude every 1/2 cycle, a signal V ₀ delayed by a predetermined delay amount di is obtained.
(t) is obtained.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the circuit of the present invention. Hereinafter, the signals to be handled will be, for example, digital signals, but since it is difficult to understand the waveforms of digital signals as they are, analog signal waveforms will be used for explanation. In the same figure, for example, triangular wave input signals Q0 to Q7 (solid lines in FIG. The addition/subtraction timing signal SC() having the opposite polarity to that shown in FIG. 3C) is supplied to the addition/subtraction circuit 2 and the constant value generation circuit 4.

The timing signal SC() has a timing corresponding to a desired amount of delay, and is supplied to a constant value generating circuit 4, where a constant value αi, which will be described later, is obtained. constant value αi
is supplied to the addition/subtraction circuit 2. In the addition/subtraction circuit 2, the input signals Q0 to Q7 and the constant value αi are added or subtracted according to the timing of the timing signal SC( ), and signals S0 to S7 shown by the solid line in FIG. 3B are taken out. That is, while the timing signal SC() (L level period subtraction in FIG. 3C is performed), its H level period is
Level period addition is performed. The signals S0 to S7 are signals whose waveforms are distorted for a period corresponding to the delay time from the maximum and minimum points of the input signals Q0 to Q7, and their values indicate the magnitude of distortion for the desired signals SS0 to SS7 (described later). When the indicated strain value is x, (0+
x) and {(maximum M)-x}.

Timing signal extracted from addition/subtraction circuit 2
SC1 (D in the figure) has a timing corresponding to the desired delay amount, and is supplied to the timing signal generation circuit 5 together with the timing signal SC (Q) (C in the figure) inputted to the terminal 3, and the timing signal SC2 (E in the same figure).

Signals S0 to S7 taken out from the addition/subtraction circuit 2
(B in the same figure), the timing signal SC2 (E in the same figure) taken out from the timing signal generation circuit 5 is supplied to the amplitude correction circuit 6, and the signals _S0 to _S7 are variously added and subtracted according to the timing of the timing signal SC2. Ru.
That is, the signals _S0 to _S7 are taken out as they are during the L level period of the timing signal SC2, while the value of {(maximum value M) - (distortion value x)} (broken line in B in the figure) is taken out during the H level period _t1 . ), and in the next H level period _t2 , the value is set to (0+x) (broken line in B in the figure), and this is repeated.

In this way, the signals S ₀ to S ₇ (solid lines in FIG. 6B) are corrected in the amplitude correction circuit 6 as shown by the broken lines during predetermined periods t ₁ and t ₂ from their maximum and minimum points, and the signals Extracted as SS0 to SS7.

Signals SS0 to SS7 are supplied to the amplitude adjustment circuit 7,
The amplitudes of the maximum and minimum values are adjusted according to the timing of the signal OF (F in the same figure) and the signal UF (G in the same figure) from the adjustment signal generation circuit 8, and the delayed signal is output from the terminal 9.
They are taken out as DQ0 to DQ7 (dashed lines in A in the figure). Signals OF and UF are timing signals taken out from the addition/subtraction circuit 2 in the adjustment signal generation circuit 8.
It is created in response to the timing of SC1 (D in the same figure).

In this way, the input signals Q0 to Q7 (solid lines in A in the figure) are delayed by a predetermined amount by adding or subtracting a constant value αi, and correcting the period amplitude according to the delay amount di every 1/2 period. The output signals DQ0 to DQ7 (broken lines in FIG. 2B) are extracted. In other words, without using large-scale circuits such as ultrasonic delay lines or shift registers, it is possible to obtain delayed signals DQ0 to DQ7 simply by adding or subtracting a constant value αi to input signals Q0 to Q7 at a predetermined period and then correcting the waveform. I can do it.

Here, let us consider the relationship between the input signal, the amount of delay, and the period. For example, FIG. 4A uses the sampling timing shown in FIG. 4D (same as the clock CK of the adjustment signal generation circuit 8 in FIG. 2).
Regarding the input signal waveforms shown by the solid lines in ~C, consider the waveforms after each delay. For example, in FIG. 4A, the input signal is Vi(t), its peak value is v ₁ ,
Delay time is d ₁ , period is T ₁ , signal after delay is V _d1
(t-di), then V _d1 (t-di) = Vi(t)-{±vi/(Ti/2)}·d ₁ . In general, V _di (t-di) = Vi (t) - {±vi/(Ti/2)}·d ₁ = Vi (t) ±2vi·(d ₁ /Ti). If we set 2vi·(d ₁ /Ti)≡αi here, then V _d1 (t−di) = Vi(t)±αi (1). αi is the constant value mentioned above, and is a value added to or subtracted from the input signal in the addition/subtraction circuit 2 in FIG.

Input signals V ₂ (t), V ₃ (t) shown in Figure 4B and C
Equation (1) above can also be applied to
Delayed signals V _d2 (t- _{d 2 ) ,} V _d3 (t-
_d3 ) can be obtained.

In the above equation (1), when the constant value αi is set constant, and if the period Ti of the input signal Vi(t) changes (each input signal Vi(t), V ₂ shown in FIG. 4 A to C)
(t), V ₃ (t), αi=2vi・(di/Ti), where vi is constant, period Ti and delay time di
will change proportionately.

That is, in FIGS. 4A to 4C, by setting a constant value αi, it is possible to obtain an output signal Vdi (t-di) having a delay time di corresponding to the period (Ti) of the input signal Vi(t). Therefore, when delaying input signals with different frequencies by a delay amount corresponding to the frequency, in conventional circuits it was necessary to change the number of stages in the shift register or change the clock frequency, but with this The invention does not require any such operations.

〔Effect of the invention〕

According to the circuit of the present invention, an output signal with a predetermined amount of delay can be obtained by simply adding or subtracting an input signal to a constant value and then correcting the amplitude of the input signal. Compared to the conventional circuit used, the circuit can be configured more easily and at a lower cost.
In particular, since it is possible to obtain a signal with a delay amount that follows the frequency of the input signal, it is possible to obtain a delayed signal without the need for any operations such as changing the number of stages of a shift register or the clock frequency. It has the following features.

[Brief explanation of drawings]

Figure 1 is a principle block diagram of the circuit of the present invention, Figure 2 is a circuit diagram of an embodiment of the circuit of the present invention, and Figure 3 is a block diagram of the principle of the circuit of the present invention.
Timing chart of the signals of the circuit shown in the figure, No. 4
The figure shows the relationship between the input signal, the amount of delay, and the period, and FIG. 5 is a diagram explaining the number of stages of the shift register. In the figure, 1 is a signal input terminal, 2 is an addition/subtraction circuit, 3 is a timing signal input terminal, 4 is a constant value generation circuit, 5 is a timing signal generation circuit, 6 is an amplitude correction circuit, 7 is an amplitude adjustment circuit, and 8 is adjustment In the signal generation circuit, 9 is an output terminal.

Claims (1)

[Claims] 1. In a signal processing circuit that obtains an output signal (V ₀ (t)) delayed by a predetermined amount of delay (di) with respect to an input signal (Vi (t)), the amount of delay (di) and a timing signal (SC()) having a timing corresponding to the period of the input signal when it has the delay amount (di), and a constant value generating circuit 4 that generates a constant value (αi) from the input signal. Every 1/2 cycle of (Vi(t)), subtract the above constant value (αi) from the above input signal (Vi(t)) and input the above during a period according to the timing of the timing signal (SC()). an addition/subtraction circuit 2 that outputs a signal obtained by adding the above-mentioned constant value (αi) to the signal (Vi(t));
(t)), the period amplitude is corrected according to the delay amount (di), and the output signal (V ₀ (t)) has an amplitude corresponding to the amplitude of the input signal (Vi(t)). 1. A signal processing circuit comprising: an amplitude correction circuit 6 for obtaining