JPH03220918A - A/d converter - Google Patents

Abstract

PURPOSE:To attain highly accurate measurement of an analog quantity and high speed waveform analysis by counting consecutively an output of a V/F converter and calculating a change in a count per a prescribed time so as to apply digital conversion. CONSTITUTION:An endless counter 12 counts consecutively an output signal from a V/F converter 10 outputting a frequency signal proportional to the amplitude of an analog signal, a subtractor 18 samples a counted value of the counter 12 during counting at every prescribed time and outputs continuously the variation in the counted value per prescribed time as a digital value with respect to the analog signal. Thus, the output signal from the V/F converter 10 is counted continuously by the counter 12, and the variation in the counted value per prescribed time is outputted from the subtracting means 18 as the digital value corresponding to the amplitude of the analog signal. Thus, the highly accurate measurement of the analog quantity and the high speed waveform analysis are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field of the Present Invention The present invention relates to an A/D converter that converts an analog signal into a digital value corresponding to its magnitude.

<Prior Art> (Fig. 4) Conventionally, a V/F converter has been used as an A/D converter because it is relatively simple and inexpensive.

FIG. 4 is a block diagram showing the configuration of this V/F conversion type A/D converter.

In Figure 4, 1 is the voltage of the input analog signal.
It is a V/F converter that outputs a pulse signal with a frequency F proportional to is configured to do so.

2 is a counting circuit that counts the frequency of the pulse signal from this V/F converter 1, and this pulse signal is passed through an AND circuit 4 by the gate pulse from the gate signal generation circuit 3, and is counted by N bits for a predetermined period of time. It is input to the counter 5, and the count result is latched by the latch circuit 6 and output as a digital value.

In addition, 7 is a latch pulse generation circuit that outputs a latch pulse that is slightly delayed from the falling edge of the gate pulse, and 8 is a latch pulse generation circuit that outputs a reset pulse that is delayed from the latch pulse and advanced from the rising edge of the gate pulse to reset the counter 5. This is a reset pulse generation circuit.

Therefore, if the analog voltage V changes, the count value latched by the latch circuit 6 will also change in accordance with the change.

<Problems to be Solved> However, with the #Aji1 A/D converter as described above, approximately 3
A fairly long gate time of 2 milliseconds (64/2M) - 1z) is required, and when performing both high-precision measurement of analog quantities and waveform analysis, it is necessary to accurately examine changes in analog signals containing high frequency components. The problem is that it is not possible.

Therefore, it is possible to shorten the gate time to, for example, 178 4 milliseconds to speed up sampling and add 811 to the obtained count value to obtain 16-bit precision. The time required for resetting the V/F converter 1 must be shortened to the extent that it can be ignored with respect to the period of the highest frequency pulse signal output from the V/F converter 1.

That is, since the number of pulses input within this reset time is not included in the count result each time, the result of addition of the count value includes a large error and the #I degree decreases significantly.

For this reason, it is possible to use high-speed elements such as ECL, which can be expected to operate at high speeds, but such high-speed elements are expensive, generate a lot of heat, and have to deal with new problems such as drift, making them difficult to use. There is.

An object of the present invention is to provide an A/D converter that solves this problem.

Means for Solving the Problems> In order to solve the above problems, the A/D converter of the present invention includes: a V/F converter that outputs a signal with a frequency proportional to the magnitude of the analog signal; A counter that continuously counts the output signal from the converter, and a count value that is being counted by the counter is sampled at predetermined time intervals, and the amount of change in this count value per the predetermined time is continuously converted into a digital value with respect to the analog signal. and a subtraction means for outputting the output.

Therefore, the output signal from the V/F converter is continuously counted by the counter, and the amount of change in the count value per predetermined time is output from the subtraction means as a digital value corresponding to the magnitude of the analog signal. It turns out.

Embodiments of the present invention> (Figures 1 and 2) An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of an A/D converter according to an embodiment.

In FIG. 1, 10 is a V/F converter that outputs a pulse signal with a frequency proportional to the analog voltage V. For example, a synchronous type converter in which the output pulse is output in synchronization with the output signal from the crystal oscillator 11 is used. With the V/F converter, the above-mentioned V/F
Similar to converter 1, it outputs pulses with frequencies from zero H2 to 2 MHz for analog voltages from zero volts to 10 volts.

12 is, for example, a 16-bit endless counter that continuously counts the pulse signal from the V/F converter 10.

13 is the count output of this endless counter 12 as the first
A first latch circuit 14 latches the output of the first latch circuit 13 every time it receives a second latch pulse.

15 is a latch pulse generation circuit that divides the clock signal from the crystal oscillator 11 and outputs a first latch pulse every millisecond, for example, and 16 is a write pulse that is delayed by a short time d1 from the first latch pulse. The first delay circuit 17 outputs a second latch pulse that is delayed by a short time d2 from the write pulse.

A subtracter 18 subtracts the output of the second latch circuit 14 from the output of the first latch circuit 13.

The result of this subtraction is TTL when a certain first latch pulse is generated.
-1 to the count value of endless counter 12 at -1
is the count of Tn when the next first latch pulse is generated IaA n
The value Cn is obtained by subtracting from the value Cn, which is a digital value for the magnitude of the analog voltage from T, -1 o'clock to Tn o'clock.

Also, since this digital value is the result of subtraction between the values obtained by latching a maximum 2MHz pulse signal every 1 millisecond,
It has a maximum resolution of "'2000" or 11 bits.

20 is an Ia arithmetic circuit that outputs an integrated value of a predetermined number (32) of continuously input subtraction results; a shift register 21 that sequentially stores the subtraction results; and an adder that adds the contents stored in the shift register 21. It is composed of 22.

Next, the operation of this A/D converter will be explained.

When an analog signal is applied to the V/F converter 10, a pulse signal with a frequency proportional to this signal voltage is output to the endless counter 12, and the counting of the pulse signals progresses, for example, as shown in FIG. 2 (a). The count value A increases.

On the other hand, when the first latch pulse as shown in FIG. 2(b) is output to the TJR, the first latch circuit 13
The count value Aj is latched as shown in (C) in Figure 2, and a slightly delayed concussion pulse ((d) in Figure 2) is generated.
As a result, a value C1 obtained by subtracting the previous count value (referred to as Ao) stored in the second latch circuit 14 from the count value A1 is stored in the shift register 21 ((in FIG. 2)).
e)).

When the second latch pulse slightly delayed from this write pulse is input to the second latch circuit 14 as shown in (f) in FIG. The count value A1 latched in the latch circuit 13 is latched in the second latch circuit 14.

Thereafter, in the same way, the difference in count values every 1 millisecond is sequentially stored in the shift register 21.

For example, 32 subtraction results 02 to 0 are stored in the shift register 21.
When 3B is stored, the output of the adder 22 becomes a digital value corresponding to the voltage magnitude of the analog signal for 32 milliseconds from 11 o'clock to T'i), and the endless counter 12 continues counting. Therefore, there is no accumulation of errors during this time, and the addition result has an accuracy of 16 bits.

When the next subtraction result C61 is stored in the shift register 21, the output of the adder 22 is 32 from 12 o'clock to 14 o'clock.
The digital value corresponds to the magnitude of the analog voltage in milliseconds, and in the same manner, a 16-bit precision digital value corresponding to the analog signal can be obtained every millisecond.

Note that the count of the endless counter 12 overflows and the current count value A is changed from the previous count value A1-.
In some cases, n may be smaller than the subtracter 18.
17 of the latch output An of the first latch circuit 13 in advance.
The subtraction is performed on the assumption that "1" exists in the th bit, so that the correct count difference for the increment is always output.

Another Embodiment of the Present Invention> (Figure 3) In the above embodiment, 3! By storing the subsequent subtraction results in the shift register 21 and adding a predetermined number (32), a digital value with a resolution of 16 bits was obtained. However, when performing waveform analysis, etc. All subtraction results can be stored in a memory circuit and read out with a resolution as required.

In addition, in the above embodiment, the subtraction results with 11-bit resolution were added as they were, but as shown in FIG. , M consecutive 16-bit subtraction results are added by the adder 22-, and the addition results are averaged by the 1/M divider 23 to obtain 16-bit resolution. be able to.

Further, in the above embodiment, a 16-bit endless counter 12 was used, but this does not limit the present invention, and the output frequency at full scale of the V/F converter was divided by the latch frequency. It is only necessary that the value can be counted without overflowing the value, and even in the case of the above embodiment, it is clear that 12 bits or more can be used.

Effects of the Present Invention> As described above, the A/D converter of the present invention continuously counts the output of the V/F converter, calculates the amount of change in the counted value per predetermined time, and converts it into digital. Because of this configuration, it is possible to perform digital conversion with the desired precision even if the sampling interval for analog signals is reduced without using a particularly high-speed counter, and it is possible to perform high-precision measurement of analog quantities and high-speed waveform analysis. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the embodiment,
FIG. 3 is a block diagram showing part of another example of actual flow, and FIG. 4 is a block diagram showing the configuration of a conventional device. 10... V/F converter, 12... Endless counter, 13... First latch circuit,
14... Second latch circuit, 18...
Subtractor, 20...Integrator circuit.

Claims (1)

[Claims] A V/F converter that outputs a signal with a frequency proportional to the magnitude of an analog signal, a counter that continuously counts the output signal from the V/F converter, and a count of the counter. an A/D, characterized in that it is equipped with a subtraction means for sampling a count value of the count value at predetermined time intervals, and continuously outputting the amount of change in the count value per the predetermined time period as a digital value for the analog signal. converter.