JPH0322158A - Computer system - Google Patents

Abstract

PURPOSE:To quickly discover a fault by switching the control signal of a paralell interface and data to either a peripheral device or an internal control circuit with a switching circuit. CONSTITUTION:A switching circuit 4 and an internal control circuit 5 are provided so that connection between a parallel interface 2 and a peripheral device 3 can be switched to connection between the parallel interface 2 and internal control circuit 5 by the switching circuit 4 and the exchange of the data can be executed between a CPU 1 and the internal control circuit 5 through the parallel interface 2, switching circuit 4 and data lines 6-9 when operational defect is generated. Thus, it can be decided whether the operation defect is generated on the CPU 1 side or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer device equipped with a parallel interface, and particularly to a computer device equipped with a parallel interface that connects a CPU and various peripheral devices.

[Conventional technology]

Conventionally, in this type of computer system, there is a method called a handshake method as a typical connection method for a parallel interface that connects a CPU and peripheral devices. In the following, the first method for controlling the parallel interface will be explained using a two-wire handshake as an example of the handshake method.

FIG. 2 is a block diagram illustrating an example of the connection between a conventional converter device and a peripheral device β, and FIG. 3 is a time chart illustrating an example of two-wire handshake control. Next, the control method of the parallel interface will be explained with reference to FIGS. 2 and 3.

Parallel InternoAce 2 reads command B from CPU 1
When the parallel interface 2 wants to receive data from the peripheral device 3 in response to the request, the parallel interface 2 makes the data request signal C valid, that is, set it to logic "1" (time j1). After detecting that the request signal @C has become 1 valid, when it is ready to send data l-1, it outputs data H and makes the acknowledge signal QD valid, that is, logic "1". Time t2).The parallel interface 2 detects that the acknowledge signal Db<@ has become valid, and outputs the data HJF!: data line 7.
At the same time, the data request signal C is invalidated. [ta3] detects that the data request signal C has become invalid, and sets the acknowledge signal RD to logic "0°" (time t3).

Data is exchanged between the CPtJ 1 and the parallel interface 2 via the data line 6 and the CPU bus 10. The parallel interface 2 connects the data port from the data line 7 to the CP in response to the read command B from the CPU 1.
It is sent to the CPU bus 10 via the data line 6 as U data 8 (time ta).

The timing of the data request signal C, the output of the data port, the acknowledge signal @D, and the human power of C P tJ data 8 in the above operation are shown in the timing chart of FIG. 3 in order from the top.

The line that transmits the read command B and the two lines that transmit the data request signal C and the acknowledge signal D each carry data Ii! 6 and data line 7.

[Problem to be solved by the invention]

In the conventional computer equipment mentioned above, when a parallel interface is used to connect the CPU and peripheral devices, for example, when a failure occurs in the parallel interface or the peripheral Ml and data cannot be sent and received normally. When a test is to be performed to find a failure location, the test must be performed while these devices are connected, and therefore, there is a drawback that it takes time to identify the n locations.

Therefore, the present invention eliminates the above-mentioned drawbacks and performs tests using only the C PtJ and the parallel interface with a simple circuit configuration and without connecting peripheral devices. It is an object of the present invention to provide a computer Ml including a parallel interface, which can specify whether or not an accident has occurred.

[Means to solve the problem]

The computer device of the present invention is a computer device that connects a CPU and a peripheral device via a parallel interface for exchanging data with the peripheral device, and stores check data under the control of tiI1 of a CPLJ.
An internal control circuit outputs the check data under the control of υ1, which is the same control signal as the control signal lI11 that controls data transmission from the peripheral device to the parallel interface; and an internal control circuit that outputs the check data by receiving the switching signal output from the CPU, and receiving the switching signal > 4. is the first
When the switching signal is at the second logic level, the data line and control signal line between the parallel interface and the peripheral 5A are connected, and when the switching signal is at the second logic level, the digital data and the same control signal are connected to the internal control. It has a switching circuit that connects a transmission line from the circuit to the parallel interface I-space.

(Function) In this way, the combination 1-ta am is connected to the switching circuit and the internal
Equipped with an I11 circuit, when an initial failure occurs, a switching circuit switches the connection between the parallel interface and the peripheral device to the connection between the parallel interface and the internal υ1 control circuit, and switches the connection between the CPIJ and the internal ill control circuit. between the parallel interface, switching circuit and data line,
Since test data can be exchanged, it is determined whether or not a malfunction has occurred on the CPU side.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the computer system of the present invention. Components whose numbers in FIG. 1 are the same as those in FIG. 2 have the same functions, and both the present embodiment and the conventional example have CPU 1 . It is equipped with a parallel interface 2 and a peripheral ffi3.

In this embodiment, a switching circuit 4 is connected between the parallel interface 2 and the peripheral device 3, the parallel interface 2 and the switching circuit 4 are connected by the data line 8, and the peripheral device 113 and the switching circuit 4 are connected to the data line 17. It is connected.

Further, between the CPU bus 10 and the switching circuit 4, an internal control circuit 5 is connected in parallel with the parallel interface 2.
The CPLI bus 10 and the internal iqm circuit 5 are connected by the data line 9, and the internal control circuit 5 and the switching circuit 4 are connected by the data line 1.
1.

The internal control circuit 5 receives a data set signal from the CPU 1,
” to set the book data M.

The signal 44L output from the switching circuit 4 has the same 11 fl as the data request signal C, and the signal K output from the internal control circuit 5 has the same I as the acknowledge signal 1'ilD.
This is a signal with N capability. The switching circuit 4 receives the switching signal N from the CPU 1, and transfers the data request signal C outputted from the parallel interface 2 and the data H outputted from the peripheral device ta3 to internal! A signal L equivalent to the data request signal C output by the II1 control circuit 5 and the internal control circuit 4
Switch to check data M set in . In this case, the peripheral device I13 is disconnected, and check data M is exchanged between the CPU 1 and the internal control circuit 5 via the parallel interface 2 and the switching circuit 4.

When the switching signal QN is off, the data request signal Ct is output as the data request signal F to the peripheral device 3 via the switching circuit 4, and the acknowledgment signal G in response to it is output as the data request signal F to the peripheral device 3.
Peripheral It! 23, the signal becomes an acknowledge signal D and is sent to the parallel interface 2 via the switching circuit 4. Similarly, the data port of the peripheral device 3 is sent to the parallel interface 2 via the switching circuit 4 and the data [18], and is further sent to the data line 6 and the CPU bus 1.
0 and sent to cpui.

In addition, in FIG. 1 as well as in the second case, the line that transmits the Ill ill signal such as the data request signal C is
Parallel with this line I: It may be included in a certain data line. That is, the line for transmitting the data set signal j is included in the data line 9, and the line for transmitting the data set signal j is included in the data line fi corresponding to the data request signal C.
iL and {i'? corresponding to the acknowledge signal D. Two lines transmitting l<K are included in the data line 11. Also,
Two lines for transmitting data request signal C and acknowledge signal 8D are included in data line 8, and lines for transmitting switching signal N are included in CPU bus 10, data I16 and data line 8.
include.

Next, the operation of this embodiment will be explained with reference to FIG.

When the switching signal N is on, the data request signal PC is output as a signal equivalent to the data request signal C to the internal control circuit 5, and the acknowledge signal D from the internal control circuit 5 is A corresponding signal K is output. Similarly, check data M from the internal control circuit 5 is output as data F. That is, at this time,
The peripheral device @3 is now separated from the parallel interface 2.

In this device, according to an instruction from the CPU 1, the switching signal N
is turned on and check data M is set in the internal control circuit 5 by the data set signal J. If the data is to be received from the peripheral device 3 TFI etc. in response to a request from the CPU, the interface operation is performed to the peripheral device 3. Instead, it is performed on the internal control circuit 5. Also, the data retrieved at this time is the check data M set in advance in the internal control circuit 5 by the CPUIG, and Cr'U1 reads the check data M from the parallel interface 2 and sets the data By comparing with parallel interface 2
It is possible to check whether it is functioning properly.

〔Effect of the invention〕

As explained above, the present invention includes a switching circuit and an internal control circuit, and the switching circuit switches the control signal and data of the parallel interface to the peripheral device or to the internal control circuit. Since the test is performed on a standalone device without connecting peripheral devices, it is easy to identify whether the fault is occurring inside the computer device or in a peripheral device, and the fault can be quickly discovered. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the computer system of the present invention, FIG. 2 is a block diagram showing the combination of a conventional computer device and peripheral devices, and FIG. 3 is a two-wire system. FIG. 3 is a time chart diagram showing an example of handshake control (data transfer by parallel interface). 1... CPU, 2... Parallel interface, 3... Peripheral device, 4... Switching circuit, 5...
・Internal control m+ circuit, 6, 7.8, 9.11...data line, A...CPU
Data, B...Read command, C. F...Data request signal, D. G... Acknowledgment signal, E.口...Data, 1...Data set signal, K...signal equivalent to acknowledge signal D, L...
Signal equivalent to data request signal C, M...Check data, N...Switching signal. Patent No. 71 Applicant [1 木罿 ゆうび 2% 1会本} 浬人 BR 士 IN 原汽车2 1 聜 3

Claims (1)

[Scope of Claims] 1. In a computer device that connects a CPU and a peripheral device via a parallel interface for exchanging data with the peripheral device, check data is stored under the control of the CPU, and data is transferred from the peripheral device to the parallel interface. an internal control circuit that outputs the check data under the control of the same control signal as the control signal that controls data transmission; and an internal control circuit that receives a switching signal output from the CPU, and when the switching signal is at a first logic level, a parallel interface. Connecting a data line and a control signal line between peripheral devices, and connecting a line for transmitting the check data and the same control signal from the internal control circuit to the parallel interface when the switching signal is at a second logic level. A computer device comprising a switching circuit.