JPH0322290A - Read circuit for dynamic ram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a read circuit for a dynamic RAM.

BACKGROUND OF THE INVENTION A conventional dynamic RAM readout circuit is shown in FIG.
) In Fig. 8(a), 1 and 2 are the first and second bit lines a to which the memory cell 3 is connected, and 4 is the sense amplifier circuit, as shown in Fig. 8(b). The circuit shown in is used. 5 is a precharge switch, 6 is a precharge switch, 7 is an equalization switch, 8 is a column decode switch, 9 is an input/output line pair, and 10 is a word line. Conventionally, in the above structure, the following order was used. (1) Precharge switch 6, equalize switch 7
is turned on and each bit line 1, 2 is connected to the precharge power supply 5.

(2) Precharge switch 6, equalize switch 7
is turned off to disconnect each bit line 1 and 2 from the precharge power supply 5.

(3) Select one word line lO and electrically connect memory cell 3 and each bit line l or 2.

(4) The sense amplifier 4 is activated to amplify the signals on each bit line 1 and 2, and (5) the column decode switch 8 is selected to output data to the input/output line pair 9.

However, as the density of dynamic RAM increases (
\ As the bit line spacing becomes narrower, the coupling capacitance between adjacent bit lines tends to increase. Therefore, at present, in the 16Mb first DRAM or 64Mb first DRAM, which is the highest integrated and high-density DRAM, the amount of noise received from adjacent bit lines due to the coupling capacitance is reduced from the entire memory cell. Although it is said that it is about 40% of the read signal of The amount of noise that bit line 2 or 2°, 2'' receives is about 40 mV, and the read signal △V decreases by that amount. For example, in the case of bit line pair l-2, effectively @t-ΔV ++t)-100mV
-40mV=60mV In the case of bit line pair 1'-2°, △V2=(△V$2+△Vse)-100mV+
40mV = 140mV25.

In addition, in the case of bit line pair l"-2", △V 2-(△v@r△VII3→=-( 100mV
-40mV) = -60mV, so there is a problem that the operating margin of the sense amplifier 4 connected to the bit line pair 12 and 1''-2' is reduced. When activated, the potential difference ΔV between bit line pair 12 due to the influence of the interference noise explained earlier. Originally large bit line pair 1
゜-2' IL Bit line pair 1-2 or l''-2'', whose power exchange ΔV was amplified more quickly, had a smaller amplification delay than bit line pair 1 whose amplification was delayed. -2 or 1"-22 (The problem is that amplification becomes slower due to the influence of interference noise from the adjacent bit line pair l-2' which is amplified more rapidly, causing a significant delay in access time or malfunction. The problem is even more important than the above (Imajo) Although it is thought that it will become more and more important in the readout circuit of dynamic RAM that is becoming highly integrated and dense, the present invention has been tried in view of the above-mentioned problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM readout circuit that can suppress the effects of interference noise between bit lines and eliminate Lm operations. In dynamic RAM, each bit line on the reference side is temporarily added with a large capacitance or connected to a power supply when reading a memory cell, thereby suppressing fluctuations in the potential noise of the bit line on the reference side. In the case of a readout circuit, one example of a specific means is a plurality of bits that are paired with a first bit line that is coupled to a memory cell and a second bit line that is electrically complementary to the bit line. In the line pairs, a first semiconductor switch controlled by the first signal line is connected between the first bit lines of each bit line pair, and similarly, a first semiconductor switch controlled by the first signal line is connected between the second bit lines. The second bit line is connected to the semiconductor switch of the power supply line.

Effect of the present invention (above) When the signal ΔV is read out to the first bit line by the above-described structure (i. By turning on the semiconductor switch of the power supply line, all the second bit lines can be connected to a large additional capacitance or the power supply line.The influence of noise from the adjacent bit line, that is, the first bit line, is When the sense amplifier is activated, the number of bit line pairs whose amplification is greatly delayed is reduced, and malfunctions can be reduced. An example of an example of suppressing resistance. 6 @ 7th
The circuit of the embodiment of the present invention shown in the figure basically consists of get,
Since it has the same structure as the conventional circuit shown in FIG. The structure and operation of the readout circuit of the dynamic RAM according to the first embodiment of the present invention will be explained. In FIGS. 1 and 2, the bit line 1. Purpose of placement
In order to make the capacitance between adjacent bit lines the same among the plurality of first and second bit lines, △ In order to prevent the capacitance between adjacent bit lines from becoming small only for the bit line placed at the end. In this embodiment, the dummy first and second bit lines are placed each time the power supply 5 or the additional capacitance l1 is provided.
This is a schematic diagram showing one part of the other part.
The second signal line 30 is the same as the conventional example except that the second signal line 30 controls the first semiconductor switch 21 and the second semiconductor switch 31 for equalizing the bit line pair, respectively. The reading method in this embodiment will be explained using the timing chart shown in FIG. 3. Each bit line l, 2 is connected to the precharge power supply 5 (2) When t=T+, the precharge switch 6,
Only the semiconductor switch 2l connected to the bit line 1 to which the memory cell 3 selected by the word line lO is connected is turned off, and the bit line l is disconnected from the precharge power supply 5.

(3) When t=Ta, select l word lines 10.
To electrically connect the memory cell 3 and the bit line l, (4) At t=Ts, the semiconductor switch 31 that was kept on in (2) is also turned off, and the bit line 2 is connected to a large load capacitance l1 or Disconnect from the bricharge power supply 5.

(5) Activate sense amplifier 4 at t=T4
Amplify the signal on bit line 1 or 2.

(6) When t=Ts, select column decode switch 8 and output data to input/output line pair 9.

Each bit line l or 2ζ on the reference side is all connected, and the influence that each bit line on the reference side receives from the adjacent bit line is such that the readout of the selected memory cells 3 is "0" and the readout level is "l". If reading is mixed, there is a high possibility of some cancellation.Also, even if the amount of cancellation is small, the potential of each bit line on the reference side is all common and the same potential is applied to each bit line pair. The amount of noise is considered to be the same &W
Above all, if a large load capacitance 1L or pre-charge power supply 5 is connected, the amount by which the bit line potential fluctuates due to noise is considered to be extremely small. However, in the worst case, the total series on-resistance Ro- of the plurality of first and second semiconductor switches is lower than that of the power supply. The on-resistance ROM of the series resistor from 5 or capacitor l1 to the bit line located at the farthest position suppresses the noise between power supply 5 or capacitor l during P6●0.
ROM = T / C -10' [Ω] C: Quantitative force interaction of noise If it is 25% of the bit line charge, then 50 fF T :5nsec In other words, in this embodiment, this value is sufficient and even a realizable value.With the above dynamic RAM readout circuit, the voltage at which the potential of each bit line on the reference side is read out to its adjacent bit line, which was a problem in the past. The phenomenon in which the potential difference between each bit line pair becomes small due to fluctuations becomes less likely to occur.

(Example 2) Dynamic RA of the second example of the present invention shown in FIG.
The structure and operation of the readout circuit M will be explained below.The first signal line 2, the second signal line 3o connects the bit line pair to the precharge power supply 5, the first semiconductor switch 2l, the second This embodiment is the same as the conventional example except that it controls the semiconductor switch 3l.
Read out in the following order. Timing chart (shown in Figure 5).

(1) At t=T●, equalize switch 7, 1st, 2nd
Turn on the semiconductor switches 21 and 3l of each bit line 1.
, 2 are connected to the precharge power supply 5.

(2) Equalize switch 7 and word line 1 at t=T+
Only the semiconductor switch 21 connected to the bit line l to which the memory cell 3 selected by 0 is connected is turned off, and only that bit line is disconnected from the precharge power supply 5.

(3) At t=T2, select one word line IO and electrically connect memory cell 3 and bit line 1 or 2.

(4) When t='rt, the semiconductor switch 31 that remained on in (2) is also turned off to disconnect the bit line 2 from the precharge power supply 5.

(5) At time t=T4, the sense amplifier 4 is activated and the signal on the bit line 1 or 2 is amplified.

(6) At t=Ts, select the column decode switch 8 and output data to the input/output line pair 9. All bit lines on the reference side remain connected to the precharge power supply 5. Naturally, the sense amplifier The bit lines whose amplification is greatly delayed when 4 is activated also become resistant to noise from adjacent bit line pairs. The dynamics of
The reading circuit of the link RAM prevents the potential of the bit line on the reference side from fluctuating due to the voltage read to the adjacent bit line, which was a problem in the past (Example 3).
) Next, the structure and operation of the dynamic RAM readout circuit according to the third embodiment of the present invention shown in FIG. 6 will be explained.
The second signal line 30 connects the bit line pair to the input/output line pair 9, respectively.
In this embodiment, it is the same as the conventional example except that it controls the second semiconductor switch 3l.
Read out in the following order. Timing chart ζ friend Since it is basically the same as that shown in FIG. 5, I will explain using it. (1) At t=T●, equalize switch 7, precharge switch 6, 11th second semiconductor switch 21 ,
31 is turned on, each bit line 1, 2, input/output line pair 9
is connected to the precharge power supply 5 (2) When t=T+, it is connected to the equalize switch 7, the precharge switch 6, and the bit line 1 to which the memory cell 3 selected by the word line 10 is connected. Semiconductor switch 2L
is turned off to disconnect only that bit line from the input/output line pair 9.

(3) When t=Ta, one word line IO is selected and the memory cell 3 and the bit line are electrically connected.

(4) At t=Ts, the semiconductor switch 31 that was left on in (2) is also turned off to disconnect the bit line 2 from the input/output line pair 9.

(5) At t=T4, the sense amplifier 4 is activated and the signal on bit line 1 or 2 is amplified. (6) At t=Ts, the 11th and 2nd signals are
Select the semiconductor switches 21 and 31 to output data to the input/output line pair 9.

All the bit lines on the reference side are connected through the input/output line 9. The influence that the bit lines on the reference side receive from adjacent bit lines is small for the same reason as in the first embodiment. This increases by the wiring capacitance of output line 9, but the influence from adjacent bit lines is small.With the above dynamic RAM read circuit, the potential of the bit line on the reference side, which has been a problem in the past, is reduced by the voltage read to the adjacent bit line. The phenomenon in which the potential difference between bit line pairs becomes small due to fluctuations (even though it is unlikely to occur (Embodiment 4)) Next, the structure and operation of a read circuit of a dynamic RAM according to a fourth embodiment of the present invention shown in FIG. To explain this, there is a bit line pair 1 connected to the right side by the third and fourth semiconductor switches 41 and 51 so as to sandwich the sense amplifier 4,
2. Similarly, on the left side, install the first and second semiconductor switches 2.
This is the same as the conventional example except that bit line pairs 1 and 2 connected by lines 1 and 31 are provided. In this embodiment, reading is performed in the following order. The timing chart is basically the same as Fig. 5, so we will explain using that figure. (1) When t=Te, equalize switch 7, precharge switch 6, 11th, second, third, and fourth semiconductor switches Turn on 21, 31, 41, and 51 and connect each bit line l and 2 to the precharge power supply 5 (2) t=
At T+, the equalize switch 7, the precharge switch 6, the bit line to which the memory cell 3 selected by the word line IO is connected, and the bit line placed on the opposite side of the sense amplifier 4. semiconductor switch 21, 41, or 31, 51 that electrically connects
This reduces the additional capacitance of the bit line to which the selected cell is connected.

(3) When t=Ts, select one word line 10 and electrically connect the memory cell 3 and the bit line.

(4) When t='rs, all the semiconductor switches left on in (2) are turned off, and all bit lines are disconnected from the sense amplifier 4.

(5) At time t=T4, the sense amplifier 4 is activated and amplification is completed, and then connected to the bi-soto line again.

(6) When t='rs, select column decode switch 8 and output data to input/output line pair 9.

The bit line on the reference side (reference side) remains connected to the bit line on the opposite side across the sense amplifier 4, so its capacitance is large and fluctuations from the influence from the adjacent bit line are small. ,% Furthermore, in this structure,
When activating the sense amplifier, all bit lines can be disconnected from the sense amplifier.
Although it is thought that the influence from single-connection bit lines is extremely small, in the future, due to higher density, the ratio of the capacitance between adjacent bit lines to the total capacity of the bit line itself will increase.
Don't worry about the influence of noise between the Soto wires. This is considered the best way to solve this problem. With the dynamic RAM readout circuit described above, the conventional problem of the potential of the bit line on the reference side fluctuating depending on the voltage read to the adjacent bit line and the potential difference between the bit line pair becoming small is less likely to occur. Effects As is clear from the above explanation, according to the present invention, the bit line spacing becomes extremely narrow due to the high density of dynamic RAM, and the ratio of the capacitance between adjacent bit lines to the total capacitance of the bit lines themselves increases. It is possible to suppress the influence of noise from adjacent bit lines, which is a problem with the timing diagram of the first embodiment of the present invention, by simply adding signal lines and changing the control method. Figure 4 is a dynamic RAM readout circuit according to the second embodiment of the present invention; Figure 5 is a timing chart of the second embodiment of the present invention; Figure 6 is the dynamic RAM readout circuit according to the third embodiment of the present invention. 7 is a dynamic RAM readout circuit according to the fourth embodiment of the present invention. FIG.
1"...First bit turtle 2.2'.2"...・
Second bit a 3...Memory Seno L/. 4...
・Sense amplifier, 11...Load capacity, 20...
First signal turtle 21...first semiconductor switch, 30
...Second signal f&3l...Second semiconductor switch, 40...Third signal Tortoise 41...Third semiconductor switch, 50...Signal line of Sword 4 , 51...
-Fourth semiconductor switch.

Claims (8)

[Claims] (1) In a plurality of bit line pairs consisting of a first bit line coupled to a memory cell and a second bit line electrically complementary to the first bit line, each bit line pair is A first semiconductor switch controlled by a first signal line is connected between the first bit lines, and a second semiconductor switch controlled by a second signal line is connected between the second bit lines. A dynamic RAM readout circuit characterized in that a semiconductor switch is connected to the dynamic RAM. (2) The dynamic RAM according to claim 1, characterized in that a load capacitor having a capacitance value sufficiently larger than the bit line capacitance is connected to each of the first semiconductor switch and the second semiconductor switch. readout circuit. (3) a first semiconductor switch, a second semiconductor switch,
2. The dynamic RAM readout circuit according to claim 1, wherein a power supply line is connected to each of the dynamic RAM readout circuits. (4) In a plurality of bit line pairs consisting of a first bit line coupled to a memory cell and a second bit line electrically complementary to the first bit line, each bit line pair is A first line is connected between the first bit line and the power supply line, respectively.
connecting a first semiconductor switch controlled by a signal line of
Similarly, a dynamic RAM read circuit characterized in that second semiconductor switches each controlled by a second signal line are connected between the second bit line and the power supply line. (5) In a plurality of bit line pairs consisting of a first bit line coupled to a memory cell and a second bit line electrically complementary to the first bit line, each bit line pair is A first semiconductor switch controlled by a first signal line is connected between the first bit line and the first input/output data line, and similarly, a first semiconductor switch controlled by the first signal line is connected between the second bit line and the first input/output data line. A readout circuit for a dynamic RAM, characterized in that a second semiconductor switch controlled by each second signal line is connected between a second output data line that is electrically complementary to the output data line. . (6) A first bit line coupled to a memory cell and a second bit line electrically complementary to the bit line are each connected to a first semiconductor switch controlled by a first signal line. A second semiconductor switch controlled by a second signal line is connected to the sense amplifier circuit, and a third bit line on the opposite side of the sense amplifier circuit is electrically complementary to the third bit line. The fourth bit line is connected to the sense amplifier circuit by a third semiconductor switch controlled by a third signal line and a fourth semiconductor switch controlled by a fourth signal line, respectively. Dynamic RAM readout circuit. (7) At the timing of bit line equalization, the first
When the first semiconductor switch and the second semiconductor switch are turned on using the signal line and the second signal line, and the word line is selected to read out the memory cell, the selected memory cell is connected. Only the semiconductor switch connected to the bit line on the side being turned off using the first or second signal line, and when the sense amplifier circuit is activated, the first or second signal line is used to turn off the semiconductor switch connected to the bit line on the side where the , first,
6. The dynamic RAM read circuit according to claim 1, wherein both of the second semiconductor switches are turned off. (8) At the timing of bit line equalization, the first
, the first, second, third, and fourth semiconductor switches are turned on using the second, third, and fourth signal lines to select the word line and read the memory cell. Turn off only the semiconductor switch that electrically connects the bit line to which the memory cell is connected and the bit line located on the opposite side of the sense amplifier, and activates the sense amplifier circuit. 7. The dynamic RAM read circuit according to claim 6, wherein all of the first, second, third, and fourth switches are turned off at the timing.