JPH03224041A - Capacity recognizing method for externally connected ram - Google Patents

Capacity recognizing method for externally connected ram

Info

Publication number
JPH03224041A
JPH03224041A JP2018079A JP1807990A JPH03224041A JP H03224041 A JPH03224041 A JP H03224041A JP 2018079 A JP2018079 A JP 2018079A JP 1807990 A JP1807990 A JP 1807990A JP H03224041 A JPH03224041 A JP H03224041A
Authority
JP
Japan
Prior art keywords
data
ram
address
memory capacity
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2018079A
Other languages
Japanese (ja)
Inventor
Shoichi Matsumoto
正一 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2018079A priority Critical patent/JPH03224041A/en
Publication of JPH03224041A publication Critical patent/JPH03224041A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the chip area of an IC and to decrease the number of external parts by making a voice solid-state recording and reproducing IC recognize automatically the capacity of an externally connected RAM with an access given from the IC at the time of an initial action. CONSTITUTION:The data are read out of the address of a RAM 2a at the time of the initial action of a voice solid-state recording and reproducing IC 1. These read data are held by the IC 1 and a certain data is written into the address of the RAM 2a. Then the data is read again out of the address of the RAM 2a. If the coincidence is secured between the read data and the written ones, it is decided that the RAM 2a is connected to the IC 1 and is normally working. Then the areas are previously secured in 1st and 2nd addresses of respective RAMs to write the specific data indicating that the memory capacity is already checked. Simultaneously, an area is secured in a 3rd address to write the memory capacity data. When the memory capacity is recognized at the time of initial action, the specific data indicating that the memory capacity is already checked are written into the 1st and 2nd addresses of respective RAMs together with the memory capacity data written into the 3rd memory respectively. Thus the IC chip area is reduced and the number of external parts can be decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、音声固体録音再生ICに外部接続の音声デー
タ格納用RAMの容量を認識させる方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for making an audio solid-state recording and reproducing IC recognize the capacity of an externally connected audio data storage RAM.

〔従来の技術〕[Conventional technology]

従来、音声固体録音再生ICに音声データ格納用RAM
を外部接続する時、ICに接続メモリ容量を認識させる
のに、接続するメモリ容量に応じて、あらかじめ、外部
からメモリ容量の情報を設定するという方法を採ってき
た。
Conventionally, audio solid-state recording and playback ICs had RAM for storing audio data.
When externally connecting an IC, a method has been adopted in which memory capacity information is set externally in advance in accordance with the memory capacity to be connected, in order to make the IC recognize the connected memory capacity.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の音声固体録音再生ICでは、外部接続の音声デー
タ格納用RAMの容量を認識させるのに、外部からメモ
リ容量の情報を設定するという方法を採ってきたので、
設定のための端子の増加によるIC面積の増大、外付部
品の増加という問題があった。
Conventional audio solid-state recording and playback ICs have adopted a method of setting memory capacity information externally in order to recognize the capacity of externally connected audio data storage RAM.
There are problems in that the IC area increases due to the increase in the number of terminals for setting, and the number of external components increases.

本発明は上記の問題を解消するためになされたもので、
ICに外部接続RAMの容量を、外部から設定すること
なく認識させる方法を提供することを目的とする。
The present invention was made to solve the above problems.
It is an object of the present invention to provide a method for making an IC recognize the capacity of an externally connected RAM without setting it from the outside.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の方法は、初期動作時に、音声固体録音再生IC
に、ICからのアクセスにより、外部接続RAMの容量
を自動的に認識させるものである。
In the method of the present invention, during initial operation, the audio solid-state recording and playback IC
Second, the capacity of the externally connected RAM is automatically recognized by access from the IC.

〔実施例〕〔Example〕

第1図は音声固体録音再生ICへのRAMの接続状態の
一例を示す。
FIG. 1 shows an example of the connection state of the RAM to the solid-state audio recording and reproducing IC.

図において1は音声固体録音再生IC,2a。In the figure, 1 is an audio solid-state recording and playback IC, 2a.

2b、2cはRAM、3はアドレスバス、4はデータバ
ス、5はチップセレクトラインである。
2b and 2c are RAMs, 3 is an address bus, 4 is a data bus, and 5 is a chip select line.

以下、本発明の詳細な説明する。The present invention will be explained in detail below.

音声固体録音再生ICIの初期動作時に、RAM2aの
アドレス(アドレスへアクセスしていく方法は後で説明
する方法による)からデータを読み込み、そのデータを
音声固体録音再生ICIが保持し、あるデータ(例えば
次の4パターン; OF’、5AHA5’  FO’)
をそのアドレスに書き込み、再びそのアドレスからデー
タを読み込む。書き込んだデータと読み込んだデータを
比較して一致すれば、RAM2aは接続されていて正常
に動作していることが同時に判る。その後音声固体録音
再生ICIで保持していたデータを書き込んで元の状態
に戻す。
During the initial operation of the audio solid-state recording and reproducing ICI, data is read from the address of the RAM 2a (the method for accessing the address is explained later), and the audio solid-state recording and reproducing ICI retains that data, and stores certain data (e.g. The following 4 patterns; OF', 5AHA5'FO')
is written to that address, and data is read from that address again. When the written data and the read data are compared and they match, it is simultaneously determined that the RAM 2a is connected and is operating normally. After that, the data held by the audio solid state recording and playback ICI is written to restore the original state.

アドレスへアクセスしていく方法は、LSB(最下位桁
ビット)をカウントアツプしていき、オーバーフローす
るごとに、ビット1〜MSB(最上位桁ビット)をシフ
トアンプしていく方法による。
The method of accessing the address is to count up the LSB (least significant bit) and shift-amplify bits 1 to MSB (most significant bit) each time there is an overflow.

RAM2b、2cに対しても上記と同じことを行うこと
により、接続メモリ容量を知ることができる。
By doing the same thing as above for the RAMs 2b and 2c, it is possible to know the connected memory capacity.

上記方法の処理時間を短縮するため、本発明では、あら
かしめ、RAMの第1番目、第2番目のアドレスにメモ
リ容量チェック済を現わす特定のデータを書き込む領域
と、第3番目のアドレスにメモリ容量データを書き込む
領域を確保しておき、初期動作時の音声固体録音再生I
CIからのアクセスによる容量認識が終ると、各RAM
の第1番目、第2番目のアドレスにメモリ容量チェック
済を現わす特定のデータを、第3番目のアドレスにメモ
リ容量データを書き込む。
In order to shorten the processing time of the above method, the present invention provides an area for writing specific data indicating that the memory capacity has been checked at the first and second addresses of the RAM, and at the third address. Secure an area to write memory capacity data, and perform audio solid-state recording and playback during initial operation.
After the capacity recognition by access from CI is completed, each RAM
Specific data indicating that the memory capacity has been checked is written to the first and second addresses, and memory capacity data is written to the third address.

そして、以後の容量認識を第1番目、第2番目、第3番
目のアドレスからのみの読み込みで行なうこととした。
Then, it was decided that subsequent capacity recognition would be performed by reading only from the first, second, and third addresses.

第2図は上記方法による容量認識のフローチャート、第
3図は第2図におけるアドレスの表示法を示すメモリマ
ツプである。
FIG. 2 is a flow chart of capacity recognition using the above method, and FIG. 3 is a memory map showing a method of displaying addresses in FIG.

先ず、外部接続RAMの第1番目、第2番目のアドレス
からデータを読み込み、読み込んだデータが特定のデー
タと一致するか否かを調べ、一致する場合は、第3番目
のアドレスからメモリ容量データを読み込んで該RAM
の容量を認識する。
First, data is read from the first and second addresses of the externally connected RAM, and it is checked whether the read data matches specific data. If they match, the memory capacity data is read from the third address. Read the corresponding RAM
Recognize the capacity of

データが一致しない場合は、先に説明したアドレスにあ
るデータを書き込み、そのアドレスからデータを読み込
んでいく方法により該RAMの容量を認識するとともに
、第1番目、第2番目、第3番目のアドレスにそれぞれ
所定のデータを書き込む。
If the data do not match, the capacity of the RAM is recognized by writing the data at the address described above and reading data from that address, and the first, second, and third addresses are Predetermined data is written to each.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、あらかじめ、音
声固体録音再生ICに外部から接続メモリ容量のデータ
を設定する必要がなくなり、設定するための端子の削減
によるICのチップ面積の縮小と、外付部品の減少に連
なるという効果がある。
As explained above, according to the present invention, it is no longer necessary to externally set connection memory capacity data to the audio solid-state recording and playback IC in advance, and the chip area of the IC can be reduced by reducing the number of terminals for setting. This has the effect of reducing the number of external parts.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は音声固体録音再生ICへのRAMの接続状態の
一例を示す説明図、第2図は本発明の容量認識方法のフ
ローチャート、第3図は第2図におけるアドレスの表示
法を示すメモリマツプである。 1・・・音声固体録音再生IC12a、  2b、2C
・・・RAM、3・・・アドレスバス、4・・・データ
バス、5・・・チップセレクトライン。 実用新案登録出願人 新日本無線株式会社 3ニアドレスバス アドレス 第 図 第 図
FIG. 1 is an explanatory diagram showing an example of the connection state of RAM to the audio solid-state recording and playback IC, FIG. 2 is a flowchart of the capacity recognition method of the present invention, and FIG. 3 is a memory map showing the address display method in FIG. It is. 1...Audio solid recording and playback IC12a, 2b, 2C
...RAM, 3...address bus, 4...data bus, 5...chip select line. Utility model registration applicant New Japan Radio Co., Ltd. 3 Nearest Address Bus Address Figure Figure

Claims (1)

【特許請求の範囲】[Claims] 音声固体録音再生ICに外部接続の音声データ格納用R
AMの容量を認識させる容量認識方法で、あらかじめ、
RAMの第1番目、第2番目のアドレスにメモリ容量チ
ェック済を現わす特定のデータを書き込む領域と、第3
番目のアドレスにメモリ容量データを書き込む領域を確
保しておき、初期動作時に、音声固体録音再生ICにI
Cからのアクセスにより接続各RAMの容量を認識させ
て、第1番目、第2番目のアドレスにメモリ容量チェッ
ク済を現わす特定のデータを、第3番目のアドレスにメ
モリ容量データを書き込ませ、すでに第1番目、第2番
目のアドレスにメモリ容量チェック済を現わす特定のデ
ータを、第3番目のアドレスにメモリ容量データを書き
込んであるRAMではこれらデータを読み込ませること
で容量を認識させることを特徴とする外部接続RAMの
容量認識方法。
R for audio data storage externally connected to audio solid-state recording and playback IC
With the capacity recognition method that recognizes the capacity of AM, in advance,
An area where specific data indicating that the memory capacity has been checked is written to the first and second addresses of the RAM, and an area where the third address is written.
An area for writing memory capacity data is secured at the second address, and at the time of initial operation, the I
The capacity of each connected RAM is recognized by access from C, and specific data indicating that the memory capacity has been checked is written to the first and second addresses, and memory capacity data is written to the third address. In a RAM in which specific data indicating that the memory capacity has been checked has already been written to the first and second addresses, and memory capacity data has been written to the third address, the capacity can be recognized by reading these data. A method for recognizing the capacity of an externally connected RAM.
JP2018079A 1990-01-30 1990-01-30 Capacity recognizing method for externally connected ram Pending JPH03224041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018079A JPH03224041A (en) 1990-01-30 1990-01-30 Capacity recognizing method for externally connected ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018079A JPH03224041A (en) 1990-01-30 1990-01-30 Capacity recognizing method for externally connected ram

Publications (1)

Publication Number Publication Date
JPH03224041A true JPH03224041A (en) 1991-10-03

Family

ID=11961645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018079A Pending JPH03224041A (en) 1990-01-30 1990-01-30 Capacity recognizing method for externally connected ram

Country Status (1)

Country Link
JP (1) JPH03224041A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101950368A (en) * 2010-09-20 2011-01-19 珠海天威技术开发有限公司 Recognition method of storage capacity of 24C series chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101950368A (en) * 2010-09-20 2011-01-19 珠海天威技术开发有限公司 Recognition method of storage capacity of 24C series chip

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