JPH03224077A - Unique information input method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is effective for initial settings such as when manufacturing a logic LSI having a memory element (hereinafter simply referred to as rLSIJ) and testing with an LSI tester at the time of acceptance. The present invention relates to a unique information input method, and particularly relates to a unique information input method that makes it possible to reduce the number of used pins of an LSI. Note that here, the unique information refers to, for example, information regarding the device of an element in an LSI.

[Conventional technology]

As a conventional method of this kind, for example, Japanese Patent Application Laid-Open No. 57-8
A method disclosed in Japanese Patent No. 823 is known.

In this method, the output pin of the LSI is bidirectional, and a control signal is inputted from the outside to set/reset the memory element inside the LSI.

[Problem to be solved by the invention]

In the above conventional technology, the LS
It was necessary to input a control signal from outside, put the LSI into an initial setting mode, and input the control signal to the LSI once for each storage element to initialize the LSI.

However, the above-described initial setting method has serious problems in that it takes a long time to perform the initial setting and also requires a lot of effort. Furthermore, L
As SIs become more highly integrated, the number of input/output pins for inputting and outputting the above-mentioned control signals increases, creating a serious problem in terms of implementation.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology, and to improve the LS
An object of the present invention is to provide a unique information input method that makes it possible to reduce the number of pins used in I.

[Means to solve the problem]

The above-mentioned object of the present invention is to provide an LSI having a unique information input timing signal generation circuit and a timing signal output pin;
and a timing signal outputted from the specific information input timing signal generation circuit inside the LSI during initial setting in the specific information input device for the LSI having a specific information output control unit that controls input of specific information to the LSI. by outputting from the timing signal output pin, the specific information output control section is put into a movable state, and the specific information is output from the specific information output control section within a certain period of time during which the timing signal is output. This is achieved by the characteristic unique information input method.

[Effect]

In the unique information input method according to the present invention, at the time of initial setting by power-on and reset, the unique information input timing signal generation circuit built in the LSI generates the unique information input timing signal for a certain period of time until the main control circuit operates. Output. This unique information input timing signal is output from the input timing signal output pin to the outside of the LSI, and
I set the external specific information output control unit to the active state, and while the specific information output control unit is in the active state, that is, while the specific information input timing signal is being output, the pins of the LSI (common to the main storage unit) In this system, specific information is input to the LSI by sharing the same bus.

This makes it possible to input a large amount of unique information to the LSI at the same time, and since this input is performed by sharing the pins of the LSI (common bus with the main memory), when there is a lot of unique information, However, it brings about the effect that it is possible to prevent an increase in the number of pins of an LSI.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing an example of a circuit configuration to which the present invention is applied. In the figure, ■ indicates an LSI, and the LS
II is the main control unit 2. It is composed of unique information holding circuits 31 to 3N and a unique information input timing signal generation circuit 4. Further, the LS 11 is incorporated on a board (not shown) together with specific information output control circuits 51 to 5N, specific information setting circuits 61 to 6N, a main storage section 9, etc., which will be described later. The above-mentioned unique information output control circuits 51 to 5N control the L of the information set by the unique information setting circuits 61 to 6N.
The output control for the SII is performed by the unique information output control signals 81 to 8N output from the unique information input timing signal generation circuit 4, and the unique information holding circuits 31 to 3N
The holding control of the unique information is performed using the unique information holding control signals 71 to 7N outputted from the unique information input timing signal generation circuit 4 as well. Note that the LSII inputs unique information via a common bus IO with the main storage unit 9, as will be described in detail below.

FIG. 1 is a timing chart showing the operation of this embodiment configured as described above.

The operation of this embodiment will be explained below based on FIGS. 1 and 2.

First, during initial setup by powering on and resetting, the LS
The unique information input timing signal generation circuit 4 of II sequentially outputs the unique information input control signals 81 to 8N for a certain period of time. The unique information output control circuits 51 to 5N are activated by the unique information input control signals 81 to 8N, and the unique information input control signals 81 to 8N output the unique information set in the unique information setting circuits 61 to 6N. output to the common bus 10 for a certain period of time. That is, the unique information set in the unique information setting circuits 61 to 6N is sequentially outputted from the unique information output control circuits 51 to 5N in response to the unique information input control signals 81 to 8N.

The unique information output to the common bus IO is input to the unique information holding circuits 31 to 3N of the LSII, and the unique information holding control signals 71 to 3N corresponding to the unique information input control signals 81 to 8N are input to the unique information holding circuits 31 to 3N of the LSII.
It is held by 7N. The timing chart of FIG. 1 clearly shows this situation.

FIG. 3 shows a schematic flow of the operation.

The unique information input control signals 81 to 8N are turned off after a certain period of time, and the unique information output control circuits 51 to 5N are connected to the common bus l.
Separate from O. After the unique information input control signals 81 to 8N are turned off, the main control circuit 2 starts operating.

According to the above embodiment, when controlling the input of specific information to an LSI having a specific information input timing signal generation circuit and a timing signal output pin, the timing output from the specific information input timing signal generation circuit inside the LSI is performed. By outputting a signal from the above-mentioned timing signal output pin, the specific information output control unit is made active, and within a certain period of time during which the above-mentioned timing signal is output, the specific information is output from the above-mentioned specific information output control unit to the common bus. Since the configuration is configured such that the information is output through the LSI, it is possible to realize a unique information input method that can reduce the number of pins used in the LSI when inputting unique information during initial settings and the like.

It should be noted that the above-mentioned embodiment is shown as an example of the present invention, and it goes without saying that the present invention should not be limited thereto. For example, instead of providing a plurality of unique information setting circuits and unique information output control circuits in parallel, a circuit that outputs unique information serially is provided and this is synchronized with the aforementioned unique information input control signals 81 to 8N. , a modification in which switching is performed sequentially is also possible.

〔Effect of the invention〕

As described above in detail, the present invention includes an LSI having a unique information input timing signal generation circuit and a timing signal output pin, and a unique information output control section that controls input of unique information to the LSI. Said LSI
In the unique information input device for , the unique information output control section is put into a movable state by outputting a timing signal output from the unique information input timing signal generation circuit inside the LSI from the timing signal output pin during initial setting. Since the unique information is configured to be outputted from the unique information output control section within a certain period of time during which the timing signal is output, the number of pins used on the LSI can be reduced when inputting the unique information during initial settings, etc. This has the remarkable effect of making it possible to realize a unique information input method.

[Brief explanation of drawings]

FIG. 1 is a timing chart showing the operation of an embodiment of the present invention, FIG. 2 is a diagram showing an example of an electric circuit to which the present invention is applied, and FIG. 3 is a schematic flowchart of the operation. 1: LSI, 2: Main control unit, 31 to 3N: Unique information holding circuit, 4: Unique information input timing signal generation circuit, 51
~5N=specific information output control circuit, 61 to 6N: specific information setting circuit, 71 to 7N: specific information holding control signal, 81 to 8N=specific information output control signal, , main storage section, lO: common bus.

Claims (1)

[Claims] 1. In an LSI having a unique information input timing signal generation circuit and a timing signal output pin, and a unique information input device for the LSI having a unique information output control unit that controls input of unique information to the LSI, initial settings are performed. By outputting a timing signal outputted from the specific information input timing signal generation circuit inside the LSI from the timing signal output pin, the specific information output control section is put into a movable state, and the timing signal is output. A unique information input method characterized in that unique information is output from the unique information output control section within a certain period of time.