JPH03224199A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, such as a bipolar CMOS (hereinafter abbreviated as Bi-CMO5) type RAM (random access memory), etc. It relates to techniques that are particularly effective when used.

[Prior Art] Static memory cells whose basic configuration is a MOSFET (metal oxide semiconductor field effect transistor; in this specification, MOSFET is a general term for insulated gate field effect transistor) are arranged in a grid pattern. ECL (ECL), whose basic configuration is a memory array made up of
Mitter Co.

pled logic) circuit and CMO5 (complementary type M
There is a B1-CMOS type RAM that is equipped with a peripheral circuit constituted by a B1-CMO8 composite circuit or the like, which is a combination of these circuits, and achieves both high-speed operation and high-density integration of elements. 13i・CMO
S-type RAM usually has interface conditions that are compatible with the ECL level, and its peripheral circuits are designed to be compatible with the ECL circuit, 0M03 circuit, or B1/CMOS composite circuit, while comprehensively evaluating power consumption, operating speed, etc. Different uses will be made.

Regarding Bi CMOS type RAM, for example, 1988
February 18th
(ISSCC) Digest of Technical Babers
Papers) 5ESSION Xn1J No. 184
It is described on pages 185 to 185.

[Problem to be solved by the invention]

FIG. 9 shows the X address buffer
A circuit diagram of I is illustrated. In the figure, the X address buffer XBI includes three current switch circuits C81 to C33 provided corresponding to external terminals AO-A2 and three pairs of level conversion circuits that receive complementary output signals of these current switch circuits. LC1 and LC2 to LC5 and LC
6. E supplied via external terminals AO to A2
The CL level address signals AO to A2 are input to the corresponding current switch circuits of the X address buffer The signal a0 and the inverted internal address signal aO are collectively expressed as a complementary internal address signal aO.Hereinafter,
The same applies to complementary signals).

Complementary internal address signal! 0 to a2, as shown in FIG.
As a result, its output signals, that is, predecode signals X10 to X17 are alternatively set to low level. As shown in FIG. 6, these predecode signals, together with predecode signals X2O-X27 supplied from the X predecoder PXD2,
-X including CMOS NOR gate circuits BN01 to BNO3
are supplied to the address decoder XD in a predetermined combination,
As a result, the word lines WO to W of the memory array MARY
63 is alternatively set to a high level selection state.

However, the inventors of the present invention have found that the above-mentioned CMOS type RAM suffers from the following problems, particularly at the initial stage of power-on. In other words, the X address buffer X of the Bi CMOS type RAM
The current switch circuits C3I to C53 that constitute the BI etc. are as follows:
As illustrated in FIG. 9, a predetermined constant voltage of 1.5 V
Transistor T4 receiving BE and emitter load resistor R3
and constant current sources, respectively.

The above constant voltage 1.5 V BE is B1/CMOS type RA
When the power supply voltage of M is stabilized, it is stabilized to the desired potential. However, if the absolute value of the power supply voltage of the circuit does not reach a predetermined value, such as when the power is initially turned on, the constant current source may not function normally. This value becomes too small to cause the constant current source to turn off, and the transistor T4 constituting the constant current source becomes substantially in a cant-off state. For this reason, the current switch circuits C3I to C3
Both the inverting output node n1 and the non-inverting output node n2 of No. 3 go to a high level such as -VBE (here, VBE indicates the base-eminter voltage of the bipolar transistor), which causes the level conversion circuits LC1 to LC6 to
, that is, the non-inverted and inverted signals of the complementary internal address signals 0 to 12 are both at an intermediate level. Therefore, the output signals of X predecode signals D1 and PXD2, that is, predecode signals X10-X17 and X20
~X27 becomes low level all at once, and memory array MA
All word lines WO to W63 of RY are fully selected. As a result, a large operating current exceeding the limit is temporarily caused to flow, which may cause an abnormality in the power supply system of the B i -CMOS type RAM.

An object of the present invention is to stabilize the operation of a Bl-CMO8 type RAM or the like when the power supply voltage is unstable. Another object of the present invention is to prevent an abnormal increase in the operating current of a 13i-cMOS type RAM or the like at the initial stage of power-on, and to protect its power supply system.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

Means for Solving Problem C] A brief summary of typical inventions disclosed in this application is as follows.

That is, a 13i-CMO5 type RAM equipped with an X address buffer including a current switch circuit and a level conversion circuit.
etc., a power supply voltage detection circuit that has the same operating characteristics as the current switch circuit with respect to the power supply voltage and selectively enables its output signal when the absolute value of the power supply voltage does not reach a predetermined value; A pull-down or pull amplifier MO3FET is provided which is selectively turned on according to the output signal of the power supply voltage detection circuit and forcibly fixes the output signal of the level conversion circuit to a low level or a high level.

[Operation] According to the above means, even if the absolute value of the power supply voltage does not reach a predetermined value at the initial stage of power-on, and the current switch circuit such as the X address buffer does not operate normally, the output of the level conversion circuit is By forcibly fixing the signal to a low level or a high level, it is possible to prevent all word lines from being selected. As a result, it is possible to stabilize the operation of the B1 CMOS type RAM, etc. when the power supply voltage is unstable, prevent an abnormal increase in operating current, and protect the power supply system.

〔Example〕

Figure 8 shows the Bi-CMO5 type R to which this invention is applied.
A block diagram of one embodiment of an AM is shown. Further, FIG. 1 shows a circuit diagram of an embodiment of the X address huffing circuit of the Bi-CMO5 type RAM shown in FIG. 8, and FIGS. 2 and 3 show the power supply voltage detection circuit VCL and A circuit diagram of an embodiment of the constant voltage generating circuit VRF is shown. Furthermore, FIGS. 5, 6, and 7 show the X predecoder PXD of the Bi CMOS type RAM in FIG.
I and X address decoder XD and memory array M
A circuit diagram of one embodiment of the ARY is shown in each case. Based on these figures, the 134-cMOs type R of this example
An overview of the configuration and operation of AM as well as its characteristics will be explained. In addition, Figures 1 to 3 and Figures 5 to 7
Each circuit element in the figure and the circuit elements constituting each block in FIG. 8 are formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques, although not particularly limited thereto. . In the diagram below,
MO with an arrow added to the channel (back gate) part
The SFET is of the P-channel type and is shown to distinguish it from the N-channel MO3FET, which is not marked with an arrow. Also,
The illustrated bipolar transistors are all NPN type transistors, although they are not particularly limited.

In FIG. 8, Bi・CMOS type O3M of this embodiment is shown.
is selectively put into an operating state according to a chip selection signal C5 supplied as an activation control signal from the outside, although not particularly limited, and its operation mode is selectively specified according to a write enable signal WE. Bi・CMOS type O3M
is not particularly limited, but 4096X4 or 163
It has a storage capacity of 84 bits (so-called 16 kilobits), and has four data input terminals DinO to Din3 and data output terminals DoutQ to Dout3 to which stored data is input or output, and 12 data output terminals to which address signals are input. It includes address input terminals AO to All.

Although not particularly limited, the memory array MARY includes 64 word lines WO-W63 arranged in the horizontal direction and 64 word lines WO-W63 arranged in the vertical direction, as illustrated in FIG.
It includes six sets of complementary data lines Do-Dan 255. At the intersections of these word lines and complementary data lines, 64×256, or 16384, static memory cells MC are connected.
are arranged in a grid pattern. In this embodiment, the complementary data lines DO to D255 are grouped into four data line groups, as will be described later, and each data line group is brought into a selected state at the same time.

The memory cells MC constituting the memory array MARY include, but are not particularly limited to, a pair of N-channel type drive MO3FETs Q56 and Q57 whose gates and drains are cross-coupled to each other, as illustrated in Figure '$7. The drain of the driving MO3FET and the ground potential of the circuit (
The commonly coupled gates and drains of the drive MO3FETs Q56 and Q57 each include two load resistors provided between the first power supply voltage (first power supply voltage) and the non-inverting and inverting input/output nodes of each memory cell MC. Although not particularly limited, N-channel type control MO3FETQ
54 and Q55 to the non-inverting or inverting signal line of the corresponding complementary data line. Above system @MOS
The gates of FETs Q54 and Q55 are commonly coupled to corresponding word lines WO to W63. Also drive MO3FET
The sources of Q56 and Q57 are coupled to the circuit's power supply voltage (second power supply voltage). Here, the power supply voltage of the circuit is
Although not particularly limited, a negative power supply voltage such as -5.2V is used.

Word lines WO to W63 forming memory array MARY
Although not particularly limited, is coupled to the X address decoder XD and is alternatively set in the selected state. Although not particularly limited to the X address decoder XD, the X pre-decoder PX
From D1 and PXD2, B') Qi7-F signal Xl
0-X17 and X20-X27 are supplied. These predecode signals are selectively set to a low level according to the corresponding 3-bit address signal AO-A2 or A3 to Δ5, as will be described later.

Although not particularly limited, the X address decoder
As shown in the figure, 64 Bk-CMOS NOR gate circuits BN are provided corresponding to the word line WO-W63.
Contains 01 to BNO3. These B1-CMOS NOR gate circuits are similar to the Bi-cMOS NOR gate circuit B in FIG.
As represented by NOI, the basic configuration is a pair of output transistors T16 and T17 provided in a totem pole configuration between the ground potential and the power supply voltage of the circuit, and the input terminals of the pair have the above-mentioned predecode Signal X10~
X17 and X20 to X27 are respectively supplied in corresponding predetermined combinations. The output terminal of each Bi CMOS NOR gate circuit is used as the output terminal of the X address decoder XD, and the corresponding word line WO~ of the memory array MARY
W63 respectively.

Each B1-CMOS NOR gate circuit of the X address decoder XD receives predecode signals XIO~Xi7 and X20~
When X27 are in a corresponding combination and are both row I novels, the output signal thereof is selectively set to high level.

As a result, the corresponding word line W of the memory array MARY
O to W63 are alternatively set in the selected state.

The X predecoders PXDI and PXD2 include, but are not limited to, a corresponding X address buffer XBI or XB.
2, 3-bit complementary internal address signals 0 to 2 or a3 to a5 are supplied. These complementary internal address signals are formed according to the corresponding address signals AO-A2 or A3-A5.

Although the X predecoders PXD1 and PXD2 are not particularly limited, as represented by the X predecoder XPD1 in FIG. -C
MOS Nant gate circuits BNAI to BNA3 are provided, respectively. These 81 CMOS Nant gate circuits are
Although not particularly limited, as typified by the B1 CMOS Nant gate circuit BNAI, the basic configuration is a pair of output transistors T14 and T15 provided in a totem pole configuration between the ground potential and the power supply voltage of the circuit, and its input The above complementary internal address signals 10 to 2 are connected to the terminals.
or! The non-inverted or inverted signals 3 to 5 are respectively supplied in predetermined combinations.

Each Bi/CMO of X predecoder PXDI and PXD2
The S NAND game I circuit uses complementary internal address signals 10~
When the non-inverted and inverted signals of X2 or 13-15 are set to high level all at once in a corresponding combination, their output signals, that is, predecode signals X10-X17 or X20-X27 are alternatively set to low level.

External terminal A is connected to X address bar 7, XBI and XB2.
Three-bit address signals AO-A2 or A3-A5 are supplied via O-A2 or A3-A5, respectively. Further, an internal control signal VCL is supplied from a power supply voltage detection circuit VCL, which will be described later, and predetermined reference potentials VREI and VRE2 are supplied from a constant voltage generation circuit VRE.

Here, the internal control signal VCL is set to a low level in a normal state when the absolute value of the power supply voltage of the circuit exceeds, for example, 3.4 square meters, and is set to a high level in an abnormal state where the absolute value of the power supply voltage of the circuit does not reach the above level. Further, reference potentials VREI and VRE2 are formed by a constant voltage generating circuit VRE shown in FIG. 3, although not particularly limited, and are set to the same predetermined level.

Although the X address buffers XBI and XB2 are not particularly limited, as represented by the X address buffer X81 in FIG.
three current switch circuits C81 to C33 receiving 5;
Three pairs of level conversion circuits LCI and LC2 to L receive non-inverted and inverted output signals of these current switch circuits.
C5 and LC6, respectively.

Among these, the current switch circuits C3I to C33 are, although not particularly limited, as represented by the current switch circuit C3I, a pair of differential bipolar transistors T2 (
2nd transistor) and T3 (@1 transistor) are the basic configuration. Load resistors R1 and R are connected between the collectors of these differential transistors and the circuit ground potential.
2 (first load resistor), and between its commonly coupled emitter and the power supply voltage of the circuit is provided a transistor T4 which receives a predetermined constant voltage 1.5 V BE at its base.
(third transistor) and emitter load resistor R3 (second
A constant current source consisting of a load resistor) is provided, respectively. Further, an input emitter follower circuit whose emitter load is an N-channel MO3FETQ21 receiving a predetermined constant voltage 2VBE is provided at the front stage of the differential transistor, and an input emitter follower circuit whose emitter load is an N-channel MO3FETQ21 receiving the constant voltage 2V8E in the subsequent stage. A pair of output limiter follower circuits with Q23 and Q23 as emitter loads are provided.

A predetermined reference potential VBB is applied to the base of the transistor T3.
is supplied. As a result, the differential transistors T2 and T3, together with the surrounding circuit elements,
It acts as a current switch circuit with BB as the logic threshold.

On the other hand, the level conversion circuits LCI to LC6, as represented by the level conversion circuit LCI in FIG. , a CMOS type current mirror circuit provided in front of each of these output transistors. P channel Mo5FETQ
The gate of 1, the drain of N-channel Mo3FETQ24, and the 7-sence of P-channel Mo3FETQ2 are as follows:
They are commonly coupled as input nodes of the level conversion circuits LCI-LC6, and are supplied with non-inverted or inverted signals of the corresponding current switch circuits C3I-C33, respectively. Moreover, the output signal of each level conversion circuit is supplied to the corresponding . Although not particularly limited, between the output nodes of the level conversion circuits LCI to LC6 and the power supply voltage of the circuit, there is an N-channel pull-down M whose gate receives the internal control signal VCL.
O5FETs Q30 to Q35 are provided, respectively.

ECL level address signals AO-A2 and A supplied via external terminals AO-A2 and A3-A5
The levels of voltages 3 to A5 are determined by current switch circuits C81 to C33, which use the reference potential vea as a logic threshold.

Then, after being converted to the MOS level by the corresponding level conversion circuits LCI and LC2, LLC5 and LC6, the non-inverted internal address signals aO to a2 or a3 to a
5 or inverted internal address signal B Q-a2 or a3
~a5.

By the way, the power supply voltage detection circuit VCL which forms the internal control signal VCL and supplies it to the X address buffers XBI and XB2 is not particularly limited, but as shown in FIG. Resistor R4 (third load resistance) and transistor T9 provided in series between
(fourth transistor), Tl0 (fifth transistor), and resistor R5 (fourth load resistor). Among these, the base of the transistor T9 has the reference potential V
Bi+ is supplied to the base of the transistor TIO,
The constant voltage 1.5VBE is supplied. In this embodiment, resistors R4 and R5 constituting the power supply voltage detection circuit VCL are designed to have the same resistance values as resistors R2 and R3 constituting the current switch circuit C31 etc. in FIG. 1, respectively. Further, the transistors T9 and TIO are designed to have the same size as the transistors T3 and T4, respectively, and have the same electrical characteristics. As a result, the power supply voltage detection circuit VCL has the same operating characteristics as the current switch circuits C3I to CS3 of the X address buffers XBI and XB2 with respect to the power supply voltage of the circuit.

Although the collector potential of the transistor T9 is not particularly limited, the transistor Tll and the N-channel Mo3F
P via an emitter follower circuit consisting of ETQ36
It is transmitted to the gate of channel Mo3FETQ3. The source of this MO3FETQ3 is coupled to the ground potential of the circuit, and its drain is connected to the N-channel Mo5FETQ3.
N-channel Mo3 configured as a current mirror with B
It is coupled to the circuit power supply voltage via FET Q37.

The drain of MO3FETQ38 is coupled to the circuit's ground potential via a diode-shaped P-channel Mo3FETQ4, and its source is coupled to the circuit's power supply voltage.

From these facts, the absolute value of the circuit power supply voltage is, for example, 3
．． When the voltage exceeds 4V, the transistor T10 is turned on and acts as a constant current source together with the resistor R5. Therefore, the collector potential of the transistor T9 is set to a predetermined low level determined by the operating current obtained from the constant current source composed of the transistor TIO and the resistor R5 and the resistance value of the resistor R4, and the MO3FET Q3 is turned on.

Therefore, the MO3FET Q38 is turned on, and thereby the output signal of the power supply voltage detection circuit VCL, that is, the internal control signal VCL becomes low level. At this time, X
In the address buffers XBI and XB2, when the absolute value of the power supply voltage of the circuit exceeds, for example, 3°4V, the current switch circuits C3I to C33 function normally, and the internal control signal VCL is set to a low level, so that the pull-down M
Both O3FETs Q30 to Q35 are turned off.

As a result, the level conversion circuits LCI-LC6 also function normally, and the X address puffers XBI and Form soil 5.

On the other hand, when the absolute value of the power supply voltage of the circuit does not reach, for example, 3.4.times., when the power of the Bi-CMOS type RAM is first turned on or when the power supply is abnormal, the transistor TIO in the power supply voltage detection circuit VCL is turned off. Therefore, the collector potential of the transistor T9 becomes a high level such as the ground potential of the circuit, and the emitter potential of the transistor Tll becomes a high level such as VBH.
ETQ3 is almost in an off state. Therefore, MO3F
ETQ38 is almost turned off, and as a result, the output signal of the power supply voltage detection circuit VCL, that is, the internal control signal VC
L becomes a high level like the ground potential of the circuit. At this time, in the X address buffers XBI and XB2, since the absolute value of the circuit power supply voltage does not reach, for example, 3.4V, the transistors T4 of the current switch circuits C51 to C33
are turned off and cannot function normally, and the output signals of the level conversion circuits LCI-LC6, that is, the non-inverted internal address signals aO-a2 and a3-a5 and the inverted internal address signals aO-a2 and a3-a5 are simultaneously Try to reach the level. However, this Bi/CMO
In the S-type RAM, as mentioned above, the level conversion circuit LCI
Pull-down MOSFETs Q30-Q35 are respectively provided between the output terminal of ~LC6 and the power supply voltage of the circuit, and when the internal control signal VCL is set to high level, these pull-down MOSFETs Q30-Q35 are turned on all at once. Therefore, level conversion circuits LC1 to LC
6 output signals, that is, non-inverted internal address signals aO to a
2 and a3-a5 and inverted internal address signal aO-
a2 and a3 to a2 are all fixed at low level.

As a result, the operations of the X predecoders XPD1 and XPD2 are stabilized, and it is possible to prevent the word lines from being inadvertently brought into a fully selected state.

Next, the complementary data lines configuring the memory array MARY -
Do to D255 are not particularly limited, but as illustrated in FIG.
Paired load MO3FET QI 1 and Q14 and Q1
2 and Q13 to the circuit ground potential, and on the other hand the corresponding two pairs of switch MOSFETs Q58 and Q59 and Q15 of the column switch C5W.
and Q16.

Of the above two sets of load MO3FETs, the load MO3FETs QI 1 and Q14 provided on the outside are designed to have relatively small conductance, although not particularly limited, and their gates are fixedly coupled to the power supply voltage of the circuit. . In addition, another pair of MO3FETQ installed inside
I2 and Q13 are designed to have relatively large conductance, and have internal control signal WP at their gates.
G is commonly supplied. Here, the internal control signal WPG is normally set at a low level, although it is not particularly limited.
It is set to a high level when the CMOS type RAM is in a selected state in write mode.

When the internal control signal WPG is set to a low level due to the 13i-c MO3 type RAM being set to a non-selected state or selected state in the read mode, two sets of loads MO3FETQI 1 provided corresponding to each complementary data line are set. and Q14, Q12, and Q13 are simultaneously turned on. Therefore, a relatively high bias voltage is applied to the complementary data edges 0 to 255 forming the memory array MARY. This suppresses the incidence of soft errors caused by alpha rays and the like, and improves the reliability of the Bi-CMO5 type RAM.

On the other hand, when the Bi-CMOS type RAM is selected in the write mode and the internal control signal WPG is set to high level, the inner load MOSFETs Q12 and Q13 are turned off, and only the outer load MO3FETs QI 1 and Q14 are turned on. state. Therefore, the load impedance for the complementary data lines -Do to 255 of the memory array MARY is relatively thick (as a result, the write signal amplitude of each complementary data line is expanded, which causes the Bi/CMOS type O3M The speed and stability of the write operation can be increased.

The column switch C5W is not particularly limited, but as illustrated in FIG. 7, the column switch C5W includes N-channel type switches MO3FETQ58 and Q59 provided corresponding to the complementary data line Do-0255 of the memory array MARY and a P-channel type switch. Among them, the drains of N-channel type MO3FETQ5B and Q59 including MO3FETQ15 and Q16 are connected to the corresponding MO3FETQI5.
and Q16, and then to the non-inverting or inverting signal lines of the corresponding complementary data lines 10 to 255, respectively. These switches MO3FETQ5B
Although not particularly limited, the sources of Q59 and Q59 are commonly coupled to the non-inverted or inverted signal line of the corresponding write complementary common data lines CDWO-CDW3 every fourth set. The gates of the switches MO3FETQ58 and Q59 are commonly coupled in four sets, and each is supplied with a corresponding data line selection signal YO-Y63 from the Y address decoder YD. Similarly, the drains of the P-channel switch MO3FETs Q15 and Q16 are commonly coupled to the non-inverted or inverted signal lines of the corresponding read complementary common data lines -CDRO to -CDR3 every fourth set. These switches MO3
Similarly, the gates of the FETs are commonly connected in groups of four, and are each supplied with an inverted signal of the corresponding data line selection signal YO to Y63 by the inverter circuit N1.

Four sets of adjacent switches MO3 of column switch C3W
FETQ58 and Q59 and Q15 and Q16 are
By selectively setting the corresponding data line selection signals YO to Y63 at a high level, all four sets are selectively turned on all at once. As a result, four sets of corresponding complementary data lines of memory array MARY are connected to write complementary common data lines ΩDW0 to CDW3 and read complementary common data lines CD.
Selectively connected to RO to CDR3.

In FIG. 8, Y address decoder YD includes predecode signals YlO to Y17 and Y
By combining 20 to Y27, the corresponding data line selection signals YO to Y63 are alternatively set to high level.

Although the Y predecoders PYDI and PYD2 and the Y address buffers YBI and YB2 are not particularly limited,
The circuit configuration is substantially the same as that of the X predecoders PXD1 and PXD2 and the X address buffers XBI and XB2. Then, by incorporating 6 to All into the address signal supplied to the external terminal via 6 to All and decoding them by combining 3 bits each, the predecoded signals YIO-Y17 and Y20 to Y27 are
are formed alternatively.

The write complementary common data lines S-DWO to CDW3 are coupled to the output terminals of the corresponding unit circuits of the write amplifier WA, although not particularly limited thereto. The input terminal of each unit circuit of write amplifier WA is coupled to the output terminal of the corresponding unit circuit of data input buffer DIB. Furthermore, the output terminal of each unit circuit of the data input buffer DIB is coupled to the corresponding data input terminal DinO=Din3.

Each unit circuit of the light amplifier WA has an internal control signal wp.
is commonly supplied. Here, the internal control signal WP is B
When the i-CMOS type O3M is brought into a selected state in write mode, it is temporarily set to a high level at a predetermined timing.

On the other hand, the read complementary common data edge DRO-CDR3 is coupled to the input terminal of the corresponding unit circuit of the read amplifier RA. The output terminal of each unit circuit of read amplifier RA is data output buffer D.

It is coupled to the input terminal of the corresponding unit circuit of B.

Furthermore, the output terminals of each unit circuit of the data output buffer DOB are connected to the corresponding data output terminals DoutO to pout.
Combined with 3. An internal control signal OG is commonly supplied to each unit circuit of the data output buffer DOB. Here, the internal control signal OG is not particularly limited, but Bi/C
When the MOS type RAM is brought into a selected state in the read mode, it is set to a high level at a predetermined timing.

Each unit circuit of the write amplifier WA is selectively and simultaneously put into an operating state by setting the internal control signal WP to a high level when the B i-CMO5 type O5M is put into a selected state in write mode. . In this operating state, each unit circuit of the write amplifier WA uses the write data transmitted via the corresponding unit circuit of the data manual buffer DIB as a complementary write signal, and uses the write data transmitted via the corresponding unit circuit of the data manual buffer DIB as a complementary write signal, and sends the write data via the corresponding write complementary common data lines CDWO to -CDW3. Then, the data is written to the four selected memory cells of the memory array MARY.

Each unit circuit of the data input terminal 7DIB takes in the write data supplied through the data input terminals DinO to I)in3, and transmits it to the corresponding unit circuit to the write amplifier W.

On the other hand, each unit circuit of read amplifier RA is made of Bi/CMO
When the S-type RAM is selected in read mode,
Corresponding read complementary common data lines CDRO to CDR from four selected memory cells of memory array MARY
3. Amplify the readout signal outputted through 3. These read signals are transmitted to corresponding unit circuits of data output buffer DOB.

Each unit circuit of the data output buffer DOB is Bi-cM
When the O3 type O3M is selected in the read mode, the internal control signal OG is set to a high level, so that
Selectively activated.

In this operating state, the data output buffer D.

Each unit circuit of B sends out the read signal amplified by each unit circuit of read amplifier RA via the corresponding data output terminal DoutQ-Dout3.

The timing generation circuit TG forms the above-mentioned various internal control signals based on the chip selection signal C8 and the write enable signal WE, which are supplied as start-up control signals without any particular limitation, and generates each of the B i-CMO8 type O8M. supply to the circuit.

As described above, the Bi CMOS type RAM of this embodiment includes a memory array in which high resistance load static type memory cells whose basic configuration is MOSFET are arranged in a grid pattern, an ECL circuit, an 0M03 circuit, and a Bi CMOS type RAM.・C
It is equipped with a peripheral circuit formed by combining MOS composite circuits, and achieves both high integration of elements and high-speed operation.

Bt CMOS type RAM has a pair of differential transistors T
2 and T3, a current switch circuit C3 including a constant current source consisting of a transistor T4 and an emitter load resistor R3.
X address buffer XB, which includes level conversion circuits LCI to LC6 whose basic configuration is I to C53 and a pair of output transistors T7 and T8 in a totem pole configuration.
It is provided with X predecoders PXD1 and PXD2 and an X address decoder XD, each of which has a Bi/CMOS composite circuit as its basic configuration. In this embodiment, the Bi CMOS type RAM further has the same operating characteristics as the current switch circuits C3I to C53 with respect to the li power supply voltage, and the absolute value of the power supply voltage is, for example, 3.4
When the output signal, that is, the internal control signal VC
Power supply voltage detection circuit VCL that selectively sets L to low level
Equipped with Also, the X address buffers XBI and XB2
Between the output terminals of the level conversion circuits LCI to LC6 constituting the circuit and the power supply voltage of the circuit, there is a pull-down MOS FETQ30 whose gate receives the internal control signal VCL.
~Q35 are provided respectively. For this reason, Bi・CM
When the power supply voltage of the circuit is abnormally low when the OS-type RAM is first powered on or when a failure occurs, the current switch circuit C3I of the X address buffers XBI and XB2
Even if C33 cannot operate normally, the output of the level conversion circuit is
is fixed at low level by turning on. This stabilizes the operations of the X predecoders XPD1 and XPD2 and the X address decoder XD, and prevents the word lines from being inadvertently brought into a fully selected state.

As a result, B
Prevents abnormal increase in operating current of i-CMOS type RAM,
The power supply system can be protected.

As shown in the above embodiment, this invention can be applied to B1-C
By being applicable to semiconductor integrated circuit devices such as MOS type RAM, the following effects can be obtained. In other words, (11) A Bl/CMOS type RAM etc. equipped with an X address buffer including a current switch circuit and a level conversion circuit, etc.
A power supply voltage detection circuit having operating characteristics similar to the above current switch circuit with respect to the power supply voltage and selectively validating its output signal when the absolute value of the power supply voltage does not reach a predetermined value, and a power supply voltage detection circuit based on the above. By providing a pull-down or pull-up MO3FET that is selectively turned on according to the output signal of the voltage detection circuit and forcibly fixes the output signal of the level conversion circuit to a low level or a high level, the power supply voltage can be controlled at the time of power-on, etc. When the absolute value does not reach a predetermined value and the current switch circuit such as the above-mentioned X address buffer cannot operate normally, this can be accurately identified and the output signal of the level conversion circuit, that is, the This provides the effect of being able to fix the level.

(2) The fi1 term above stabilizes the operation of the X predecoder, the X address decoder, etc. provided after the X address buffer, and prevents the word lines of the memory array from being inadvertently brought into a fully selected state. This effect can be obtained.

(3) According to (11) and (2) above, Bl/CMOS type RA at the initial power-on or when the power supply voltage is unstable, etc.
It is possible to stabilize the operation of the M, etc., prevent an abnormal increase in operating current, and protect the power supply system.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, if the subsequent X predecoders PXD1 and PXD2 are configured by, for example, a B1-CMOS NOR gate circuit, the X
A pull-up MO3FET that is selectively turned on according to the internal control 8Ii signal VCL may be provided between the non-inverted and inverted output nodes of each bit of the address buffers XBI and XB2 and the ground potential of the circuit. When the number of bits of the X address signal becomes relatively large, the X address buffers XBI and XB2, etc. may include, for example, ECL type wiring logic. The absolute value of the power supply voltage that makes the output signal valid does not necessarily have to be 3.4V, and may be slightly larger than the absolute value of the power supply voltage that makes it impossible for the current switch circuits CSI to C36 to operate normally. The specific circuit configurations of the power supply voltage detection circuit VCL and the constant voltage generation circuit VRE shown in FIGS. 2 and 3 are not limited by this embodiment, and as shown in FIG. A constant current source provided between the commonly coupled emitters of the differential transistors T2 and T3 of C33 and the power supply voltage of the circuit has a predetermined constant voltage V applied to its gate, for example.
N-channel MO3FET Q40 receiving IE and resistor R
3, the power supply voltage detection circuit VCL
A constant current source provided between the emitter of the transistor T9 and the power supply voltage of the circuit is connected to the constant voltage VI at its gate.
N-channel MO3FET Q41 receiving E and resistor R5
In this case, MO3FETQ4
0 and Q41 must be formed with approximately the same size or the same resistance value. In FIG. 5, the X predecoder may predecode address signals AO-A5 by combining two pins at a time, for example. In this case, there are three sets of predecode signals, and the X address decoder in FIG. For example, each word line drive circuit of B1 is operated by three people.
- It is necessary to configure it with a CMOS NOR gate circuit. 7th
In the figure, the Bi-cMO3 type O3M can include, for example, a plurality of memory arrays provided corresponding to storage data. Further, the number of write complementary common data lines, read complementary common data lines, write amplifiers, and read amplifiers to be installed is also arbitrary.

In FIG. 8, the storage capacity, bit configuration, and address configuration of the Bi-cMO3 type RAM are arbitrary, and its block configuration can also take various embodiments.

The above explanation will mainly focus on the B1/CMOS type R, which is the field of application that was the background of the invention made by the present inventor.
Although the case where the present invention is applicable to AM has been described, the present invention is not limited thereto, and can also be applied to, for example, a Bi-CMOS type dynamic RAM or various logic integrated circuit devices whose basic configuration is a Bi-CMOS type RAM. The present invention is widely applicable to semiconductor integrated circuit devices including at least a current switch circuit and a level conversion circuit made of a Bi/CMOS composite circuit.

〔Effect of the invention〕

The effects obtained by typical inventions disclosed in this application are as follows. In other words, a Bi CMO equipped with an X address buffer including a current switch circuit and a level conversion circuit.
5 type O5M, etc., which has equivalent operating characteristics with respect to the power supply voltage as the above current switch circuit, and whose output signal is selectively enabled when the absolute value of the power supply voltage does not reach a predetermined value. By providing a power supply voltage detection circuit and a pull-down or pull amplifier MO3FET that is selectively turned on according to the output signal of the power supply voltage detection circuit and forcibly fixes the output signal of the level conversion circuit to a low level or a high level, the power supply voltage can be reduced. It is possible to accurately identify that the absolute value of the power supply voltage does not reach a predetermined value at the time of power-on, etc., and forcibly fix the output signal of the level conversion circuit to a low level or a high level. This stabilizes the operation of the X address decoder and the like provided in the subsequent stage, and prevents the word lines of the memory array from being inadvertently brought into a fully selected state. As a result, it is possible to stabilize the operation of the Bi-cMO3 type RAM, etc. during the initial power-up or when the power supply voltage is unstable, prevent abnormal increases in operating current, and protect the power supply system.

[Brief explanation of drawings]

Figure 1 shows a B i-CMO8 type R to which this invention is applied.
A circuit diagram showing an example of an AM X address buffer, FIG. 2 is a Bi-CMO8 type RA to which this invention is applied.
FIG. 3 is a circuit diagram showing an embodiment of the M power supply voltage detection circuit.
FIG. 4 is a circuit diagram showing an embodiment of a constant voltage generating circuit for M, and is a Bi-cM to which the present invention is applied. FIG. 5 is a circuit diagram showing another embodiment of the X address buffer and i4 voltage detection circuit of the S-type RAM, and FIG. The circuit diagram shown in FIG. 6 is a Bi-CMO8 type RA to which this invention is applied.
FIG. 7 is a circuit diagram showing an embodiment of the M X address decoder. FIG. 7 is a Bi-CM to which the present invention is applied. A circuit diagram showing an example of an S-type RAM memory array, FIG. 8 is a Bi-CMO8 type RA to which the present invention is applied.
FIG. 9, a block diagram showing an embodiment of M, is a Bi/CMOS type RA developed by the inventors of the present invention prior to this invention.
FIG. 3 is a circuit diagram showing an example of an M X address buffer. MARY...Memory array, XD...X address decoder, PXD 1 to PXD2...X predecoder,
XBI~XB2...X address buffer, C5W...
・Column switch, YD...Y address decoder, P
YDI~PYD2...Y predecoder, YBI~YB
2...Y address buffer, WA...write amplifier, RA...read amplifier, DIB...data input buffer, DOB...data output buffer, VCL...
・・Power supply voltage detection circuit, VRE・−・Constant voltage generation circuit 11
, TG...timing generation circuit. C3I to C53...Current switch circuit, LC1 to LC
6...Level conversion circuit, BNAI to BNA3...B
1-CMOS Nant gate circuit, BNOI ~ BNO3
・-・Bi・CMOS/Agate circuit, N1... Inverter circuit. MC...Memory cell, Q1-Q16...P-channel MO3FET, Q21-Q59...N-channel M
O3FET, Tl-T17...NPN type bipolar transistor, R1-R7...resistance.

Claims (1)

[Claims] 1. A current switch circuit including a differential transistor, a constant current source that provides a predetermined operating current to the differential transistor, and an emitter follower circuit that transmits the collector potential of the differential transistor, and the current switch A level conversion circuit that converts the output signal of the circuit to a MOS level, and a level conversion circuit that has the same operating characteristics as the current switch circuit with respect to the power supply voltage and that converts the output signal when the absolute value of the power supply voltage reaches a predetermined value. a power supply voltage detection circuit that is selectively enabled; and a pull-down or pull-down that is selectively turned on when the output signal of the power supply voltage detection circuit is not enabled and fixes the output signal of the level conversion circuit to a low level or a high level. A semiconductor integrated circuit device comprising: an up MOSFET. 2. The above semiconductor integrated circuit device is a bipolar CMOS
Claim 1, wherein the current switch circuit and the level conversion circuit are included in an X address buffer, an X predecoder, or an X address decoder of the Bi/CMOS type RAM. The semiconductor integrated circuit device according to item 1. 3. The differential transistor includes a first transistor whose base receives a predetermined reference potential and whose collector is coupled to a first power supply voltage via a first load resistor; and a second transistor of a differential type, the constant current source receiving a predetermined constant voltage at its base and having its collector commonly coupled to the emitters of the first and second bipolar transistors. and a second load resistor provided between the emitter of the third transistor and a second power supply voltage, the power supply voltage detection circuit having a base thereof a fourth transistor that receives the reference potential and is formed to have the same size as the first transistor; a fourth transistor that is provided between the collector of the fourth transistor and the first power supply voltage and that is connected to the first load resistor; a third load resistor having the same resistance value; and a third load resistor having a base receiving the constant voltage and having a collector coupled to the emitter of the fourth transistor and having the same size as the third transistor. and a fourth load resistor provided between the emitter of the fifth transistor and a second power supply voltage and having the same resistance value as the second load resistor. A semiconductor integrated circuit device according to claim 1 or 2.