JPH0322421A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the short channel effect of a MOS transistor by forming source-drain by diffusing an impurity in polysilicon and reducing junction depth. CONSTITUTION:A first conductive film is grown onto a semiconductor substrate 1, and a first insulating film 3 is grown to the upper section of the first conductive film. The first conductive film is left on source 10-drain 11 regions through patterning. A second insulating film 5 is grown, and left only on the sidewalls of the first conductive films through anisotropic dry etching. A gate oxide film 7 is formed through thermal oxidation, and a second conductive film is grown. The second conductor is left only in the clearance of the first conductive films through anisotropic dry etching. Ions are implanted while using the first and second conductors as masks. An impurity in the first conductive films is diffused into the semiconductor substrate.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

FIGS. 4(a) to 4(d) are cross-sectional views shown in the order of steps for explaining a method of manufacturing a MOS transistor according to the prior art.

FIG. 4(a) shows the state where polysilicon 8 is grown after forming a field oxide film for transistor isolation on P-type silicon substrate 1.

FIG. 4(b) shows the area where PR (photoresist) 4 is formed for the gate type.

FIG. 4C shows the gate electrode formed by anisotropic dry etching of polysilicon 8.

FIG. 4(d) shows the state in which arsenic ions were implanted using the gate electrode and field oxide film as masks, and then the source and drain were formed by heat treatment. FIG. 5 is a plan view of FIG. 4(i).

[Problem to be solved by the invention]

The conventional MOS transistor described above suffers from adverse effects such as a short channel effect such as a decrease in threshold voltage when the gate length is reduced to sub-microns.

Therefore, it is necessary to reduce the gate length and the junction depth of the source and drain at the same time based on the proportional reduction law that reduces the gate length and the junction depth of the source and train at the same ratio.

However, in order to reduce the junction depth, it is necessary to reduce the energy of arsenic ion implantation as shown in FIG. Furthermore, if the junction depth becomes smaller, there will be a problem of penetration of the wiring aluminum into the substrate when forming the contact electrode.

As described above, if the gate length is made finer while maintaining the conventional structure, various obstacles will occur, which will pose problems in achieving higher integration and higher speed of MOSLSI.

[Means to solve the problem]

In the method for manufacturing a semiconductor device of the present invention, a first
A step of growing a first insulating film on top of the first insulating film, and patterning the source. A step of leaving the first conductive film on the drain region, a step of growing a second insulating film and leaving only the sidewalls of the first conductive film by anisotropic dry etching, and a step of removing the gate oxide film by thermal oxidation. a step of growing a second conductive film and leaving the second conductor only in the gap of the first conductive film by anisotropic dry etching; and a step of forming the first and second conductors. The method includes a step of implanting ions using a mask as a mask, and a step of diffusing impurities in the first conductive film into the semiconductor substrate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(i) are sectional views shown in order of steps for explaining a first embodiment of the present invention.

The following describes the NMOS} transistor, but P
The same precautions apply to MOS transistors.

Figure 1(a) shows a phosphorus-doped n+ polysilicon 2 on a P-type silicon substrate 1 at a temperature of 0.4 μm at around 700°C.
Then, a CVD oxide film is grown to a thickness of 0.3 μm. Here, the phosphorus content in n+ polysilicon is 1 0
The resistance is made sufficiently small by setting it to about "cm-". Note that there is almost no diffusion of phosphorus into the silicon substrate at this temperature.

FIG. 1(b) shows a photoresist 4 formed by patterning. The PR spacing is 0.5 μm.

Next, CVD S:023 and n+ polysilicon are anisotropically dry etched separately. Here, when the n+ polysilicon 2 is etched with CF4, since it is doped with phosphorus, the etching rate is high and the silicon substrate is hardly etched. This is shown in FIG. 1(C).

Figure 1(d) shows CVD S:025 grown to about 500 people.

Next, S:02 is anisotropically dry etched to expose the silicon substrate. At this time, C■D S:023
Although it is etched to some extent, about 0.2 μm remains. Furthermore, S:02 remains on the side wall of the n'' polysilicon 2, as shown in FIG. 1(e).

FIG. 1(f) shows the silicon substrate oxidized and the gate oxide film 7 of about 150 people formed.

Next, 0.6 μm thick phosphorus-doped n+ polysilicon 8
grow to a certain extent. This is shown in FIG. 1(g).

Next, n1 polysilicon 8 is removed by anisotropic dry etching, and n+ polysilicon 8 is removed by anisotropic dry etching so that it remains only on the side walls of n+ polysilicon 2. At this time, since the interval between the polysilicon 2 is as narrow as 0.5 μm, the n+ polysilicon 8 between them is not removed, and the gate 9 is left intact. This is shown in FIG. 1(h).

Next, in order to form the anti-inversion P+ layer 12 for preventing the formation of parasitic MOS transistors, ion implantation of 56 ion is performed at 40 keV IXIO"cm-2. When heat-treated for 1 minute, the phosphorus contained in 2 diffuses into the n+ polysilicon, and the source 10,
The drain 11 is transformed into a MOS transistor.

The gate length at this time is approximately 0.4 μm. This is shown in FIG. 1(i).

In the case of a PMOS transistor, n+ polysilicon 2 and 8 are made of P+ polysilicon. In addition, reversal prevention P+
Make it polysilicon. Further, the anti-inversion P+ layer 12 is n+
become layers. Note that the CVD oxide films 3 and 5 may be other insulating films such as a nitride film. In addition, n+ polysilicon is WSi containing phosphorus. (tungsten silicide) etc. may also be used.

FIG. 2 is a plan view of FIG. 1(i).

N+ polysilicon 18 is provided to form a contact 13 on the gate. This n+ polysilicon prevents direct conduction between the gate and the substrate. Note that this n+ polysilicon 18 is patterned at the same time as the source and drain as shown in FIG. 1(b).

Further, since an n+ layer is formed below this n+ polysilicon 18, a diode is formed between the n''-P sub-subs, which also serves to protect the gate from static electricity.

FIGS. 3(a) to 3(i) are cross-sectional views showing the steps of the second embodiment of the present invention.

In the first embodiment, polysilicon 2 is used in FIG. 1(a).
Although phosphorus was doped before the polysilicon 2 was grown, in this embodiment, after the polysilicon 2 is grown, arsenic ions are implanted. Note that since arsenic has a small diffusion coefficient, it is difficult to diffuse through heat treatment, so the junction depth between the source and drain can be reduced. This is shown in FIG. 3(a). The rest is the same as in the first embodiment.

〔Effect of the invention〕

As described above, the present invention has the effect of suppressing the short channel effect of a MOS transistor by reducing the junction depth since the source and drain can be shaped by diffusion of impurities in polysilicon.

Furthermore, since the gate shape is done in self-line, there is no need for an additional photoresist process. Furthermore, although conventionally a field oxide film was required for transistor isolation, the present invention requires only ion implantation for preventing inversion, thereby shortening the process.

In-contact, 16...source, 17...drain, 18...n+ polysilicon.

Claims (1)

[Claims] A step of growing a first conductive film on a semiconductor substrate and growing a first insulating film on top of the first conductive film, a step of leaving the first conductive film on regions that will become sources and drains by patterning, and a second step. a step of growing an insulating film and leaving only the sidewalls of the first conductive film by anisotropic dry etching, and a step of forming a gate oxide film by thermal oxidation;
a step of growing a second conductive film and leaving the second conductor only in the gap between the first conductive films by anisotropic dry etching; A method for manufacturing a semiconductor device, comprising the steps of: implanting an impurity in the first conductive film; and diffusing impurities in the first conductive film into the semiconductor substrate.