JPH03224264A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, for example, a DRAM (Dynamic Random Acc.
The present invention relates to a technology that is effective when applied to improve the yield and reliability of ESSMemory.

C Conventional technology] 4 megabits [Mbit] or 16 megabits [Mbit]
The memory cells of large-capacity DRAMs such as BIT) adopt a so-called stacked structure in which the information storage capacitor is placed above the memory cell selection MISFET in order to ensure the amount of charge stored in the information storage capacitor. ing. The stacked structure information storage capacitor is usually composed of a pair of electrodes (a lower electrode and an upper electrode) made of low-resistance polysilicon and a dielectric film provided between these electrodes. A part of M is for memory cell selection.
It is connected to one semiconductor region of the ISFET. In order to form the information storage capacitive element of the stacked structure made of polysilicon, first, the MISFE for memory cell selection is
After a polysilicon film for a lower electrode is deposited on the entire surface of the semiconductor substrate on which the T is formed, impurities are introduced into the polysilicon film. The purpose of introducing the impurity is to reduce the resistance value of the polysilicon film and ensure a sufficient amount of charge stored in the information storage capacitive element. At this time, by diffusing a part of the impurity introduced into the polysilicon film into one semiconductor region of the memory cell selection MISFET below the polysilicon film, a part of the semiconductor region is doped with high impurity concentration semiconductor. A step of forming the regions in a self-aligned manner is involved. The reason why a semiconductor region with a high impurity concentration is formed in a part of the semiconductor region is to reduce leakage current of the memory cell. Next, e) After processing the polyrecon film into a predetermined shape using IJ lithography technology and anisotropic etching technology and forming the lower electrode of the information storage capacitive element, a dielectric film is formed on the entire surface of the substrate. accumulate. The dielectric film is formed, for example, in a two-layer structure in which a 513N4 film and a 5IO2 film are sequentially laminated.

Next, a polysilicon film for the upper electrode is deposited on the entire surface of the substrate, and impurities are introduced to reduce the resistance value, and then anisotropic etching is performed on each of the polysilicon film and the dielectric film. By forming a dielectric film and an upper electrode of the information storage capacitive element, an information storage capacitive element having a stacked structure is completed. A method for manufacturing the information storage capacitive element having a stacked structure consisting of a pair of electrodes made of low resistance polysilicon and a dielectric film is described in, for example, Japanese Patent Application No. 1-169137. There is.

[Problem to be solved by the invention]

According to studies by the present inventors, there are the following problems in the manufacturing process of a memory cell equipped with a stacked-structure information storage capacitor element having a pair of electrodes made of low-resistance polysilicon.

As described above, in the step of forming the stacked structure information storage capacitor element, after depositing a polysilicon film for the lower electrode on the entire surface of the semiconductor substrate, impurities are introduced into the polysilicon film to form the polysilicon film. In addition to reducing the resistance value of the film, a part of the impurity introduced into the polysilicon film is diffused into one semiconductor region of the memory cell selection MISFET below the polysilicon film to form a semiconductor region with a high impurity concentration. Form in a self-consistent manner. However, DRAM with a large capacity such as 4 megabits (Mbit) or 16 megabits (Mbit)
In order to compensate for the decrease in the amount of stored charge due to the reduction in the lateral area of the information storage capacitive element due to miniaturization, the surface area is increased by increasing the thickness of the polysilicon film for the electrode. It is difficult to optimize the respective impurity concentrations of the semiconductor regions of one of the information storage capacitive element and the memory cell selection MISFET. In other words, in order to ensure a sufficient amount of stored charge in the information storage capacitor and reduce the soft error rate of the memory cell, it is necessary to increase the impurity concentration of the electrode polysilicon film to reduce the depletion rate of the storage capacitor. However, if the amount of impurities diffused from the polysilicon film into one semiconductor region of the memory cell selection MISFET is increased, the depth of the main semiconductor region in the substrate direction becomes too deep and the memory cell selection Problems such as deterioration of the characteristics of the selection MISFET arise. On the other hand, if the amount of impurities diffused from the polysilicon film into one semiconductor region of the memory cell selection MISFET is suppressed, a semiconductor region with a high impurity concentration will not be sufficiently formed, and leakage current will increase, resulting in poor refresh characteristics of the memory cell. Problems such as a decrease in

The present invention has been made in view of the above-mentioned problems, and its purpose is to use a part of the impurity introduced into the polysilicon film constituting the lower electrode of a stacked information storage capacitor element for memory cell selection. In a manufacturing method in which a semiconductor region with a high impurity concentration is formed in a part of the semiconductor region in a self-aligned manner by diffusion into one semiconductor region of a MISFET,
The above information storage capacitive element and memory cell selection M, I
An object of the present invention is to provide a technique that can optimize the impurity concentration of each semiconductor region of an SFET.

Another object of the present invention is to diffuse a portion of impurities introduced into a polysilicon film deposited on a semiconductor substrate into the semiconductor substrate to form a semiconductor region with a high impurity concentration in a portion of the semiconductor substrate in a self-aligned manner. An object of the present invention is to provide a technique that can optimize the impurity concentrations of the polysilicon film and the semiconductor region in a manufacturing method.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

One invention of the present application is a method for manufacturing a semiconductor integrated circuit device equipped with a DRAM having a memory cell constituted by a series circuit of an M+5 FET for memory cell selection and an information storage capacitor element of a stacked structure. By introducing impurities into the polysilicon film constituting the lower electrode of the information storage capacitive element, the resistance value of the polysilicon film is reduced, and a part of the impurity introduced into the polysilicon film is When forming a semiconductor region with a high impurity concentration in a part of the semiconductor region in a self-aligned manner by diffusing it into one semiconductor region of the memory cell selection MISFET below the film, the polysilicon film, A plurality of types of impurities having different diffusion coefficients are introduced into the semiconductor substrate and the interface region thereof.

[Effect]

According to the above-mentioned means, multiple types of impurities having different diffusion coefficients in the polysilicon film, the semiconductor substrate, and the interface region thereof are introduced into the polysilicon film constituting the lower electrode of the stacked-structured information storage capacitor. By doing so, the capacitive element for information storage and MIS for memory cell selection are
It becomes easy to control the impurity concentration of each semiconductor region of the FET. In other words, for example, impurity species with a small diffusion coefficient in the main interface region tend to remain in the polysilicon film, and can mainly reduce the resistance value of the polysilicon film and increase its impurity concentration, thereby reducing the depletion of storage capacitance. Accordingly, the amount of charge stored in the information storage capacitive element having a stacked structure can be increased. In addition, for example, impurity species with a large diffusion coefficient in the polysilicon film and in the interface region tend to diffuse into one semiconductor region of the memory cell selection MISFET under the polysilicon film, and mainly in the semiconductor region. Since it acts to increase the impurity concentration of , leakage current of the memory cell can be reduced.

Hereinafter, the present invention will be explained in detail with reference to Examples. Incidentally, in the purpose of explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

〔Example〕

A method for manufacturing a semiconductor integrated circuit device, which is an embodiment of the present invention, is applied to a method for manufacturing a DRAM having a memory cell configured of a series circuit of a memory cell selection MISFET Qs and a stacked information storage capacitor C. It is what was done. The above DRAM is, for example, 16 megabits) (M
It has a capacity of bit:l and a minimum processing size of 0.5 [μm].
] is manufactured according to the so-called 0.5 [μm] design rule.

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate (wafer) 1 at an intermediate stage in the manufacturing process of an upper magnetic DRAM. A p-type well region 2 is provided on the main surface of the memory cell formation region of the substrate 1 made of p-type silicon single crystal. The p-type well region 2 has a thickness of, for example, 10'' to 10
” (Impurity concentration (D
B (or BF,) DO~70 CK e V]
After introducing ion implantation method with energy of about
It is formed by heat-treating in an atmosphere at a high temperature of about 1100 to 1300 (t).

The main surface of the p-type well region 2 has a thickness of 400 to 600 (nm).
A field insulating film 3 for element isolation having a film thickness of about :] is provided. The field insulating film 3 is 5iC
h, and is formed by, for example, a selective oxidation method (LOCO3 method). A p-type channel stopper region 4 is provided below the field insulating film 3. The upper Ep type channel stopper region 4 is formed by introducing BF2 with an impurity concentration of about IQ'' (atoms/ci) into the main surface of the p type well region 2, for example, by ion implantation with an energy of about 50 to 70 (KeV). After that, the substrate 1 is heated to 1050~11
It is formed by heat treatment at a high temperature of about 50 [°C]. Through the above heat treatment, the impurity introduced into the main surface of the p-type well region 2 is stretched and diffused, and the field insulating film 3
The p-type channel stopper region 4 is formed by substantially the same manufacturing process as in the formation of the p-type channel stopper region 4. A gate insulating film 5 of a memory cell selection MISFET Qs is provided on the main surface of the active region of the p-type well region 2 surrounded by the field insulating film 3. The gate insulating film 5
is formed by steam oxidizing the substrate 1 at a high temperature of, for example, 800 to 1000 [°C], and
It has a film thickness of about [nm]. On each of the upper gate insulating film 5 and the field insulating film 3, there is a MISFET Qs for memory cell selection which also serves as a word line (WL).
A gate electrode 6 is provided. The gate electrode 6 is made of a polysilicon film having a thickness of, for example, about 200 to 300 [nm]. An n-type impurity (P or As) is introduced into the upper polysilicon film to reduce the resistance value. To form the gate electrode 6, for example, a polysilicon film is first deposited on the entire surface of the substrate 1 by the CVD method, and then a polysilicon film is deposited on the polysilicon film by a thermal diffusion method.
After introducing type impurities (P or As), an interlayer insulating film 7 having a temperature of about 250 to 350 [nm][deg.]C] is deposited over the entire surface of the polysilicon film. The interlayer insulating film 7 is formed, for example, by a CVD method using inorganic silane gas and nitrogen oxide gas as source gases. Next, the interlayer insulating film 7 and the polysilicon film are each anisotropically etched using a photoresist mask (not shown). Note that the gate electrode 6 is made of a high melting point metal (Mo,
Ti, Ta, W) films and high melting point metal silicide (MoS
i, , TiSi2. It may be composed of a single layer of TaSi□, WSi□) film, or it may be composed of a composite film in which the above-mentioned high melting point metal film or high melting point metal silicide film is laminated on a polysilicon film.

Next, using the field insulating film 3, gate electrode 6, and interlayer insulating film 7 thereon as an impurity introduction mask, n-type impurities are introduced into the main surface of the active region. The n-type impurity is introduced into the gate electrode 6 in a self-aligned manner.

The n-type impurity is, for example, l Q13atoms/ca
Using P (or As) with an impurity concentration of about 30
It is introduced by an ion implantation method with an energy of about 50 CKeV:l. Subsequently, the substrate 1 is heat-treated at a high temperature of, for example, 900 to 1000 [°C] to stretch and diffuse the n-type impurity, thereby forming an n-type semiconductor of the memory cell selection MISFETQs as shown in FIG. Region 8 is formed.

Next, as shown in FIG. 3, sidewall spacers 9 are formed on each sidewall of the gate electrode 6 and the interlayer insulating film 7 thereon. Above side wall spacer 9
For example, after depositing a 5102 film using inorganic silane gas and nitrogen oxide gas as source gases by CVD method, R
It is formed by applying anisotropic etching such as IE. Next, an interlayer insulating film 10 is deposited on the entire surface of the substrate 1.

The interlayer insulating film 10 is used as an etching stopper layer when processing the electrode of the information storage capacitive element C of the memory cell, which will be described later. It is formed to electrically isolate the gate electrode 6. The interlayer insulating film 10 is made of 5102 oxide film deposited by the CVD method using, for example, inorganic silane gas and nitrogen oxide gas as source gases.
It is composed of a film and has a film thickness of about 130 to 180 (nun). Next, the interlayer insulating film 10 on one n-type semiconductor region (the side to which the lower electrode of the information storage capacitive element C is connected) 8 of the memory cell selection MISFET Qs is removed, and a connection hole 11 is formed.

Next, as shown in FIG. 4, a polysilicon film 12A for the lower electrode of the information storage capacitive element C is deposited on the entire surface of the substrate 1. A part of the polysilicon film 12A passes through the connection hole 11 and is connected to the memory cell selection M I S F E
It is connected to one n-type semiconductor region 8 of TQs. The upper polysilicon film 12A is deposited by, for example, a CVD method, and has a thickness of 200 nm or more in order to ensure a sufficient surface area for the lower electrode of the information storage capacitive element C. After the polysilicon film 12A is deposited, n-type impurities are introduced into the polysilicon film 12A. The introduction of the n-type impurity reduces the resistance value of the polysilicon film 12A, and also allows a part of the n-type impurity introduced into the polysilicon film 12A to pass through the connection hole 11 to the MISF for memory cell selection.
This is done to diffuse into one n-type semiconductor region 8 of ETQs. In this embodiment, the polysilicon film 12A has n
In introducing the type impurities, two types of n-type impurities (As and P) having different diffusion coefficients are used. That is, for example, As with an impurity concentration of about 1016 Catoms/cffl:l is introduced by ion implantation with an energy of about 80 CKeV:l, and then 1015 to 5X101
5 (P with an impurity concentration of about atoms/cafl is 80
It is introduced by an ion implantation method with an energy of approximately (KeV).

The above two types of n-type impurities are introduced through a thin thermal oxide film (not shown) of about 10 to 30 (nm) formed on the surface of the polysilicon film 12A, and immediately after that, for example, 90 nm is introduced.
The substrate 1 is heat-treated at a high temperature of about 0 Ctl for about 10 minutes to perform stretching and diffusion.

Note that P may be introduced into the polysilicon film 12A using a thermal diffusion method. As a result, a part of the n-type impurity is diffused into the n-type semiconductor region 8 of the memory cell selection MISFETQs, and an n°-type semiconductor region 13 with a high impurity concentration is formed in the negative part in a self-aligned manner. Ru. At this time, As has a relatively small diffusion coefficient in the interface region between the polysilicon film 12A and the substrate 1.
Since it tends to remain in the polysilicon film 12A and is occluded in the polysilicon film 12A, it mainly contributes to reducing the resistance value and preventing the storage capacitance from decreasing. Since relatively large P easily diffuses into the n-type semiconductor region 8, it mainly contributes to the formation of the n-type semiconductor region 13 with a high impurity concentration.

Next, the polysilicon film 12A is processed into a predetermined shape using photolithography and anisotropic etching to form the lower electrode 12 of the information storage capacitive element C as shown in FIG.

Next, for example, a 513N4 film, a 5102
A dielectric film 14 having a two-layer structure in which films are sequentially laminated is deposited.

The film thickness of the dielectric film 14 is determined by the effective oxide film thickness (tox e
7 (nm) or less in terms of rt).

Next, a polysilicon film for the upper electrode of the information storage capacitive element C is deposited on the dielectric film 14, and an n-type impurity, such as P, is introduced into the polysilicon film by thermal diffusion to increase its resistance. After reducing the value, the polysilicon film and the dielectric film 14 are sequentially anisotropically etched to form the dielectric film 14 and the upper electrode 15 of the information storage capacitive element C as shown in FIG. form. As a result, an information storage capacitive element C having a stacked structure is completed, and D
The RAM memory cell is completed.

In this way, according to the DRAM manufacturing method of this embodiment,
By introducing two types of n-type impurities (As and P) with different diffusion coefficients into the polysilicon film 12A and utilizing the difference in the diffusion coefficients of the two types of n-type impurities, the above-mentioned information storage capacity can be increased. The impurity concentrations of the element C and the n-type semiconductor region 13 can be optimized. This results in
Since a sufficient amount of accumulated charge in the information storage capacitive element C is ensured, the soft error rate of the memory cell is reduced. Also p
Since the memory cell selection MISFET Qs having the n° type semiconductor region 13 with good n-junction characteristics is formed, the leakage current of the memory cell is reduced and the refresh characteristics of the DRAM are improved.

As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.

In the above embodiment, a case was described in which the present invention is applied to a method for manufacturing a DRAM having a memory cell configured of a series circuit of a memory cell selection MrSFETQs and a stacked information storage capacitor C. Impurities are introduced into the polysilicon film deposited on the semiconductor substrate to reduce its resistance value, and a portion of the impurity is diffused into the semiconductor substrate to form a semiconductor region with a high impurity concentration in a portion of the semiconductor substrate. The present invention can be widely applied to a method of manufacturing a semiconductor integrated circuit device including a step of forming a self-aligned circuit. That is, by introducing two types of impurities with different diffusion coefficients into the polysilicon film and utilizing the difference in the diffusion coefficients of the two types of impurities, the respective impurity concentrations of the polysilicon film and the semiconductor region can be adjusted. Since the depth of the semiconductor region can be optimized, it is possible to improve the yield and reliability of semiconductor integrated circuit devices.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

By introducing impurities into the polysilicon film constituting the lower electrode of the information storage capacitive element having a stacked structure, the resistance value of the upper polysilicon film is reduced, and the impurity introduced into the polysilicon film is A part of the MIS for memory cell selection under the polysilicon film
MIS for memory cell selection, including a step of forming a semiconductor region with a high impurity concentration in a part of the semiconductor region in a self-aligned manner by diffusing one semiconductor region of the FET.
According to the present invention, in a method for manufacturing a memory cell configured with a series circuit of an FET and a stacked information storage capacitor element, a plurality of types of impurities having different diffusion coefficients are used to introduce impurities into the polysilicon film. For example, it is possible to optimize the impurity concentration of each of the high impurity concentration semiconductor regions formed in a part of the semiconductor region of one of the information storage capacitor element and the memory cell selection MISFET. It is possible to improve the yield and reliability of a semiconductor integrated circuit device having the present invention.

[Brief explanation of drawings]

1 to 6 are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. l...Semiconductor substrate, 2...P-type well region, 3...
-Field insulating film, 4...p-type channel stopper region, 5...gate insulating film, 6...gate electrode (word line WL), 7.10...interlayer insulating film, 8...n
--shaped semiconductor region, 9...side wall spacer, 1
1・φ・Connection hole, 12・・′・Lower electrode, 12A・・
Polysilicon film, 13... n-type semiconductor region, 14.
...Dielectric film, 5. Upper electrode.

Claims (1)

[Claims] 1. The resistance value of the polysilicon film is reduced by introducing impurities into the polysilicon film deposited on the semiconductor substrate, and a part of the impurities introduced into the polysilicon film is reduced. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a semiconductor region with a high impurity concentration in a part of the semiconductor substrate in a self-aligned manner by diffusing the polysilicon film into the semiconductor substrate below the polysilicon film. 1. A method for manufacturing a semiconductor integrated circuit device, comprising introducing into a silicon film a plurality of types of impurities having different diffusion coefficients in the polysilicon film, the semiconductor substrate, and an interface region therebetween. 2. By introducing an impurity into the polysilicon film constituting the lower electrode of the information storage capacitive element having a stacked structure, the resistance value of the polysilicon film is reduced, and the impurity introduced into the polysilicon film is reduced. A part of the memory cell selection MIS under the polysilicon film
MIS for memory cell selection, including a step of forming a semiconductor region with a high impurity concentration in a part of the semiconductor region in a self-aligned manner by diffusing it into one semiconductor region of the FET.
A method for manufacturing a semiconductor integrated circuit device having a memory cell constituted by a series circuit of an FET and a stacked information storage capacitive element, the method comprising: forming a polysilicon film on the polysilicon film, the semiconductor substrate, and an interface thereof; 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising introducing a plurality of types of impurities having different diffusion coefficients in each region.