JPH03224326A - Pll circuit for fm stereophonic demodulation - Google Patents

Abstract

PURPOSE:To stably perform stereophonic demodulation by passing a subcarrier signal component receiving the influence of frequency fluctuation obtained by a PLL circuit through a PLL circuit with low responsiveness as a PLL in which a crystal oscillator is used as an oscillator. CONSTITUTION:Since a CR type oscillation circuit is used in a VCO 23 comprising the PLL circuit 2, the subcarrier signal component receiving the influence of the frequency fluctuation is outputted from a frequency divider 3. To eliminate the influence of the frequency fluctuation, the PLL circuit 5 using the crystal oscillator is provided at the output side of the frequency divider 3. A phase comparator 51 performs the phase comparison of the frequency division output of the frequency divider 3 with an oscillation signal from the crystal oscillator 52, and sends out a phase difference signal to a low-pass filter 53. The low-pass filter 53 takes out the constant area component of the phase difference signal sent from the phase comparator 51, and supplies it to an oscillation controller 52 as the oscillation frequency control signal of the oscillation controller 52.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a PLL circuit for FM stereo demodulation, and more particularly to a PLL circuit for FM stereo demodulation for generating subcarriers that reduces the influence of frequency fluctuations (sickness).

(Prior Art) A circuit that detects a 19 KHz pilot signal from an FM composite signal received by an FM stereo receiver and generates a subcarrier signal for FM stereo demodulation based on the detected pilot signal is a PLL circuit. It is configured.

FIG. 3 shows a circuit illustrating an example thereof. FM
From the FM composite signal received by the stereo receiver, a pilot signal with a frequency near 19 KHz is detected by a pilot signal detection circuit 1 and inputted to a PLL circuit 2.

PLL circuit B2 is a circuit for capturing a 38 KHz subcarrier signal component using the signal supplied from the pilot signal detection circuit 1, and includes a phase comparator 21, a frequency divider 22,
It is composed of a VCO (voltage controlled oscillator) 23 having a CR type oscillation circuit configuration and a low pass filter (LP filter) 24.

A frequency signal of 38xn (Kl-1z>) is generated from the VC023, and the frequency is divided by 1/''2n in the frequency divider 22.The phase comparator 21 separates the signal from the pilot signal detection circuit 1 and the The phase difference with the output signal of the frequency divider 22 is determined and sent to the low-pass filter 24.

The low-pass filter 24 extracts the low-frequency component of the phase difference signal from the phase comparator 21 and supplies it to the VCO 23 as an open/close signal of the oscillation frequency of the VC023.

In this way, the oscillation frequency of the VCO 23 is changed by the phase comparator 21.
The phase difference signal is controlled to be zero, and the phase is lengthened.

The signal output from VC023 is divided into 1 by frequency divider 3.
/n divided and synchronized to the input pilot signal 3 8
A subcarrier signal component of K I-1z is obtained, and after being waveform-shaped by a waveform shaping circuit 4, it is output as a subcarrier signal (sine wave signal or rectangular wave signal). This P
As the VCO 23 of the LL circuit 2, a CR using an IC etc.
This type of oscillation circuit has the advantage of wide capture range and lock range when operated as a PLL.

(Problems to be Solved by the Invention) Subcarriers are generated by the conventional FM stereo demodulation PLL circuit as described above.

However, since the VCO 23 is constituted by a CR-type oscillation circuit using an IC or the like, when it is operated as a PLL circuit, frequency fluctuations (jitter) may occur.
It just follows the KHz pilot signal.

In other words, the pilot signal included in the FM composite signal is originally a single wave of 19 KHz, or it is affected by harmonics of the modulation signal, and it is also affected by multipath interference depending on the field conditions, so it may be slightly distorted. The received pilot signal fluctuates in frequency.

Therefore, the pilot/to (
If a subcarrier signal is output from a PLL circuit following No. 3, there are problems such as noise problems and deterioration of stereo demodulation characteristics such as channel separation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL circuit for FM stereo demodulation that can reduce frequency fluctuations of subcarriers and obtain stable stereo demodulation characteristics.

(Means for Solving the Problems) In order to solve the above-mentioned problems, a PLL circuit for FNl stereo demodulation according to the present invention includes a first PLL circuit that extracts a pilot signal from an FM composite signal and outputs a subcarrier signal component. and a second PLL circuit configured to control the oscillation frequency from the crystal oscillator by comparing the phases of the subcarrier signal component from the first PLL circuit and the oscillation frequency signal from the crystal oscillator; and is configured to output the output from the second PLL circuit as a subcarrier signal.

(Function) The PLL circuit for FM stereo demodulation according to the present invention inputs subcarrier signal components extracted and generated by a normal PLL circuit to a PLL circuit that uses a crystal oscillator with low PLL response as an oscillation section. , is configured to reduce the influence of frequency fluctuations (jitter) on subcarrier signals.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a PLL circuit for FM stereo demodulation according to the present invention.

In FIG. 1, components indicated by the same reference numerals as in FIG. 3 are components that perform the same functions.

That is, the pilot signal with a frequency near 19 KHz detected by the pilot signal detection circuit 1 from the FM composite signal received in FM stereo reception is processed by the PLL.
The signal is input to a phase comparator 21 that constitutes the circuit 2.

The phase comparator 21 compares the phase of the pilot signal with a frequency-divided signal whose oscillation frequency is not divided by the frequency divider 22 from the VCO 23, and passes the phase difference signal to the low-pass filter 24.
supply to.

The oscillation frequency of VC023 is controlled by the low-frequency component of the phase difference signal obtained by the low-pass filter 24, and VC0
23 outputs a subcarrier signal component (38xnKHz). This subcarrier signal component is frequency-divided by 1/n by the frequency divider 3 to obtain a 38 KHz subcarrier signal.

By the way, as mentioned above, the VC○ constituting the PLL circuit 2
Since 23 uses a CR type oscillation circuit, subcarrier signal components affected by frequency fluctuations are output from frequency divider 3.

In this invention, the influence of this frequency fluctuation constitutes the following:
A PLL circuit 5 using a crystal oscillator is provided on the output side of the frequency divider 3.

That is, as an oscillation circuit that generates 5 PLL times B, for example, a crystal oscillator (X'tal) with an oscillation frequency of 38 KHz is used.
An oscillation controller (~'
cx○: Volajage Controlled X
52 controls the output frequency.

The phase comparator 51 compares the phases of the divided output from the frequency divider 3 (subcarrier signal components affected by frequency fluctuations) and the oscillation signal from the crystal oscillator 52, and sends the phase difference signal to the low-pass filter 53. Send.

The low-pass filter 53 extracts the low-frequency component of the phase difference signal sent from the phase comparator 51 and supplies it to the oscillation controller 52 as an oscillation frequency control signal.

By the way, the crystal oscillator X'tal by the oscillation controller 52
The control of the oscillation frequency has lower sensitivity (VC○ sensitivity) than that of the CR type oscillator. Therefore, P of PLL circuit 5
Since the responsiveness of the LL is slowed down, the influence of the frequency fluctuation on the subcarrier component signal from the frequency divider 3, which is affected by the frequency fluctuation, is reduced.

In this way, a 38 KHz subcarrier signal component with reduced effects of frequency fluctuations (jitter) is obtained from the PLL circuit 5. The output from the PLL circuit 5 is waveform-shaped by the waveform shaping circuit 4, and a 38 KHz subcarrier signal is output.

FIG. 2 shows another example of the configuration of the PLL circuit 5 shown in FIG. 1. This configuration example improves the problem that when the crystal oscillator is operated in a relatively low frequency band of 38 KHz as shown in FIG. 1, the frequency variable band is small.

This circuit consists of a crystal oscillator X'tal and an oscillation control section (V
CXO) 54, n times the frequency 1 e.g. 38X12
By using a crystal oscillator 3 with a frequency of 8 = 4.864 (MHz) and dividing the frequency by n by a frequency divider 55 and supplying it to the phase comparator 51, it is possible to achieve a relatively large variable width (approximately ±200 ppm). There is.

(Effects of the Invention) As explained above, in the present invention, subcarrier signal components affected by frequency fluctuations obtained by a PLL circuit are By passing it through a PLL circuit with low responsiveness, it is possible to generate a subcarrier signal that reduces the influence of frequency fluctuations.Therefore, not only stable stereo demodulation is possible, but also dynamic Channel separation has been improved, allowing you to get better quality playback sound.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an FM stereo demodulation PLL circuit according to the present invention, FIG. 2 is a partial block diagram showing another embodiment of the invention, and FIG. 3 is a block diagram of a conventional FM stereo demodulation PLL circuit.
FIG. 2 is a block diagram of a PLL circuit for stereo demodulation. 1. Pilot signal detection circuit, 2.5. PLL circuit, 3. Frequency divider, 4. Waveform shaping circuit, 21.51 Phase comparator, 22
゜55・Frequency divider, 23...VCOl 24゜52゜53・54・Low pass filter, oscillation control section. Figure 1 Figure 2

Claims (1)

[Claims] A first PLL circuit that extracts a pilot signal from an FM composite signal and outputs a subcarrier signal component; and a subcarrier signal component from the first PLL circuit and an oscillation frequency signal from a crystal oscillator. a second PLL circuit configured to control the oscillation frequency from the crystal oscillator by comparing the phases thereof, and extracting the output from the second PLL circuit as a subcarrier signal. PLL circuit for FM stereo demodulation.